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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV32IM %s3; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV64IM %s4; RUN: llc -mtriple=riscv64 -mattr=+m,+xventanacondops -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV64IMXVTCONDOPS %s5; RUN: llc -mtriple=riscv32 -mattr=+m,+zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECKZICOND,RV32IMZICOND %s6; RUN: llc -mtriple=riscv64 -mattr=+m,+zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECKZICOND,RV64IMZICOND %s7; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \8; RUN: | FileCheck %s --check-prefixes=RV32IXQCI9 10define i16 @select_xor_1(i16 %A, i8 %cond) {11; RV32IM-LABEL: select_xor_1:12; RV32IM: # %bb.0: # %entry13; RV32IM-NEXT: slli a1, a1, 3114; RV32IM-NEXT: srai a1, a1, 3115; RV32IM-NEXT: andi a1, a1, 4316; RV32IM-NEXT: xor a0, a0, a117; RV32IM-NEXT: ret18;19; RV64IM-LABEL: select_xor_1:20; RV64IM: # %bb.0: # %entry21; RV64IM-NEXT: slli a1, a1, 6322; RV64IM-NEXT: srai a1, a1, 6323; RV64IM-NEXT: andi a1, a1, 4324; RV64IM-NEXT: xor a0, a0, a125; RV64IM-NEXT: ret26;27; RV64IMXVTCONDOPS-LABEL: select_xor_1:28; RV64IMXVTCONDOPS: # %bb.0: # %entry29; RV64IMXVTCONDOPS-NEXT: andi a1, a1, 130; RV64IMXVTCONDOPS-NEXT: seqz a1, a131; RV64IMXVTCONDOPS-NEXT: addi a1, a1, -132; RV64IMXVTCONDOPS-NEXT: andi a1, a1, 4333; RV64IMXVTCONDOPS-NEXT: xor a0, a0, a134; RV64IMXVTCONDOPS-NEXT: ret35;36; CHECKZICOND-LABEL: select_xor_1:37; CHECKZICOND: # %bb.0: # %entry38; CHECKZICOND-NEXT: andi a1, a1, 139; CHECKZICOND-NEXT: seqz a1, a140; CHECKZICOND-NEXT: addi a1, a1, -141; CHECKZICOND-NEXT: andi a1, a1, 4342; CHECKZICOND-NEXT: xor a0, a0, a143; CHECKZICOND-NEXT: ret44;45; RV32IXQCI-LABEL: select_xor_1:46; RV32IXQCI: # %bb.0: # %entry47; RV32IXQCI-NEXT: andi a1, a1, 148; RV32IXQCI-NEXT: beqz a1, .LBB0_249; RV32IXQCI-NEXT: # %bb.1: # %entry50; RV32IXQCI-NEXT: xori a0, a0, 4351; RV32IXQCI-NEXT: .LBB0_2: # %entry52; RV32IXQCI-NEXT: ret53entry:54 %and = and i8 %cond, 155 %cmp10 = icmp eq i8 %and, 056 %0 = xor i16 %A, 4357 %1 = select i1 %cmp10, i16 %A, i16 %058 ret i16 %159}60 61; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of62; icmp eq (and %cond, 1), 063define i16 @select_xor_1b(i16 %A, i8 %cond) {64; RV32IM-LABEL: select_xor_1b:65; RV32IM: # %bb.0: # %entry66; RV32IM-NEXT: slli a1, a1, 3167; RV32IM-NEXT: srai a1, a1, 3168; RV32IM-NEXT: andi a1, a1, 4369; RV32IM-NEXT: xor a0, a0, a170; RV32IM-NEXT: ret71;72; RV64IM-LABEL: select_xor_1b:73; RV64IM: # %bb.0: # %entry74; RV64IM-NEXT: slli a1, a1, 6375; RV64IM-NEXT: srai a1, a1, 6376; RV64IM-NEXT: andi a1, a1, 4377; RV64IM-NEXT: xor a0, a0, a178; RV64IM-NEXT: ret79;80; RV64IMXVTCONDOPS-LABEL: select_xor_1b:81; RV64IMXVTCONDOPS: # %bb.0: # %entry82; RV64IMXVTCONDOPS-NEXT: slli a1, a1, 6383; RV64IMXVTCONDOPS-NEXT: srai a1, a1, 6384; RV64IMXVTCONDOPS-NEXT: andi a1, a1, 4385; RV64IMXVTCONDOPS-NEXT: xor a0, a0, a186; RV64IMXVTCONDOPS-NEXT: ret87;88; RV32IMZICOND-LABEL: select_xor_1b:89; RV32IMZICOND: # %bb.0: # %entry90; RV32IMZICOND-NEXT: slli a1, a1, 3191; RV32IMZICOND-NEXT: srai a1, a1, 3192; RV32IMZICOND-NEXT: andi a1, a1, 4393; RV32IMZICOND-NEXT: xor a0, a0, a194; RV32IMZICOND-NEXT: ret95;96; RV64IMZICOND-LABEL: select_xor_1b:97; RV64IMZICOND: # %bb.0: # %entry98; RV64IMZICOND-NEXT: slli a1, a1, 6399; RV64IMZICOND-NEXT: srai a1, a1, 63100; RV64IMZICOND-NEXT: andi a1, a1, 43101; RV64IMZICOND-NEXT: xor a0, a0, a1102; RV64IMZICOND-NEXT: ret103;104; RV32IXQCI-LABEL: select_xor_1b:105; RV32IXQCI: # %bb.0: # %entry106; RV32IXQCI-NEXT: andi a1, a1, 1107; RV32IXQCI-NEXT: beqz a1, .LBB1_2108; RV32IXQCI-NEXT: # %bb.1: # %entry109; RV32IXQCI-NEXT: xori a0, a0, 43110; RV32IXQCI-NEXT: .LBB1_2: # %entry111; RV32IXQCI-NEXT: ret112entry:113 %and = and i8 %cond, 1114 %cmp10 = icmp ne i8 %and, 1115 %0 = xor i16 %A, 43116 %1 = select i1 %cmp10, i16 %A, i16 %0117 ret i16 %1118}119 120define i32 @select_xor_2(i32 %A, i32 %B, i8 %cond) {121; RV32IM-LABEL: select_xor_2:122; RV32IM: # %bb.0: # %entry123; RV32IM-NEXT: slli a2, a2, 31124; RV32IM-NEXT: srai a2, a2, 31125; RV32IM-NEXT: and a1, a2, a1126; RV32IM-NEXT: xor a0, a0, a1127; RV32IM-NEXT: ret128;129; RV64IM-LABEL: select_xor_2:130; RV64IM: # %bb.0: # %entry131; RV64IM-NEXT: slli a2, a2, 63132; RV64IM-NEXT: srai a2, a2, 63133; RV64IM-NEXT: and a1, a2, a1134; RV64IM-NEXT: xor a0, a0, a1135; RV64IM-NEXT: ret136;137; RV64IMXVTCONDOPS-LABEL: select_xor_2:138; RV64IMXVTCONDOPS: # %bb.0: # %entry139; RV64IMXVTCONDOPS-NEXT: andi a2, a2, 1140; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a2141; RV64IMXVTCONDOPS-NEXT: xor a0, a0, a1142; RV64IMXVTCONDOPS-NEXT: ret143;144; CHECKZICOND-LABEL: select_xor_2:145; CHECKZICOND: # %bb.0: # %entry146; CHECKZICOND-NEXT: andi a2, a2, 1147; CHECKZICOND-NEXT: czero.eqz a1, a1, a2148; CHECKZICOND-NEXT: xor a0, a0, a1149; CHECKZICOND-NEXT: ret150;151; RV32IXQCI-LABEL: select_xor_2:152; RV32IXQCI: # %bb.0: # %entry153; RV32IXQCI-NEXT: andi a2, a2, 1154; RV32IXQCI-NEXT: beqz a2, .LBB2_2155; RV32IXQCI-NEXT: # %bb.1: # %entry156; RV32IXQCI-NEXT: xor a0, a0, a1157; RV32IXQCI-NEXT: .LBB2_2: # %entry158; RV32IXQCI-NEXT: ret159entry:160 %and = and i8 %cond, 1161 %cmp10 = icmp eq i8 %and, 0162 %0 = xor i32 %B, %A163 %1 = select i1 %cmp10, i32 %A, i32 %0164 ret i32 %1165}166 167; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of168; icmp eq (and %cond, 1), 0169define i32 @select_xor_2b(i32 %A, i32 %B, i8 %cond) {170; RV32IM-LABEL: select_xor_2b:171; RV32IM: # %bb.0: # %entry172; RV32IM-NEXT: slli a2, a2, 31173; RV32IM-NEXT: srai a2, a2, 31174; RV32IM-NEXT: and a1, a2, a1175; RV32IM-NEXT: xor a0, a0, a1176; RV32IM-NEXT: ret177;178; RV64IM-LABEL: select_xor_2b:179; RV64IM: # %bb.0: # %entry180; RV64IM-NEXT: slli a2, a2, 63181; RV64IM-NEXT: srai a2, a2, 63182; RV64IM-NEXT: and a1, a2, a1183; RV64IM-NEXT: xor a0, a0, a1184; RV64IM-NEXT: ret185;186; RV64IMXVTCONDOPS-LABEL: select_xor_2b:187; RV64IMXVTCONDOPS: # %bb.0: # %entry188; RV64IMXVTCONDOPS-NEXT: andi a2, a2, 1189; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a2190; RV64IMXVTCONDOPS-NEXT: xor a0, a0, a1191; RV64IMXVTCONDOPS-NEXT: ret192;193; CHECKZICOND-LABEL: select_xor_2b:194; CHECKZICOND: # %bb.0: # %entry195; CHECKZICOND-NEXT: andi a2, a2, 1196; CHECKZICOND-NEXT: czero.eqz a1, a1, a2197; CHECKZICOND-NEXT: xor a0, a0, a1198; CHECKZICOND-NEXT: ret199;200; RV32IXQCI-LABEL: select_xor_2b:201; RV32IXQCI: # %bb.0: # %entry202; RV32IXQCI-NEXT: andi a2, a2, 1203; RV32IXQCI-NEXT: beqz a2, .LBB3_2204; RV32IXQCI-NEXT: # %bb.1: # %entry205; RV32IXQCI-NEXT: xor a0, a0, a1206; RV32IXQCI-NEXT: .LBB3_2: # %entry207; RV32IXQCI-NEXT: ret208entry:209 %and = and i8 %cond, 1210 %cmp10 = icmp ne i8 %and, 1211 %0 = xor i32 %B, %A212 %1 = select i1 %cmp10, i32 %A, i32 %0213 ret i32 %1214}215 216define i16 @select_xor_3(i16 %A, i8 %cond) {217; CHECK-LABEL: select_xor_3:218; CHECK: # %bb.0: # %entry219; CHECK-NEXT: andi a1, a1, 1220; CHECK-NEXT: addi a1, a1, -1221; CHECK-NEXT: andi a1, a1, 43222; CHECK-NEXT: xor a0, a0, a1223; CHECK-NEXT: ret224;225; RV32IXQCI-LABEL: select_xor_3:226; RV32IXQCI: # %bb.0: # %entry227; RV32IXQCI-NEXT: andi a1, a1, 1228; RV32IXQCI-NEXT: bnez a1, .LBB4_2229; RV32IXQCI-NEXT: # %bb.1: # %entry230; RV32IXQCI-NEXT: xori a0, a0, 43231; RV32IXQCI-NEXT: .LBB4_2: # %entry232; RV32IXQCI-NEXT: ret233entry:234 %and = and i8 %cond, 1235 %cmp10 = icmp eq i8 %and, 0236 %0 = xor i16 %A, 43237 %1 = select i1 %cmp10, i16 %0, i16 %A238 ret i16 %1239}240 241; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of242; icmp eq (and %cond, 1), 0243define i16 @select_xor_3b(i16 %A, i8 %cond) {244; CHECK-LABEL: select_xor_3b:245; CHECK: # %bb.0: # %entry246; CHECK-NEXT: andi a1, a1, 1247; CHECK-NEXT: addi a1, a1, -1248; CHECK-NEXT: andi a1, a1, 43249; CHECK-NEXT: xor a0, a0, a1250; CHECK-NEXT: ret251;252; RV32IXQCI-LABEL: select_xor_3b:253; RV32IXQCI: # %bb.0: # %entry254; RV32IXQCI-NEXT: andi a1, a1, 1255; RV32IXQCI-NEXT: bnez a1, .LBB5_2256; RV32IXQCI-NEXT: # %bb.1: # %entry257; RV32IXQCI-NEXT: xori a0, a0, 43258; RV32IXQCI-NEXT: .LBB5_2: # %entry259; RV32IXQCI-NEXT: ret260entry:261 %and = and i8 %cond, 1262 %cmp10 = icmp ne i8 %and, 1263 %0 = xor i16 %A, 43264 %1 = select i1 %cmp10, i16 %0, i16 %A265 ret i16 %1266}267 268define i32 @select_xor_4(i32 %A, i32 %B, i8 %cond) {269; RV32IM-LABEL: select_xor_4:270; RV32IM: # %bb.0: # %entry271; RV32IM-NEXT: andi a2, a2, 1272; RV32IM-NEXT: addi a2, a2, -1273; RV32IM-NEXT: and a1, a2, a1274; RV32IM-NEXT: xor a0, a0, a1275; RV32IM-NEXT: ret276;277; RV64IM-LABEL: select_xor_4:278; RV64IM: # %bb.0: # %entry279; RV64IM-NEXT: andi a2, a2, 1280; RV64IM-NEXT: addi a2, a2, -1281; RV64IM-NEXT: and a1, a2, a1282; RV64IM-NEXT: xor a0, a0, a1283; RV64IM-NEXT: ret284;285; RV64IMXVTCONDOPS-LABEL: select_xor_4:286; RV64IMXVTCONDOPS: # %bb.0: # %entry287; RV64IMXVTCONDOPS-NEXT: andi a2, a2, 1288; RV64IMXVTCONDOPS-NEXT: vt.maskcn a1, a1, a2289; RV64IMXVTCONDOPS-NEXT: xor a0, a0, a1290; RV64IMXVTCONDOPS-NEXT: ret291;292; CHECKZICOND-LABEL: select_xor_4:293; CHECKZICOND: # %bb.0: # %entry294; CHECKZICOND-NEXT: andi a2, a2, 1295; CHECKZICOND-NEXT: czero.nez a1, a1, a2296; CHECKZICOND-NEXT: xor a0, a0, a1297; CHECKZICOND-NEXT: ret298;299; RV32IXQCI-LABEL: select_xor_4:300; RV32IXQCI: # %bb.0: # %entry301; RV32IXQCI-NEXT: andi a2, a2, 1302; RV32IXQCI-NEXT: bnez a2, .LBB6_2303; RV32IXQCI-NEXT: # %bb.1: # %entry304; RV32IXQCI-NEXT: xor a0, a0, a1305; RV32IXQCI-NEXT: .LBB6_2: # %entry306; RV32IXQCI-NEXT: ret307entry:308 %and = and i8 %cond, 1309 %cmp10 = icmp eq i8 %and, 0310 %0 = xor i32 %B, %A311 %1 = select i1 %cmp10, i32 %0, i32 %A312 ret i32 %1313}314 315; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of316; icmp eq (and %cond, 1), 0317define i32 @select_xor_4b(i32 %A, i32 %B, i8 %cond) {318; RV32IM-LABEL: select_xor_4b:319; RV32IM: # %bb.0: # %entry320; RV32IM-NEXT: andi a2, a2, 1321; RV32IM-NEXT: addi a2, a2, -1322; RV32IM-NEXT: and a1, a2, a1323; RV32IM-NEXT: xor a0, a0, a1324; RV32IM-NEXT: ret325;326; RV64IM-LABEL: select_xor_4b:327; RV64IM: # %bb.0: # %entry328; RV64IM-NEXT: andi a2, a2, 1329; RV64IM-NEXT: addi a2, a2, -1330; RV64IM-NEXT: and a1, a2, a1331; RV64IM-NEXT: xor a0, a0, a1332; RV64IM-NEXT: ret333;334; RV64IMXVTCONDOPS-LABEL: select_xor_4b:335; RV64IMXVTCONDOPS: # %bb.0: # %entry336; RV64IMXVTCONDOPS-NEXT: andi a2, a2, 1337; RV64IMXVTCONDOPS-NEXT: vt.maskcn a1, a1, a2338; RV64IMXVTCONDOPS-NEXT: xor a0, a0, a1339; RV64IMXVTCONDOPS-NEXT: ret340;341; CHECKZICOND-LABEL: select_xor_4b:342; CHECKZICOND: # %bb.0: # %entry343; CHECKZICOND-NEXT: andi a2, a2, 1344; CHECKZICOND-NEXT: czero.nez a1, a1, a2345; CHECKZICOND-NEXT: xor a0, a0, a1346; CHECKZICOND-NEXT: ret347;348; RV32IXQCI-LABEL: select_xor_4b:349; RV32IXQCI: # %bb.0: # %entry350; RV32IXQCI-NEXT: andi a2, a2, 1351; RV32IXQCI-NEXT: bnez a2, .LBB7_2352; RV32IXQCI-NEXT: # %bb.1: # %entry353; RV32IXQCI-NEXT: xor a0, a0, a1354; RV32IXQCI-NEXT: .LBB7_2: # %entry355; RV32IXQCI-NEXT: ret356entry:357 %and = and i8 %cond, 1358 %cmp10 = icmp ne i8 %and, 1359 %0 = xor i32 %B, %A360 %1 = select i1 %cmp10, i32 %0, i32 %A361 ret i32 %1362}363 364define i32 @select_xor_5(i1 zeroext %cond, i32 %x) {365; RV32IM-LABEL: select_xor_5:366; RV32IM: # %bb.0:367; RV32IM-NEXT: addi a0, a0, -1368; RV32IM-NEXT: and a0, a0, a1369; RV32IM-NEXT: xori a0, a0, 128370; RV32IM-NEXT: ret371;372; RV64IM-LABEL: select_xor_5:373; RV64IM: # %bb.0:374; RV64IM-NEXT: addi a0, a0, -1375; RV64IM-NEXT: and a0, a0, a1376; RV64IM-NEXT: xori a0, a0, 128377; RV64IM-NEXT: ret378;379; RV64IMXVTCONDOPS-LABEL: select_xor_5:380; RV64IMXVTCONDOPS: # %bb.0:381; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0382; RV64IMXVTCONDOPS-NEXT: xori a0, a0, 128383; RV64IMXVTCONDOPS-NEXT: ret384;385; CHECKZICOND-LABEL: select_xor_5:386; CHECKZICOND: # %bb.0:387; CHECKZICOND-NEXT: czero.nez a0, a1, a0388; CHECKZICOND-NEXT: xori a0, a0, 128389; CHECKZICOND-NEXT: ret390;391; RV32IXQCI-LABEL: select_xor_5:392; RV32IXQCI: # %bb.0:393; RV32IXQCI-NEXT: li a2, 128394; RV32IXQCI-NEXT: bnez a0, .LBB8_2395; RV32IXQCI-NEXT: # %bb.1:396; RV32IXQCI-NEXT: xori a2, a1, 128397; RV32IXQCI-NEXT: .LBB8_2:398; RV32IXQCI-NEXT: mv a0, a2399; RV32IXQCI-NEXT: ret400 %add = xor i32 %x, 128401 %sel = select i1 %cond, i32 128, i32 %add402 ret i32 %sel403}404 405define i32 @select_or(i32 %A, i32 %B, i8 %cond) {406; RV32IM-LABEL: select_or:407; RV32IM: # %bb.0: # %entry408; RV32IM-NEXT: slli a2, a2, 31409; RV32IM-NEXT: srai a2, a2, 31410; RV32IM-NEXT: and a1, a2, a1411; RV32IM-NEXT: or a0, a0, a1412; RV32IM-NEXT: ret413;414; RV64IM-LABEL: select_or:415; RV64IM: # %bb.0: # %entry416; RV64IM-NEXT: slli a2, a2, 63417; RV64IM-NEXT: srai a2, a2, 63418; RV64IM-NEXT: and a1, a2, a1419; RV64IM-NEXT: or a0, a0, a1420; RV64IM-NEXT: ret421;422; RV64IMXVTCONDOPS-LABEL: select_or:423; RV64IMXVTCONDOPS: # %bb.0: # %entry424; RV64IMXVTCONDOPS-NEXT: andi a2, a2, 1425; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a2426; RV64IMXVTCONDOPS-NEXT: or a0, a0, a1427; RV64IMXVTCONDOPS-NEXT: ret428;429; CHECKZICOND-LABEL: select_or:430; CHECKZICOND: # %bb.0: # %entry431; CHECKZICOND-NEXT: andi a2, a2, 1432; CHECKZICOND-NEXT: czero.eqz a1, a1, a2433; CHECKZICOND-NEXT: or a0, a0, a1434; CHECKZICOND-NEXT: ret435;436; RV32IXQCI-LABEL: select_or:437; RV32IXQCI: # %bb.0: # %entry438; RV32IXQCI-NEXT: andi a2, a2, 1439; RV32IXQCI-NEXT: beqz a2, .LBB9_2440; RV32IXQCI-NEXT: # %bb.1: # %entry441; RV32IXQCI-NEXT: or a0, a0, a1442; RV32IXQCI-NEXT: .LBB9_2: # %entry443; RV32IXQCI-NEXT: ret444entry:445 %and = and i8 %cond, 1446 %cmp10 = icmp eq i8 %and, 0447 %0 = or i32 %B, %A448 %1 = select i1 %cmp10, i32 %A, i32 %0449 ret i32 %1450}451 452; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of453; icmp eq (and %cond, 1), 0454define i32 @select_or_b(i32 %A, i32 %B, i8 %cond) {455; RV32IM-LABEL: select_or_b:456; RV32IM: # %bb.0: # %entry457; RV32IM-NEXT: slli a2, a2, 31458; RV32IM-NEXT: srai a2, a2, 31459; RV32IM-NEXT: and a1, a2, a1460; RV32IM-NEXT: or a0, a0, a1461; RV32IM-NEXT: ret462;463; RV64IM-LABEL: select_or_b:464; RV64IM: # %bb.0: # %entry465; RV64IM-NEXT: slli a2, a2, 63466; RV64IM-NEXT: srai a2, a2, 63467; RV64IM-NEXT: and a1, a2, a1468; RV64IM-NEXT: or a0, a0, a1469; RV64IM-NEXT: ret470;471; RV64IMXVTCONDOPS-LABEL: select_or_b:472; RV64IMXVTCONDOPS: # %bb.0: # %entry473; RV64IMXVTCONDOPS-NEXT: andi a2, a2, 1474; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a2475; RV64IMXVTCONDOPS-NEXT: or a0, a0, a1476; RV64IMXVTCONDOPS-NEXT: ret477;478; CHECKZICOND-LABEL: select_or_b:479; CHECKZICOND: # %bb.0: # %entry480; CHECKZICOND-NEXT: andi a2, a2, 1481; CHECKZICOND-NEXT: czero.eqz a1, a1, a2482; CHECKZICOND-NEXT: or a0, a0, a1483; CHECKZICOND-NEXT: ret484;485; RV32IXQCI-LABEL: select_or_b:486; RV32IXQCI: # %bb.0: # %entry487; RV32IXQCI-NEXT: andi a2, a2, 1488; RV32IXQCI-NEXT: beqz a2, .LBB10_2489; RV32IXQCI-NEXT: # %bb.1: # %entry490; RV32IXQCI-NEXT: or a0, a0, a1491; RV32IXQCI-NEXT: .LBB10_2: # %entry492; RV32IXQCI-NEXT: ret493entry:494 %and = and i8 %cond, 1495 %cmp10 = icmp ne i8 %and, 1496 %0 = or i32 %B, %A497 %1 = select i1 %cmp10, i32 %A, i32 %0498 ret i32 %1499}500 501define i32 @select_or_1(i32 %A, i32 %B, i32 %cond) {502; RV32IM-LABEL: select_or_1:503; RV32IM: # %bb.0: # %entry504; RV32IM-NEXT: slli a2, a2, 31505; RV32IM-NEXT: srai a2, a2, 31506; RV32IM-NEXT: and a1, a2, a1507; RV32IM-NEXT: or a0, a0, a1508; RV32IM-NEXT: ret509;510; RV64IM-LABEL: select_or_1:511; RV64IM: # %bb.0: # %entry512; RV64IM-NEXT: slli a2, a2, 63513; RV64IM-NEXT: srai a2, a2, 63514; RV64IM-NEXT: and a1, a2, a1515; RV64IM-NEXT: or a0, a0, a1516; RV64IM-NEXT: ret517;518; RV64IMXVTCONDOPS-LABEL: select_or_1:519; RV64IMXVTCONDOPS: # %bb.0: # %entry520; RV64IMXVTCONDOPS-NEXT: andi a2, a2, 1521; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a2522; RV64IMXVTCONDOPS-NEXT: or a0, a0, a1523; RV64IMXVTCONDOPS-NEXT: ret524;525; CHECKZICOND-LABEL: select_or_1:526; CHECKZICOND: # %bb.0: # %entry527; CHECKZICOND-NEXT: andi a2, a2, 1528; CHECKZICOND-NEXT: czero.eqz a1, a1, a2529; CHECKZICOND-NEXT: or a0, a0, a1530; CHECKZICOND-NEXT: ret531;532; RV32IXQCI-LABEL: select_or_1:533; RV32IXQCI: # %bb.0: # %entry534; RV32IXQCI-NEXT: andi a2, a2, 1535; RV32IXQCI-NEXT: beqz a2, .LBB11_2536; RV32IXQCI-NEXT: # %bb.1: # %entry537; RV32IXQCI-NEXT: or a0, a0, a1538; RV32IXQCI-NEXT: .LBB11_2: # %entry539; RV32IXQCI-NEXT: ret540entry:541 %and = and i32 %cond, 1542 %cmp10 = icmp eq i32 %and, 0543 %0 = or i32 %B, %A544 %1 = select i1 %cmp10, i32 %A, i32 %0545 ret i32 %1546}547 548; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of549; icmp eq (and %cond, 1), 0550define i32 @select_or_1b(i32 %A, i32 %B, i32 %cond) {551; RV32IM-LABEL: select_or_1b:552; RV32IM: # %bb.0: # %entry553; RV32IM-NEXT: slli a2, a2, 31554; RV32IM-NEXT: srai a2, a2, 31555; RV32IM-NEXT: and a1, a2, a1556; RV32IM-NEXT: or a0, a0, a1557; RV32IM-NEXT: ret558;559; RV64IM-LABEL: select_or_1b:560; RV64IM: # %bb.0: # %entry561; RV64IM-NEXT: slli a2, a2, 63562; RV64IM-NEXT: srai a2, a2, 63563; RV64IM-NEXT: and a1, a2, a1564; RV64IM-NEXT: or a0, a0, a1565; RV64IM-NEXT: ret566;567; RV64IMXVTCONDOPS-LABEL: select_or_1b:568; RV64IMXVTCONDOPS: # %bb.0: # %entry569; RV64IMXVTCONDOPS-NEXT: andi a2, a2, 1570; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a2571; RV64IMXVTCONDOPS-NEXT: or a0, a0, a1572; RV64IMXVTCONDOPS-NEXT: ret573;574; CHECKZICOND-LABEL: select_or_1b:575; CHECKZICOND: # %bb.0: # %entry576; CHECKZICOND-NEXT: andi a2, a2, 1577; CHECKZICOND-NEXT: czero.eqz a1, a1, a2578; CHECKZICOND-NEXT: or a0, a0, a1579; CHECKZICOND-NEXT: ret580;581; RV32IXQCI-LABEL: select_or_1b:582; RV32IXQCI: # %bb.0: # %entry583; RV32IXQCI-NEXT: andi a2, a2, 1584; RV32IXQCI-NEXT: beqz a2, .LBB12_2585; RV32IXQCI-NEXT: # %bb.1: # %entry586; RV32IXQCI-NEXT: or a0, a0, a1587; RV32IXQCI-NEXT: .LBB12_2: # %entry588; RV32IXQCI-NEXT: ret589entry:590 %and = and i32 %cond, 1591 %cmp10 = icmp ne i32 %and, 1592 %0 = or i32 %B, %A593 %1 = select i1 %cmp10, i32 %A, i32 %0594 ret i32 %1595}596 597define i32 @select_or_2(i32 %A, i32 %B, i8 %cond) {598; RV32IM-LABEL: select_or_2:599; RV32IM: # %bb.0: # %entry600; RV32IM-NEXT: andi a2, a2, 1601; RV32IM-NEXT: addi a2, a2, -1602; RV32IM-NEXT: and a1, a2, a1603; RV32IM-NEXT: or a0, a0, a1604; RV32IM-NEXT: ret605;606; RV64IM-LABEL: select_or_2:607; RV64IM: # %bb.0: # %entry608; RV64IM-NEXT: andi a2, a2, 1609; RV64IM-NEXT: addi a2, a2, -1610; RV64IM-NEXT: and a1, a2, a1611; RV64IM-NEXT: or a0, a0, a1612; RV64IM-NEXT: ret613;614; RV64IMXVTCONDOPS-LABEL: select_or_2:615; RV64IMXVTCONDOPS: # %bb.0: # %entry616; RV64IMXVTCONDOPS-NEXT: andi a2, a2, 1617; RV64IMXVTCONDOPS-NEXT: vt.maskcn a1, a1, a2618; RV64IMXVTCONDOPS-NEXT: or a0, a0, a1619; RV64IMXVTCONDOPS-NEXT: ret620;621; CHECKZICOND-LABEL: select_or_2:622; CHECKZICOND: # %bb.0: # %entry623; CHECKZICOND-NEXT: andi a2, a2, 1624; CHECKZICOND-NEXT: czero.nez a1, a1, a2625; CHECKZICOND-NEXT: or a0, a0, a1626; CHECKZICOND-NEXT: ret627;628; RV32IXQCI-LABEL: select_or_2:629; RV32IXQCI: # %bb.0: # %entry630; RV32IXQCI-NEXT: andi a2, a2, 1631; RV32IXQCI-NEXT: bnez a2, .LBB13_2632; RV32IXQCI-NEXT: # %bb.1: # %entry633; RV32IXQCI-NEXT: or a0, a0, a1634; RV32IXQCI-NEXT: .LBB13_2: # %entry635; RV32IXQCI-NEXT: ret636entry:637 %and = and i8 %cond, 1638 %cmp10 = icmp eq i8 %and, 0639 %0 = or i32 %B, %A640 %1 = select i1 %cmp10, i32 %0, i32 %A641 ret i32 %1642}643 644; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of645; icmp eq (and %cond, 1), 0646define i32 @select_or_2b(i32 %A, i32 %B, i8 %cond) {647; RV32IM-LABEL: select_or_2b:648; RV32IM: # %bb.0: # %entry649; RV32IM-NEXT: andi a2, a2, 1650; RV32IM-NEXT: addi a2, a2, -1651; RV32IM-NEXT: and a1, a2, a1652; RV32IM-NEXT: or a0, a0, a1653; RV32IM-NEXT: ret654;655; RV64IM-LABEL: select_or_2b:656; RV64IM: # %bb.0: # %entry657; RV64IM-NEXT: andi a2, a2, 1658; RV64IM-NEXT: addi a2, a2, -1659; RV64IM-NEXT: and a1, a2, a1660; RV64IM-NEXT: or a0, a0, a1661; RV64IM-NEXT: ret662;663; RV64IMXVTCONDOPS-LABEL: select_or_2b:664; RV64IMXVTCONDOPS: # %bb.0: # %entry665; RV64IMXVTCONDOPS-NEXT: andi a2, a2, 1666; RV64IMXVTCONDOPS-NEXT: vt.maskcn a1, a1, a2667; RV64IMXVTCONDOPS-NEXT: or a0, a0, a1668; RV64IMXVTCONDOPS-NEXT: ret669;670; CHECKZICOND-LABEL: select_or_2b:671; CHECKZICOND: # %bb.0: # %entry672; CHECKZICOND-NEXT: andi a2, a2, 1673; CHECKZICOND-NEXT: czero.nez a1, a1, a2674; CHECKZICOND-NEXT: or a0, a0, a1675; CHECKZICOND-NEXT: ret676;677; RV32IXQCI-LABEL: select_or_2b:678; RV32IXQCI: # %bb.0: # %entry679; RV32IXQCI-NEXT: andi a2, a2, 1680; RV32IXQCI-NEXT: bnez a2, .LBB14_2681; RV32IXQCI-NEXT: # %bb.1: # %entry682; RV32IXQCI-NEXT: or a0, a0, a1683; RV32IXQCI-NEXT: .LBB14_2: # %entry684; RV32IXQCI-NEXT: ret685entry:686 %and = and i8 %cond, 1687 %cmp10 = icmp ne i8 %and, 1688 %0 = or i32 %B, %A689 %1 = select i1 %cmp10, i32 %0, i32 %A690 ret i32 %1691}692 693define i32 @select_or_3(i32 %A, i32 %B, i32 %cond) {694; RV32IM-LABEL: select_or_3:695; RV32IM: # %bb.0: # %entry696; RV32IM-NEXT: andi a2, a2, 1697; RV32IM-NEXT: addi a2, a2, -1698; RV32IM-NEXT: and a1, a2, a1699; RV32IM-NEXT: or a0, a0, a1700; RV32IM-NEXT: ret701;702; RV64IM-LABEL: select_or_3:703; RV64IM: # %bb.0: # %entry704; RV64IM-NEXT: andi a2, a2, 1705; RV64IM-NEXT: addi a2, a2, -1706; RV64IM-NEXT: and a1, a2, a1707; RV64IM-NEXT: or a0, a0, a1708; RV64IM-NEXT: ret709;710; RV64IMXVTCONDOPS-LABEL: select_or_3:711; RV64IMXVTCONDOPS: # %bb.0: # %entry712; RV64IMXVTCONDOPS-NEXT: andi a2, a2, 1713; RV64IMXVTCONDOPS-NEXT: vt.maskcn a1, a1, a2714; RV64IMXVTCONDOPS-NEXT: or a0, a0, a1715; RV64IMXVTCONDOPS-NEXT: ret716;717; CHECKZICOND-LABEL: select_or_3:718; CHECKZICOND: # %bb.0: # %entry719; CHECKZICOND-NEXT: andi a2, a2, 1720; CHECKZICOND-NEXT: czero.nez a1, a1, a2721; CHECKZICOND-NEXT: or a0, a0, a1722; CHECKZICOND-NEXT: ret723;724; RV32IXQCI-LABEL: select_or_3:725; RV32IXQCI: # %bb.0: # %entry726; RV32IXQCI-NEXT: andi a2, a2, 1727; RV32IXQCI-NEXT: bnez a2, .LBB15_2728; RV32IXQCI-NEXT: # %bb.1: # %entry729; RV32IXQCI-NEXT: or a0, a0, a1730; RV32IXQCI-NEXT: .LBB15_2: # %entry731; RV32IXQCI-NEXT: ret732entry:733 %and = and i32 %cond, 1734 %cmp10 = icmp eq i32 %and, 0735 %0 = or i32 %B, %A736 %1 = select i1 %cmp10, i32 %0, i32 %A737 ret i32 %1738}739 740; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of741; icmp eq (and %cond, 1), 0742define i32 @select_or_3b(i32 %A, i32 %B, i32 %cond) {743; RV32IM-LABEL: select_or_3b:744; RV32IM: # %bb.0: # %entry745; RV32IM-NEXT: andi a2, a2, 1746; RV32IM-NEXT: addi a2, a2, -1747; RV32IM-NEXT: and a1, a2, a1748; RV32IM-NEXT: or a0, a0, a1749; RV32IM-NEXT: ret750;751; RV64IM-LABEL: select_or_3b:752; RV64IM: # %bb.0: # %entry753; RV64IM-NEXT: andi a2, a2, 1754; RV64IM-NEXT: addi a2, a2, -1755; RV64IM-NEXT: and a1, a2, a1756; RV64IM-NEXT: or a0, a0, a1757; RV64IM-NEXT: ret758;759; RV64IMXVTCONDOPS-LABEL: select_or_3b:760; RV64IMXVTCONDOPS: # %bb.0: # %entry761; RV64IMXVTCONDOPS-NEXT: andi a2, a2, 1762; RV64IMXVTCONDOPS-NEXT: vt.maskcn a1, a1, a2763; RV64IMXVTCONDOPS-NEXT: or a0, a0, a1764; RV64IMXVTCONDOPS-NEXT: ret765;766; CHECKZICOND-LABEL: select_or_3b:767; CHECKZICOND: # %bb.0: # %entry768; CHECKZICOND-NEXT: andi a2, a2, 1769; CHECKZICOND-NEXT: czero.nez a1, a1, a2770; CHECKZICOND-NEXT: or a0, a0, a1771; CHECKZICOND-NEXT: ret772;773; RV32IXQCI-LABEL: select_or_3b:774; RV32IXQCI: # %bb.0: # %entry775; RV32IXQCI-NEXT: andi a2, a2, 1776; RV32IXQCI-NEXT: bnez a2, .LBB16_2777; RV32IXQCI-NEXT: # %bb.1: # %entry778; RV32IXQCI-NEXT: or a0, a0, a1779; RV32IXQCI-NEXT: .LBB16_2: # %entry780; RV32IXQCI-NEXT: ret781entry:782 %and = and i32 %cond, 1783 %cmp10 = icmp ne i32 %and, 1784 %0 = or i32 %B, %A785 %1 = select i1 %cmp10, i32 %0, i32 %A786 ret i32 %1787}788 789define i32 @select_or_4(i1 zeroext %cond, i32 %x) {790; RV32IM-LABEL: select_or_4:791; RV32IM: # %bb.0:792; RV32IM-NEXT: addi a0, a0, -1793; RV32IM-NEXT: and a0, a0, a1794; RV32IM-NEXT: ori a0, a0, 128795; RV32IM-NEXT: ret796;797; RV64IM-LABEL: select_or_4:798; RV64IM: # %bb.0:799; RV64IM-NEXT: addi a0, a0, -1800; RV64IM-NEXT: and a0, a0, a1801; RV64IM-NEXT: ori a0, a0, 128802; RV64IM-NEXT: ret803;804; RV64IMXVTCONDOPS-LABEL: select_or_4:805; RV64IMXVTCONDOPS: # %bb.0:806; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0807; RV64IMXVTCONDOPS-NEXT: ori a0, a0, 128808; RV64IMXVTCONDOPS-NEXT: ret809;810; CHECKZICOND-LABEL: select_or_4:811; CHECKZICOND: # %bb.0:812; CHECKZICOND-NEXT: czero.nez a0, a1, a0813; CHECKZICOND-NEXT: ori a0, a0, 128814; CHECKZICOND-NEXT: ret815;816; RV32IXQCI-LABEL: select_or_4:817; RV32IXQCI: # %bb.0:818; RV32IXQCI-NEXT: li a2, 128819; RV32IXQCI-NEXT: bnez a0, .LBB17_2820; RV32IXQCI-NEXT: # %bb.1:821; RV32IXQCI-NEXT: ori a2, a1, 128822; RV32IXQCI-NEXT: .LBB17_2:823; RV32IXQCI-NEXT: mv a0, a2824; RV32IXQCI-NEXT: ret825 %add = or i32 %x, 128826 %sel = select i1 %cond, i32 128, i32 %add827 ret i32 %sel828}829 830define i32 @select_add_1(i1 zeroext %cond, i32 %a, i32 %b) {831; RV32IM-LABEL: select_add_1:832; RV32IM: # %bb.0: # %entry833; RV32IM-NEXT: neg a0, a0834; RV32IM-NEXT: and a0, a0, a1835; RV32IM-NEXT: add a0, a2, a0836; RV32IM-NEXT: ret837;838; RV64IM-LABEL: select_add_1:839; RV64IM: # %bb.0: # %entry840; RV64IM-NEXT: neg a0, a0841; RV64IM-NEXT: and a0, a0, a1842; RV64IM-NEXT: addw a0, a2, a0843; RV64IM-NEXT: ret844;845; RV64IMXVTCONDOPS-LABEL: select_add_1:846; RV64IMXVTCONDOPS: # %bb.0: # %entry847; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a1, a0848; RV64IMXVTCONDOPS-NEXT: addw a0, a2, a0849; RV64IMXVTCONDOPS-NEXT: ret850;851; RV32IMZICOND-LABEL: select_add_1:852; RV32IMZICOND: # %bb.0: # %entry853; RV32IMZICOND-NEXT: czero.eqz a0, a1, a0854; RV32IMZICOND-NEXT: add a0, a2, a0855; RV32IMZICOND-NEXT: ret856;857; RV64IMZICOND-LABEL: select_add_1:858; RV64IMZICOND: # %bb.0: # %entry859; RV64IMZICOND-NEXT: czero.eqz a0, a1, a0860; RV64IMZICOND-NEXT: addw a0, a2, a0861; RV64IMZICOND-NEXT: ret862;863; RV32IXQCI-LABEL: select_add_1:864; RV32IXQCI: # %bb.0: # %entry865; RV32IXQCI-NEXT: beqz a0, .LBB18_2866; RV32IXQCI-NEXT: # %bb.1: # %entry867; RV32IXQCI-NEXT: add a2, a2, a1868; RV32IXQCI-NEXT: .LBB18_2: # %entry869; RV32IXQCI-NEXT: mv a0, a2870; RV32IXQCI-NEXT: ret871entry:872 %c = add i32 %a, %b873 %res = select i1 %cond, i32 %c, i32 %b874 ret i32 %res875}876 877define i32 @select_add_2(i1 zeroext %cond, i32 %a, i32 %b) {878; RV32IM-LABEL: select_add_2:879; RV32IM: # %bb.0: # %entry880; RV32IM-NEXT: addi a0, a0, -1881; RV32IM-NEXT: and a0, a0, a2882; RV32IM-NEXT: add a0, a1, a0883; RV32IM-NEXT: ret884;885; RV64IM-LABEL: select_add_2:886; RV64IM: # %bb.0: # %entry887; RV64IM-NEXT: addi a0, a0, -1888; RV64IM-NEXT: and a0, a0, a2889; RV64IM-NEXT: addw a0, a1, a0890; RV64IM-NEXT: ret891;892; RV64IMXVTCONDOPS-LABEL: select_add_2:893; RV64IMXVTCONDOPS: # %bb.0: # %entry894; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a0895; RV64IMXVTCONDOPS-NEXT: addw a0, a1, a0896; RV64IMXVTCONDOPS-NEXT: ret897;898; RV32IMZICOND-LABEL: select_add_2:899; RV32IMZICOND: # %bb.0: # %entry900; RV32IMZICOND-NEXT: czero.nez a0, a2, a0901; RV32IMZICOND-NEXT: add a0, a1, a0902; RV32IMZICOND-NEXT: ret903;904; RV64IMZICOND-LABEL: select_add_2:905; RV64IMZICOND: # %bb.0: # %entry906; RV64IMZICOND-NEXT: czero.nez a0, a2, a0907; RV64IMZICOND-NEXT: addw a0, a1, a0908; RV64IMZICOND-NEXT: ret909;910; RV32IXQCI-LABEL: select_add_2:911; RV32IXQCI: # %bb.0: # %entry912; RV32IXQCI-NEXT: bnez a0, .LBB19_2913; RV32IXQCI-NEXT: # %bb.1: # %entry914; RV32IXQCI-NEXT: add a1, a1, a2915; RV32IXQCI-NEXT: .LBB19_2: # %entry916; RV32IXQCI-NEXT: mv a0, a1917; RV32IXQCI-NEXT: ret918entry:919 %c = add i32 %a, %b920 %res = select i1 %cond, i32 %a, i32 %c921 ret i32 %res922}923 924define i32 @select_add_3(i1 zeroext %cond, i32 %a) {925; RV32IM-LABEL: select_add_3:926; RV32IM: # %bb.0: # %entry927; RV32IM-NEXT: addi a0, a0, -1928; RV32IM-NEXT: andi a0, a0, 42929; RV32IM-NEXT: add a0, a1, a0930; RV32IM-NEXT: ret931;932; RV64IM-LABEL: select_add_3:933; RV64IM: # %bb.0: # %entry934; RV64IM-NEXT: addi a0, a0, -1935; RV64IM-NEXT: andi a0, a0, 42936; RV64IM-NEXT: addw a0, a1, a0937; RV64IM-NEXT: ret938;939; RV64IMXVTCONDOPS-LABEL: select_add_3:940; RV64IMXVTCONDOPS: # %bb.0: # %entry941; RV64IMXVTCONDOPS-NEXT: addi a0, a0, -1942; RV64IMXVTCONDOPS-NEXT: andi a0, a0, 42943; RV64IMXVTCONDOPS-NEXT: addw a0, a1, a0944; RV64IMXVTCONDOPS-NEXT: ret945;946; RV32IMZICOND-LABEL: select_add_3:947; RV32IMZICOND: # %bb.0: # %entry948; RV32IMZICOND-NEXT: addi a0, a0, -1949; RV32IMZICOND-NEXT: andi a0, a0, 42950; RV32IMZICOND-NEXT: add a0, a1, a0951; RV32IMZICOND-NEXT: ret952;953; RV64IMZICOND-LABEL: select_add_3:954; RV64IMZICOND: # %bb.0: # %entry955; RV64IMZICOND-NEXT: addi a0, a0, -1956; RV64IMZICOND-NEXT: andi a0, a0, 42957; RV64IMZICOND-NEXT: addw a0, a1, a0958; RV64IMZICOND-NEXT: ret959;960; RV32IXQCI-LABEL: select_add_3:961; RV32IXQCI: # %bb.0: # %entry962; RV32IXQCI-NEXT: bnez a0, .LBB20_2963; RV32IXQCI-NEXT: # %bb.1: # %entry964; RV32IXQCI-NEXT: addi a1, a1, 42965; RV32IXQCI-NEXT: .LBB20_2: # %entry966; RV32IXQCI-NEXT: mv a0, a1967; RV32IXQCI-NEXT: ret968entry:969 %c = add i32 %a, 42970 %res = select i1 %cond, i32 %a, i32 %c971 ret i32 %res972}973 974define i32 @select_add_4(i1 zeroext %cond, i32 %x) {975; RV32IM-LABEL: select_add_4:976; RV32IM: # %bb.0:977; RV32IM-NEXT: addi a0, a0, -1978; RV32IM-NEXT: and a0, a0, a1979; RV32IM-NEXT: addi a0, a0, 128980; RV32IM-NEXT: ret981;982; RV64IM-LABEL: select_add_4:983; RV64IM: # %bb.0:984; RV64IM-NEXT: addi a0, a0, -1985; RV64IM-NEXT: and a0, a0, a1986; RV64IM-NEXT: addiw a0, a0, 128987; RV64IM-NEXT: ret988;989; RV64IMXVTCONDOPS-LABEL: select_add_4:990; RV64IMXVTCONDOPS: # %bb.0:991; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0992; RV64IMXVTCONDOPS-NEXT: addiw a0, a0, 128993; RV64IMXVTCONDOPS-NEXT: ret994;995; RV32IMZICOND-LABEL: select_add_4:996; RV32IMZICOND: # %bb.0:997; RV32IMZICOND-NEXT: czero.nez a0, a1, a0998; RV32IMZICOND-NEXT: addi a0, a0, 128999; RV32IMZICOND-NEXT: ret1000;1001; RV64IMZICOND-LABEL: select_add_4:1002; RV64IMZICOND: # %bb.0:1003; RV64IMZICOND-NEXT: czero.nez a0, a1, a01004; RV64IMZICOND-NEXT: addiw a0, a0, 1281005; RV64IMZICOND-NEXT: ret1006;1007; RV32IXQCI-LABEL: select_add_4:1008; RV32IXQCI: # %bb.0:1009; RV32IXQCI-NEXT: li a2, 1281010; RV32IXQCI-NEXT: bnez a0, .LBB21_21011; RV32IXQCI-NEXT: # %bb.1:1012; RV32IXQCI-NEXT: addi a2, a1, 1281013; RV32IXQCI-NEXT: .LBB21_2:1014; RV32IXQCI-NEXT: mv a0, a21015; RV32IXQCI-NEXT: ret1016 %add = add i32 %x, 1281017 %sel = select i1 %cond, i32 128, i32 %add1018 ret i32 %sel1019}1020 1021define i64 @select_add_5(i1 zeroext %cond, i64 %x) {1022; RV32IM-LABEL: select_add_5:1023; RV32IM: # %bb.0:1024; RV32IM-NEXT: addi a3, a0, -11025; RV32IM-NEXT: and a1, a3, a11026; RV32IM-NEXT: addi a0, a1, 1281027; RV32IM-NEXT: sltu a1, a0, a11028; RV32IM-NEXT: and a2, a3, a21029; RV32IM-NEXT: add a1, a2, a11030; RV32IM-NEXT: ret1031;1032; RV64IM-LABEL: select_add_5:1033; RV64IM: # %bb.0:1034; RV64IM-NEXT: addi a0, a0, -11035; RV64IM-NEXT: and a0, a0, a11036; RV64IM-NEXT: addi a0, a0, 1281037; RV64IM-NEXT: ret1038;1039; RV64IMXVTCONDOPS-LABEL: select_add_5:1040; RV64IMXVTCONDOPS: # %bb.0:1041; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a01042; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 1281043; RV64IMXVTCONDOPS-NEXT: ret1044;1045; RV32IMZICOND-LABEL: select_add_5:1046; RV32IMZICOND: # %bb.0:1047; RV32IMZICOND-NEXT: czero.nez a1, a1, a01048; RV32IMZICOND-NEXT: addi a3, a1, 1281049; RV32IMZICOND-NEXT: sltu a1, a3, a11050; RV32IMZICOND-NEXT: czero.nez a0, a2, a01051; RV32IMZICOND-NEXT: add a1, a0, a11052; RV32IMZICOND-NEXT: mv a0, a31053; RV32IMZICOND-NEXT: ret1054;1055; RV64IMZICOND-LABEL: select_add_5:1056; RV64IMZICOND: # %bb.0:1057; RV64IMZICOND-NEXT: czero.nez a0, a1, a01058; RV64IMZICOND-NEXT: addi a0, a0, 1281059; RV64IMZICOND-NEXT: ret1060;1061; RV32IXQCI-LABEL: select_add_5:1062; RV32IXQCI: # %bb.0:1063; RV32IXQCI-NEXT: mv a3, a01064; RV32IXQCI-NEXT: addi a4, a1, 1281065; RV32IXQCI-NEXT: sltu a0, a4, a11066; RV32IXQCI-NEXT: add a2, a2, a01067; RV32IXQCI-NEXT: li a0, 1281068; RV32IXQCI-NEXT: qc.mveqi a0, a3, 0, a41069; RV32IXQCI-NEXT: qc.selectieqi a3, 0, a2, 01070; RV32IXQCI-NEXT: mv a1, a31071; RV32IXQCI-NEXT: ret1072 %add = add i64 %x, 1281073 %sel = select i1 %cond, i64 128, i64 %add1074 ret i64 %sel1075}1076 1077define i64 @select_add_6(i1 zeroext %cond, i64 %x) {1078; RV32IM-LABEL: select_add_6:1079; RV32IM: # %bb.0:1080; RV32IM-NEXT: addi a3, a0, -11081; RV32IM-NEXT: lui a0, 141082; RV32IM-NEXT: and a1, a3, a11083; RV32IM-NEXT: addi a0, a0, 10051084; RV32IM-NEXT: add a0, a1, a01085; RV32IM-NEXT: sltu a1, a0, a11086; RV32IM-NEXT: and a2, a3, a21087; RV32IM-NEXT: add a1, a2, a11088; RV32IM-NEXT: ret1089;1090; RV64IM-LABEL: select_add_6:1091; RV64IM: # %bb.0:1092; RV64IM-NEXT: addi a0, a0, -11093; RV64IM-NEXT: and a0, a0, a11094; RV64IM-NEXT: lui a1, 141095; RV64IM-NEXT: addi a1, a1, 10051096; RV64IM-NEXT: add a0, a0, a11097; RV64IM-NEXT: ret1098;1099; RV64IMXVTCONDOPS-LABEL: select_add_6:1100; RV64IMXVTCONDOPS: # %bb.0:1101; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a01102; RV64IMXVTCONDOPS-NEXT: lui a1, 141103; RV64IMXVTCONDOPS-NEXT: addi a1, a1, 10051104; RV64IMXVTCONDOPS-NEXT: add a0, a0, a11105; RV64IMXVTCONDOPS-NEXT: ret1106;1107; RV32IMZICOND-LABEL: select_add_6:1108; RV32IMZICOND: # %bb.0:1109; RV32IMZICOND-NEXT: czero.nez a1, a1, a01110; RV32IMZICOND-NEXT: lui a3, 141111; RV32IMZICOND-NEXT: addi a3, a3, 10051112; RV32IMZICOND-NEXT: add a3, a1, a31113; RV32IMZICOND-NEXT: sltu a1, a3, a11114; RV32IMZICOND-NEXT: czero.nez a0, a2, a01115; RV32IMZICOND-NEXT: add a1, a0, a11116; RV32IMZICOND-NEXT: mv a0, a31117; RV32IMZICOND-NEXT: ret1118;1119; RV64IMZICOND-LABEL: select_add_6:1120; RV64IMZICOND: # %bb.0:1121; RV64IMZICOND-NEXT: czero.nez a0, a1, a01122; RV64IMZICOND-NEXT: lui a1, 141123; RV64IMZICOND-NEXT: addi a1, a1, 10051124; RV64IMZICOND-NEXT: add a0, a0, a11125; RV64IMZICOND-NEXT: ret1126;1127; RV32IXQCI-LABEL: select_add_6:1128; RV32IXQCI: # %bb.0:1129; RV32IXQCI-NEXT: mv a3, a01130; RV32IXQCI-NEXT: lui a0, 141131; RV32IXQCI-NEXT: addi a4, a0, 10051132; RV32IXQCI-NEXT: add a0, a1, a41133; RV32IXQCI-NEXT: sltu a1, a0, a11134; RV32IXQCI-NEXT: add a1, a1, a21135; RV32IXQCI-NEXT: qc.mvnei a0, a3, 0, a41136; RV32IXQCI-NEXT: qc.selectieqi a3, 0, a1, 01137; RV32IXQCI-NEXT: mv a1, a31138; RV32IXQCI-NEXT: ret1139 %add = add i64 %x, 583491140 %sel = select i1 %cond, i64 58349, i64 %add1141 ret i64 %sel1142}1143 1144define i32 @select_sub_1(i1 zeroext %cond, i32 %a, i32 %b) {1145; RV32IM-LABEL: select_sub_1:1146; RV32IM: # %bb.0: # %entry1147; RV32IM-NEXT: beqz a0, .LBB24_21148; RV32IM-NEXT: # %bb.1:1149; RV32IM-NEXT: sub a2, a1, a21150; RV32IM-NEXT: .LBB24_2: # %entry1151; RV32IM-NEXT: mv a0, a21152; RV32IM-NEXT: ret1153;1154; RV64IM-LABEL: select_sub_1:1155; RV64IM: # %bb.0: # %entry1156; RV64IM-NEXT: beqz a0, .LBB24_21157; RV64IM-NEXT: # %bb.1:1158; RV64IM-NEXT: subw a2, a1, a21159; RV64IM-NEXT: .LBB24_2: # %entry1160; RV64IM-NEXT: mv a0, a21161; RV64IM-NEXT: ret1162;1163; RV64IMXVTCONDOPS-LABEL: select_sub_1:1164; RV64IMXVTCONDOPS: # %bb.0: # %entry1165; RV64IMXVTCONDOPS-NEXT: subw a1, a1, a21166; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a01167; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a1, a01168; RV64IMXVTCONDOPS-NEXT: or a0, a0, a21169; RV64IMXVTCONDOPS-NEXT: ret1170;1171; RV32IMZICOND-LABEL: select_sub_1:1172; RV32IMZICOND: # %bb.0: # %entry1173; RV32IMZICOND-NEXT: sub a1, a1, a21174; RV32IMZICOND-NEXT: czero.nez a2, a2, a01175; RV32IMZICOND-NEXT: czero.eqz a0, a1, a01176; RV32IMZICOND-NEXT: or a0, a0, a21177; RV32IMZICOND-NEXT: ret1178;1179; RV64IMZICOND-LABEL: select_sub_1:1180; RV64IMZICOND: # %bb.0: # %entry1181; RV64IMZICOND-NEXT: subw a1, a1, a21182; RV64IMZICOND-NEXT: czero.nez a2, a2, a01183; RV64IMZICOND-NEXT: czero.eqz a0, a1, a01184; RV64IMZICOND-NEXT: or a0, a0, a21185; RV64IMZICOND-NEXT: ret1186;1187; RV32IXQCI-LABEL: select_sub_1:1188; RV32IXQCI: # %bb.0: # %entry1189; RV32IXQCI-NEXT: beqz a0, .LBB24_21190; RV32IXQCI-NEXT: # %bb.1: # %entry1191; RV32IXQCI-NEXT: sub a2, a1, a21192; RV32IXQCI-NEXT: .LBB24_2: # %entry1193; RV32IXQCI-NEXT: mv a0, a21194; RV32IXQCI-NEXT: ret1195entry:1196 %c = sub i32 %a, %b1197 %res = select i1 %cond, i32 %c, i32 %b1198 ret i32 %res1199}1200 1201define i32 @select_sub_2(i1 zeroext %cond, i32 %a, i32 %b) {1202; RV32IM-LABEL: select_sub_2:1203; RV32IM: # %bb.0: # %entry1204; RV32IM-NEXT: addi a0, a0, -11205; RV32IM-NEXT: and a0, a0, a21206; RV32IM-NEXT: sub a0, a1, a01207; RV32IM-NEXT: ret1208;1209; RV64IM-LABEL: select_sub_2:1210; RV64IM: # %bb.0: # %entry1211; RV64IM-NEXT: addi a0, a0, -11212; RV64IM-NEXT: and a0, a0, a21213; RV64IM-NEXT: subw a0, a1, a01214; RV64IM-NEXT: ret1215;1216; RV64IMXVTCONDOPS-LABEL: select_sub_2:1217; RV64IMXVTCONDOPS: # %bb.0: # %entry1218; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a01219; RV64IMXVTCONDOPS-NEXT: subw a0, a1, a01220; RV64IMXVTCONDOPS-NEXT: ret1221;1222; RV32IMZICOND-LABEL: select_sub_2:1223; RV32IMZICOND: # %bb.0: # %entry1224; RV32IMZICOND-NEXT: czero.nez a0, a2, a01225; RV32IMZICOND-NEXT: sub a0, a1, a01226; RV32IMZICOND-NEXT: ret1227;1228; RV64IMZICOND-LABEL: select_sub_2:1229; RV64IMZICOND: # %bb.0: # %entry1230; RV64IMZICOND-NEXT: czero.nez a0, a2, a01231; RV64IMZICOND-NEXT: subw a0, a1, a01232; RV64IMZICOND-NEXT: ret1233;1234; RV32IXQCI-LABEL: select_sub_2:1235; RV32IXQCI: # %bb.0: # %entry1236; RV32IXQCI-NEXT: bnez a0, .LBB25_21237; RV32IXQCI-NEXT: # %bb.1: # %entry1238; RV32IXQCI-NEXT: sub a1, a1, a21239; RV32IXQCI-NEXT: .LBB25_2: # %entry1240; RV32IXQCI-NEXT: mv a0, a11241; RV32IXQCI-NEXT: ret1242entry:1243 %c = sub i32 %a, %b1244 %res = select i1 %cond, i32 %a, i32 %c1245 ret i32 %res1246}1247 1248define i32 @select_sub_3(i1 zeroext %cond, i32 %a) {1249; RV32IM-LABEL: select_sub_3:1250; RV32IM: # %bb.0: # %entry1251; RV32IM-NEXT: addi a0, a0, -11252; RV32IM-NEXT: andi a0, a0, 421253; RV32IM-NEXT: sub a0, a1, a01254; RV32IM-NEXT: ret1255;1256; RV64IM-LABEL: select_sub_3:1257; RV64IM: # %bb.0: # %entry1258; RV64IM-NEXT: addi a0, a0, -11259; RV64IM-NEXT: andi a0, a0, 421260; RV64IM-NEXT: subw a0, a1, a01261; RV64IM-NEXT: ret1262;1263; RV64IMXVTCONDOPS-LABEL: select_sub_3:1264; RV64IMXVTCONDOPS: # %bb.0: # %entry1265; RV64IMXVTCONDOPS-NEXT: addi a0, a0, -11266; RV64IMXVTCONDOPS-NEXT: andi a0, a0, 421267; RV64IMXVTCONDOPS-NEXT: subw a0, a1, a01268; RV64IMXVTCONDOPS-NEXT: ret1269;1270; RV32IMZICOND-LABEL: select_sub_3:1271; RV32IMZICOND: # %bb.0: # %entry1272; RV32IMZICOND-NEXT: addi a0, a0, -11273; RV32IMZICOND-NEXT: andi a0, a0, 421274; RV32IMZICOND-NEXT: sub a0, a1, a01275; RV32IMZICOND-NEXT: ret1276;1277; RV64IMZICOND-LABEL: select_sub_3:1278; RV64IMZICOND: # %bb.0: # %entry1279; RV64IMZICOND-NEXT: addi a0, a0, -11280; RV64IMZICOND-NEXT: andi a0, a0, 421281; RV64IMZICOND-NEXT: subw a0, a1, a01282; RV64IMZICOND-NEXT: ret1283;1284; RV32IXQCI-LABEL: select_sub_3:1285; RV32IXQCI: # %bb.0: # %entry1286; RV32IXQCI-NEXT: bnez a0, .LBB26_21287; RV32IXQCI-NEXT: # %bb.1: # %entry1288; RV32IXQCI-NEXT: addi a1, a1, -421289; RV32IXQCI-NEXT: .LBB26_2: # %entry1290; RV32IXQCI-NEXT: mv a0, a11291; RV32IXQCI-NEXT: ret1292entry:1293 %c = sub i32 %a, 421294 %res = select i1 %cond, i32 %a, i32 %c1295 ret i32 %res1296}1297 1298define i32 @select_sub_4(i1 zeroext %cond, i32 %x) {1299; RV32IM-LABEL: select_sub_4:1300; RV32IM: # %bb.0:1301; RV32IM-NEXT: bnez a0, .LBB27_21302; RV32IM-NEXT: # %bb.1:1303; RV32IM-NEXT: addi a0, a1, -1281304; RV32IM-NEXT: ret1305; RV32IM-NEXT: .LBB27_2:1306; RV32IM-NEXT: li a0, 1281307; RV32IM-NEXT: ret1308;1309; RV64IM-LABEL: select_sub_4:1310; RV64IM: # %bb.0:1311; RV64IM-NEXT: bnez a0, .LBB27_21312; RV64IM-NEXT: # %bb.1:1313; RV64IM-NEXT: addiw a0, a1, -1281314; RV64IM-NEXT: ret1315; RV64IM-NEXT: .LBB27_2:1316; RV64IM-NEXT: li a0, 1281317; RV64IM-NEXT: ret1318;1319; RV64IMXVTCONDOPS-LABEL: select_sub_4:1320; RV64IMXVTCONDOPS: # %bb.0:1321; RV64IMXVTCONDOPS-NEXT: addiw a1, a1, -1281322; RV64IMXVTCONDOPS-NEXT: addi a1, a1, -1281323; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a01324; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 1281325; RV64IMXVTCONDOPS-NEXT: ret1326;1327; RV32IMZICOND-LABEL: select_sub_4:1328; RV32IMZICOND: # %bb.0:1329; RV32IMZICOND-NEXT: addi a1, a1, -2561330; RV32IMZICOND-NEXT: czero.nez a0, a1, a01331; RV32IMZICOND-NEXT: addi a0, a0, 1281332; RV32IMZICOND-NEXT: ret1333;1334; RV64IMZICOND-LABEL: select_sub_4:1335; RV64IMZICOND: # %bb.0:1336; RV64IMZICOND-NEXT: addiw a1, a1, -1281337; RV64IMZICOND-NEXT: addi a1, a1, -1281338; RV64IMZICOND-NEXT: czero.nez a0, a1, a01339; RV64IMZICOND-NEXT: addi a0, a0, 1281340; RV64IMZICOND-NEXT: ret1341;1342; RV32IXQCI-LABEL: select_sub_4:1343; RV32IXQCI: # %bb.0:1344; RV32IXQCI-NEXT: li a2, 1281345; RV32IXQCI-NEXT: bnez a0, .LBB27_21346; RV32IXQCI-NEXT: # %bb.1:1347; RV32IXQCI-NEXT: addi a2, a1, -1281348; RV32IXQCI-NEXT: .LBB27_2:1349; RV32IXQCI-NEXT: mv a0, a21350; RV32IXQCI-NEXT: ret1351 %add = sub i32 %x, 1281352 %sel = select i1 %cond, i32 128, i32 %add1353 ret i32 %sel1354}1355 1356 1357define i32 @select_and_1(i1 zeroext %cond, i32 %a, i32 %b) {1358; RV32IM-LABEL: select_and_1:1359; RV32IM: # %bb.0: # %entry1360; RV32IM-NEXT: beqz a0, .LBB28_21361; RV32IM-NEXT: # %bb.1:1362; RV32IM-NEXT: and a2, a1, a21363; RV32IM-NEXT: .LBB28_2: # %entry1364; RV32IM-NEXT: mv a0, a21365; RV32IM-NEXT: ret1366;1367; RV64IM-LABEL: select_and_1:1368; RV64IM: # %bb.0: # %entry1369; RV64IM-NEXT: beqz a0, .LBB28_21370; RV64IM-NEXT: # %bb.1:1371; RV64IM-NEXT: and a2, a1, a21372; RV64IM-NEXT: .LBB28_2: # %entry1373; RV64IM-NEXT: mv a0, a21374; RV64IM-NEXT: ret1375;1376; RV64IMXVTCONDOPS-LABEL: select_and_1:1377; RV64IMXVTCONDOPS: # %bb.0: # %entry1378; RV64IMXVTCONDOPS-NEXT: and a1, a1, a21379; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a01380; RV64IMXVTCONDOPS-NEXT: or a0, a1, a01381; RV64IMXVTCONDOPS-NEXT: ret1382;1383; CHECKZICOND-LABEL: select_and_1:1384; CHECKZICOND: # %bb.0: # %entry1385; CHECKZICOND-NEXT: and a1, a1, a21386; CHECKZICOND-NEXT: czero.nez a0, a2, a01387; CHECKZICOND-NEXT: or a0, a1, a01388; CHECKZICOND-NEXT: ret1389;1390; RV32IXQCI-LABEL: select_and_1:1391; RV32IXQCI: # %bb.0: # %entry1392; RV32IXQCI-NEXT: beqz a0, .LBB28_21393; RV32IXQCI-NEXT: # %bb.1: # %entry1394; RV32IXQCI-NEXT: and a2, a2, a11395; RV32IXQCI-NEXT: .LBB28_2: # %entry1396; RV32IXQCI-NEXT: mv a0, a21397; RV32IXQCI-NEXT: ret1398entry:1399 %c = and i32 %a, %b1400 %res = select i1 %cond, i32 %c, i32 %b1401 ret i32 %res1402}1403 1404define i32 @select_and_2(i1 zeroext %cond, i32 %a, i32 %b) {1405; RV32IM-LABEL: select_and_2:1406; RV32IM: # %bb.0: # %entry1407; RV32IM-NEXT: bnez a0, .LBB29_21408; RV32IM-NEXT: # %bb.1: # %entry1409; RV32IM-NEXT: and a1, a1, a21410; RV32IM-NEXT: .LBB29_2: # %entry1411; RV32IM-NEXT: mv a0, a11412; RV32IM-NEXT: ret1413;1414; RV64IM-LABEL: select_and_2:1415; RV64IM: # %bb.0: # %entry1416; RV64IM-NEXT: bnez a0, .LBB29_21417; RV64IM-NEXT: # %bb.1: # %entry1418; RV64IM-NEXT: and a1, a1, a21419; RV64IM-NEXT: .LBB29_2: # %entry1420; RV64IM-NEXT: mv a0, a11421; RV64IM-NEXT: ret1422;1423; RV64IMXVTCONDOPS-LABEL: select_and_2:1424; RV64IMXVTCONDOPS: # %bb.0: # %entry1425; RV64IMXVTCONDOPS-NEXT: and a2, a1, a21426; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a1, a01427; RV64IMXVTCONDOPS-NEXT: or a0, a2, a01428; RV64IMXVTCONDOPS-NEXT: ret1429;1430; CHECKZICOND-LABEL: select_and_2:1431; CHECKZICOND: # %bb.0: # %entry1432; CHECKZICOND-NEXT: and a2, a1, a21433; CHECKZICOND-NEXT: czero.eqz a0, a1, a01434; CHECKZICOND-NEXT: or a0, a2, a01435; CHECKZICOND-NEXT: ret1436;1437; RV32IXQCI-LABEL: select_and_2:1438; RV32IXQCI: # %bb.0: # %entry1439; RV32IXQCI-NEXT: bnez a0, .LBB29_21440; RV32IXQCI-NEXT: # %bb.1: # %entry1441; RV32IXQCI-NEXT: and a1, a1, a21442; RV32IXQCI-NEXT: .LBB29_2: # %entry1443; RV32IXQCI-NEXT: mv a0, a11444; RV32IXQCI-NEXT: ret1445entry:1446 %c = and i32 %a, %b1447 %res = select i1 %cond, i32 %a, i32 %c1448 ret i32 %res1449}1450 1451define i32 @select_and_3(i1 zeroext %cond, i32 %a) {1452; RV32IM-LABEL: select_and_3:1453; RV32IM: # %bb.0: # %entry1454; RV32IM-NEXT: bnez a0, .LBB30_21455; RV32IM-NEXT: # %bb.1: # %entry1456; RV32IM-NEXT: andi a1, a1, 421457; RV32IM-NEXT: .LBB30_2: # %entry1458; RV32IM-NEXT: mv a0, a11459; RV32IM-NEXT: ret1460;1461; RV64IM-LABEL: select_and_3:1462; RV64IM: # %bb.0: # %entry1463; RV64IM-NEXT: bnez a0, .LBB30_21464; RV64IM-NEXT: # %bb.1: # %entry1465; RV64IM-NEXT: andi a1, a1, 421466; RV64IM-NEXT: .LBB30_2: # %entry1467; RV64IM-NEXT: mv a0, a11468; RV64IM-NEXT: ret1469;1470; RV64IMXVTCONDOPS-LABEL: select_and_3:1471; RV64IMXVTCONDOPS: # %bb.0: # %entry1472; RV64IMXVTCONDOPS-NEXT: andi a2, a1, 421473; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a1, a01474; RV64IMXVTCONDOPS-NEXT: or a0, a2, a01475; RV64IMXVTCONDOPS-NEXT: ret1476;1477; CHECKZICOND-LABEL: select_and_3:1478; CHECKZICOND: # %bb.0: # %entry1479; CHECKZICOND-NEXT: andi a2, a1, 421480; CHECKZICOND-NEXT: czero.eqz a0, a1, a01481; CHECKZICOND-NEXT: or a0, a2, a01482; CHECKZICOND-NEXT: ret1483;1484; RV32IXQCI-LABEL: select_and_3:1485; RV32IXQCI: # %bb.0: # %entry1486; RV32IXQCI-NEXT: bnez a0, .LBB30_21487; RV32IXQCI-NEXT: # %bb.1: # %entry1488; RV32IXQCI-NEXT: andi a1, a1, 421489; RV32IXQCI-NEXT: .LBB30_2: # %entry1490; RV32IXQCI-NEXT: mv a0, a11491; RV32IXQCI-NEXT: ret1492entry:1493 %c = and i32 %a, 421494 %res = select i1 %cond, i32 %a, i32 %c1495 ret i32 %res1496}1497 1498define i32 @select_udiv_1(i1 zeroext %cond, i32 %a, i32 %b) {1499; RV32IM-LABEL: select_udiv_1:1500; RV32IM: # %bb.0: # %entry1501; RV32IM-NEXT: beqz a0, .LBB31_21502; RV32IM-NEXT: # %bb.1:1503; RV32IM-NEXT: divu a2, a1, a21504; RV32IM-NEXT: .LBB31_2: # %entry1505; RV32IM-NEXT: mv a0, a21506; RV32IM-NEXT: ret1507;1508; RV64IM-LABEL: select_udiv_1:1509; RV64IM: # %bb.0: # %entry1510; RV64IM-NEXT: beqz a0, .LBB31_21511; RV64IM-NEXT: # %bb.1:1512; RV64IM-NEXT: divuw a2, a1, a21513; RV64IM-NEXT: .LBB31_2: # %entry1514; RV64IM-NEXT: mv a0, a21515; RV64IM-NEXT: ret1516;1517; RV64IMXVTCONDOPS-LABEL: select_udiv_1:1518; RV64IMXVTCONDOPS: # %bb.0: # %entry1519; RV64IMXVTCONDOPS-NEXT: divuw a1, a1, a21520; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a01521; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a1, a01522; RV64IMXVTCONDOPS-NEXT: or a0, a0, a21523; RV64IMXVTCONDOPS-NEXT: ret1524;1525; RV32IMZICOND-LABEL: select_udiv_1:1526; RV32IMZICOND: # %bb.0: # %entry1527; RV32IMZICOND-NEXT: divu a1, a1, a21528; RV32IMZICOND-NEXT: czero.nez a2, a2, a01529; RV32IMZICOND-NEXT: czero.eqz a0, a1, a01530; RV32IMZICOND-NEXT: or a0, a0, a21531; RV32IMZICOND-NEXT: ret1532;1533; RV64IMZICOND-LABEL: select_udiv_1:1534; RV64IMZICOND: # %bb.0: # %entry1535; RV64IMZICOND-NEXT: divuw a1, a1, a21536; RV64IMZICOND-NEXT: czero.nez a2, a2, a01537; RV64IMZICOND-NEXT: czero.eqz a0, a1, a01538; RV64IMZICOND-NEXT: or a0, a0, a21539; RV64IMZICOND-NEXT: ret1540;1541; RV32IXQCI-LABEL: select_udiv_1:1542; RV32IXQCI: # %bb.0: # %entry1543; RV32IXQCI-NEXT: divu a1, a1, a21544; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a21545; RV32IXQCI-NEXT: mv a0, a11546; RV32IXQCI-NEXT: ret1547entry:1548 %c = udiv i32 %a, %b1549 %res = select i1 %cond, i32 %c, i32 %b1550 ret i32 %res1551}1552 1553define i32 @select_udiv_2(i1 zeroext %cond, i32 %a, i32 %b) {1554; RV32IM-LABEL: select_udiv_2:1555; RV32IM: # %bb.0: # %entry1556; RV32IM-NEXT: bnez a0, .LBB32_21557; RV32IM-NEXT: # %bb.1: # %entry1558; RV32IM-NEXT: divu a1, a1, a21559; RV32IM-NEXT: .LBB32_2: # %entry1560; RV32IM-NEXT: mv a0, a11561; RV32IM-NEXT: ret1562;1563; RV64IM-LABEL: select_udiv_2:1564; RV64IM: # %bb.0: # %entry1565; RV64IM-NEXT: bnez a0, .LBB32_21566; RV64IM-NEXT: # %bb.1: # %entry1567; RV64IM-NEXT: divuw a1, a1, a21568; RV64IM-NEXT: .LBB32_2: # %entry1569; RV64IM-NEXT: mv a0, a11570; RV64IM-NEXT: ret1571;1572; RV64IMXVTCONDOPS-LABEL: select_udiv_2:1573; RV64IMXVTCONDOPS: # %bb.0: # %entry1574; RV64IMXVTCONDOPS-NEXT: divuw a2, a1, a21575; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a01576; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a01577; RV64IMXVTCONDOPS-NEXT: or a0, a1, a01578; RV64IMXVTCONDOPS-NEXT: ret1579;1580; RV32IMZICOND-LABEL: select_udiv_2:1581; RV32IMZICOND: # %bb.0: # %entry1582; RV32IMZICOND-NEXT: divu a2, a1, a21583; RV32IMZICOND-NEXT: czero.eqz a1, a1, a01584; RV32IMZICOND-NEXT: czero.nez a0, a2, a01585; RV32IMZICOND-NEXT: or a0, a1, a01586; RV32IMZICOND-NEXT: ret1587;1588; RV64IMZICOND-LABEL: select_udiv_2:1589; RV64IMZICOND: # %bb.0: # %entry1590; RV64IMZICOND-NEXT: divuw a2, a1, a21591; RV64IMZICOND-NEXT: czero.eqz a1, a1, a01592; RV64IMZICOND-NEXT: czero.nez a0, a2, a01593; RV64IMZICOND-NEXT: or a0, a1, a01594; RV64IMZICOND-NEXT: ret1595;1596; RV32IXQCI-LABEL: select_udiv_2:1597; RV32IXQCI: # %bb.0: # %entry1598; RV32IXQCI-NEXT: divu a2, a1, a21599; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a11600; RV32IXQCI-NEXT: mv a0, a21601; RV32IXQCI-NEXT: ret1602entry:1603 %c = udiv i32 %a, %b1604 %res = select i1 %cond, i32 %a, i32 %c1605 ret i32 %res1606}1607 1608define i32 @select_udiv_3(i1 zeroext %cond, i32 %a) {1609; RV32IM-LABEL: select_udiv_3:1610; RV32IM: # %bb.0: # %entry1611; RV32IM-NEXT: bnez a0, .LBB33_21612; RV32IM-NEXT: # %bb.1: # %entry1613; RV32IM-NEXT: srli a1, a1, 11614; RV32IM-NEXT: lui a0, 1997291615; RV32IM-NEXT: addi a0, a0, -9751616; RV32IM-NEXT: mulhu a1, a1, a01617; RV32IM-NEXT: srli a1, a1, 21618; RV32IM-NEXT: .LBB33_2: # %entry1619; RV32IM-NEXT: mv a0, a11620; RV32IM-NEXT: ret1621;1622; RV64IM-LABEL: select_udiv_3:1623; RV64IM: # %bb.0: # %entry1624; RV64IM-NEXT: bnez a0, .LBB33_21625; RV64IM-NEXT: # %bb.1: # %entry1626; RV64IM-NEXT: srliw a0, a1, 11627; RV64IM-NEXT: lui a1, 1997291628; RV64IM-NEXT: addi a1, a1, -9751629; RV64IM-NEXT: mul a1, a0, a11630; RV64IM-NEXT: srli a1, a1, 341631; RV64IM-NEXT: .LBB33_2: # %entry1632; RV64IM-NEXT: mv a0, a11633; RV64IM-NEXT: ret1634;1635; RV64IMXVTCONDOPS-LABEL: select_udiv_3:1636; RV64IMXVTCONDOPS: # %bb.0: # %entry1637; RV64IMXVTCONDOPS-NEXT: srliw a2, a1, 11638; RV64IMXVTCONDOPS-NEXT: lui a3, 1997291639; RV64IMXVTCONDOPS-NEXT: addi a3, a3, -9751640; RV64IMXVTCONDOPS-NEXT: mul a2, a2, a31641; RV64IMXVTCONDOPS-NEXT: srli a2, a2, 341642; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a01643; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a01644; RV64IMXVTCONDOPS-NEXT: or a0, a1, a01645; RV64IMXVTCONDOPS-NEXT: ret1646;1647; RV32IMZICOND-LABEL: select_udiv_3:1648; RV32IMZICOND: # %bb.0: # %entry1649; RV32IMZICOND-NEXT: srli a2, a1, 11650; RV32IMZICOND-NEXT: lui a3, 1997291651; RV32IMZICOND-NEXT: addi a3, a3, -9751652; RV32IMZICOND-NEXT: mulhu a2, a2, a31653; RV32IMZICOND-NEXT: srli a2, a2, 21654; RV32IMZICOND-NEXT: czero.eqz a1, a1, a01655; RV32IMZICOND-NEXT: czero.nez a0, a2, a01656; RV32IMZICOND-NEXT: or a0, a1, a01657; RV32IMZICOND-NEXT: ret1658;1659; RV64IMZICOND-LABEL: select_udiv_3:1660; RV64IMZICOND: # %bb.0: # %entry1661; RV64IMZICOND-NEXT: srliw a2, a1, 11662; RV64IMZICOND-NEXT: lui a3, 1997291663; RV64IMZICOND-NEXT: addi a3, a3, -9751664; RV64IMZICOND-NEXT: mul a2, a2, a31665; RV64IMZICOND-NEXT: srli a2, a2, 341666; RV64IMZICOND-NEXT: czero.eqz a1, a1, a01667; RV64IMZICOND-NEXT: czero.nez a0, a2, a01668; RV64IMZICOND-NEXT: or a0, a1, a01669; RV64IMZICOND-NEXT: ret1670;1671; RV32IXQCI-LABEL: select_udiv_3:1672; RV32IXQCI: # %bb.0: # %entry1673; RV32IXQCI-NEXT: srli a2, a1, 11674; RV32IXQCI-NEXT: lui a3, 1997291675; RV32IXQCI-NEXT: addi a3, a3, -9751676; RV32IXQCI-NEXT: mulhu a2, a2, a31677; RV32IXQCI-NEXT: bnez a0, .LBB33_21678; RV32IXQCI-NEXT: # %bb.1: # %entry1679; RV32IXQCI-NEXT: srli a1, a2, 21680; RV32IXQCI-NEXT: .LBB33_2: # %entry1681; RV32IXQCI-NEXT: mv a0, a11682; RV32IXQCI-NEXT: ret1683entry:1684 %c = udiv i32 %a, 421685 %res = select i1 %cond, i32 %a, i32 %c1686 ret i32 %res1687}1688 1689define i32 @select_shl_1(i1 zeroext %cond, i32 %a, i32 %b) {1690; RV32IM-LABEL: select_shl_1:1691; RV32IM: # %bb.0: # %entry1692; RV32IM-NEXT: beqz a0, .LBB34_21693; RV32IM-NEXT: # %bb.1:1694; RV32IM-NEXT: sll a2, a1, a21695; RV32IM-NEXT: .LBB34_2: # %entry1696; RV32IM-NEXT: mv a0, a21697; RV32IM-NEXT: ret1698;1699; RV64IM-LABEL: select_shl_1:1700; RV64IM: # %bb.0: # %entry1701; RV64IM-NEXT: beqz a0, .LBB34_21702; RV64IM-NEXT: # %bb.1:1703; RV64IM-NEXT: sllw a2, a1, a21704; RV64IM-NEXT: .LBB34_2: # %entry1705; RV64IM-NEXT: mv a0, a21706; RV64IM-NEXT: ret1707;1708; RV64IMXVTCONDOPS-LABEL: select_shl_1:1709; RV64IMXVTCONDOPS: # %bb.0: # %entry1710; RV64IMXVTCONDOPS-NEXT: sllw a1, a1, a21711; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a01712; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a1, a01713; RV64IMXVTCONDOPS-NEXT: or a0, a0, a21714; RV64IMXVTCONDOPS-NEXT: ret1715;1716; RV32IMZICOND-LABEL: select_shl_1:1717; RV32IMZICOND: # %bb.0: # %entry1718; RV32IMZICOND-NEXT: sll a1, a1, a21719; RV32IMZICOND-NEXT: czero.nez a2, a2, a01720; RV32IMZICOND-NEXT: czero.eqz a0, a1, a01721; RV32IMZICOND-NEXT: or a0, a0, a21722; RV32IMZICOND-NEXT: ret1723;1724; RV64IMZICOND-LABEL: select_shl_1:1725; RV64IMZICOND: # %bb.0: # %entry1726; RV64IMZICOND-NEXT: sllw a1, a1, a21727; RV64IMZICOND-NEXT: czero.nez a2, a2, a01728; RV64IMZICOND-NEXT: czero.eqz a0, a1, a01729; RV64IMZICOND-NEXT: or a0, a0, a21730; RV64IMZICOND-NEXT: ret1731;1732; RV32IXQCI-LABEL: select_shl_1:1733; RV32IXQCI: # %bb.0: # %entry1734; RV32IXQCI-NEXT: beqz a0, .LBB34_21735; RV32IXQCI-NEXT: # %bb.1: # %entry1736; RV32IXQCI-NEXT: sll a2, a1, a21737; RV32IXQCI-NEXT: .LBB34_2: # %entry1738; RV32IXQCI-NEXT: mv a0, a21739; RV32IXQCI-NEXT: ret1740entry:1741 %c = shl i32 %a, %b1742 %res = select i1 %cond, i32 %c, i32 %b1743 ret i32 %res1744}1745 1746define i32 @select_shl_2(i1 zeroext %cond, i32 %a, i32 %b) {1747; RV32IM-LABEL: select_shl_2:1748; RV32IM: # %bb.0: # %entry1749; RV32IM-NEXT: addi a0, a0, -11750; RV32IM-NEXT: and a0, a0, a21751; RV32IM-NEXT: sll a0, a1, a01752; RV32IM-NEXT: ret1753;1754; RV64IM-LABEL: select_shl_2:1755; RV64IM: # %bb.0: # %entry1756; RV64IM-NEXT: addi a0, a0, -11757; RV64IM-NEXT: and a0, a0, a21758; RV64IM-NEXT: sllw a0, a1, a01759; RV64IM-NEXT: ret1760;1761; RV64IMXVTCONDOPS-LABEL: select_shl_2:1762; RV64IMXVTCONDOPS: # %bb.0: # %entry1763; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a01764; RV64IMXVTCONDOPS-NEXT: sllw a0, a1, a01765; RV64IMXVTCONDOPS-NEXT: ret1766;1767; RV32IMZICOND-LABEL: select_shl_2:1768; RV32IMZICOND: # %bb.0: # %entry1769; RV32IMZICOND-NEXT: czero.nez a0, a2, a01770; RV32IMZICOND-NEXT: sll a0, a1, a01771; RV32IMZICOND-NEXT: ret1772;1773; RV64IMZICOND-LABEL: select_shl_2:1774; RV64IMZICOND: # %bb.0: # %entry1775; RV64IMZICOND-NEXT: czero.nez a0, a2, a01776; RV64IMZICOND-NEXT: sllw a0, a1, a01777; RV64IMZICOND-NEXT: ret1778;1779; RV32IXQCI-LABEL: select_shl_2:1780; RV32IXQCI: # %bb.0: # %entry1781; RV32IXQCI-NEXT: bnez a0, .LBB35_21782; RV32IXQCI-NEXT: # %bb.1: # %entry1783; RV32IXQCI-NEXT: sll a1, a1, a21784; RV32IXQCI-NEXT: .LBB35_2: # %entry1785; RV32IXQCI-NEXT: mv a0, a11786; RV32IXQCI-NEXT: ret1787entry:1788 %c = shl i32 %a, %b1789 %res = select i1 %cond, i32 %a, i32 %c1790 ret i32 %res1791}1792 1793define i32 @select_shl_3(i1 zeroext %cond, i32 %a) {1794; CHECK-LABEL: select_shl_3:1795; CHECK: # %bb.0: # %entry1796; CHECK-NEXT: mv a0, a11797; CHECK-NEXT: ret1798;1799; RV32IXQCI-LABEL: select_shl_3:1800; RV32IXQCI: # %bb.0: # %entry1801; RV32IXQCI-NEXT: mv a0, a11802; RV32IXQCI-NEXT: ret1803entry:1804 %c = shl i32 %a, 421805 %res = select i1 %cond, i32 %a, i32 %c1806 ret i32 %res1807}1808 1809define i32 @select_ashr_1(i1 zeroext %cond, i32 %a, i32 %b) {1810; RV32IM-LABEL: select_ashr_1:1811; RV32IM: # %bb.0: # %entry1812; RV32IM-NEXT: beqz a0, .LBB37_21813; RV32IM-NEXT: # %bb.1:1814; RV32IM-NEXT: sra a2, a1, a21815; RV32IM-NEXT: .LBB37_2: # %entry1816; RV32IM-NEXT: mv a0, a21817; RV32IM-NEXT: ret1818;1819; RV64IM-LABEL: select_ashr_1:1820; RV64IM: # %bb.0: # %entry1821; RV64IM-NEXT: beqz a0, .LBB37_21822; RV64IM-NEXT: # %bb.1:1823; RV64IM-NEXT: sraw a2, a1, a21824; RV64IM-NEXT: .LBB37_2: # %entry1825; RV64IM-NEXT: mv a0, a21826; RV64IM-NEXT: ret1827;1828; RV64IMXVTCONDOPS-LABEL: select_ashr_1:1829; RV64IMXVTCONDOPS: # %bb.0: # %entry1830; RV64IMXVTCONDOPS-NEXT: sraw a1, a1, a21831; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a01832; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a1, a01833; RV64IMXVTCONDOPS-NEXT: or a0, a0, a21834; RV64IMXVTCONDOPS-NEXT: ret1835;1836; RV32IMZICOND-LABEL: select_ashr_1:1837; RV32IMZICOND: # %bb.0: # %entry1838; RV32IMZICOND-NEXT: sra a1, a1, a21839; RV32IMZICOND-NEXT: czero.nez a2, a2, a01840; RV32IMZICOND-NEXT: czero.eqz a0, a1, a01841; RV32IMZICOND-NEXT: or a0, a0, a21842; RV32IMZICOND-NEXT: ret1843;1844; RV64IMZICOND-LABEL: select_ashr_1:1845; RV64IMZICOND: # %bb.0: # %entry1846; RV64IMZICOND-NEXT: sraw a1, a1, a21847; RV64IMZICOND-NEXT: czero.nez a2, a2, a01848; RV64IMZICOND-NEXT: czero.eqz a0, a1, a01849; RV64IMZICOND-NEXT: or a0, a0, a21850; RV64IMZICOND-NEXT: ret1851;1852; RV32IXQCI-LABEL: select_ashr_1:1853; RV32IXQCI: # %bb.0: # %entry1854; RV32IXQCI-NEXT: beqz a0, .LBB37_21855; RV32IXQCI-NEXT: # %bb.1: # %entry1856; RV32IXQCI-NEXT: sra a2, a1, a21857; RV32IXQCI-NEXT: .LBB37_2: # %entry1858; RV32IXQCI-NEXT: mv a0, a21859; RV32IXQCI-NEXT: ret1860entry:1861 %c = ashr i32 %a, %b1862 %res = select i1 %cond, i32 %c, i32 %b1863 ret i32 %res1864}1865 1866define i32 @select_ashr_2(i1 zeroext %cond, i32 %a, i32 %b) {1867; RV32IM-LABEL: select_ashr_2:1868; RV32IM: # %bb.0: # %entry1869; RV32IM-NEXT: addi a0, a0, -11870; RV32IM-NEXT: and a0, a0, a21871; RV32IM-NEXT: sra a0, a1, a01872; RV32IM-NEXT: ret1873;1874; RV64IM-LABEL: select_ashr_2:1875; RV64IM: # %bb.0: # %entry1876; RV64IM-NEXT: addi a0, a0, -11877; RV64IM-NEXT: and a0, a0, a21878; RV64IM-NEXT: sraw a0, a1, a01879; RV64IM-NEXT: ret1880;1881; RV64IMXVTCONDOPS-LABEL: select_ashr_2:1882; RV64IMXVTCONDOPS: # %bb.0: # %entry1883; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a01884; RV64IMXVTCONDOPS-NEXT: sraw a0, a1, a01885; RV64IMXVTCONDOPS-NEXT: ret1886;1887; RV32IMZICOND-LABEL: select_ashr_2:1888; RV32IMZICOND: # %bb.0: # %entry1889; RV32IMZICOND-NEXT: czero.nez a0, a2, a01890; RV32IMZICOND-NEXT: sra a0, a1, a01891; RV32IMZICOND-NEXT: ret1892;1893; RV64IMZICOND-LABEL: select_ashr_2:1894; RV64IMZICOND: # %bb.0: # %entry1895; RV64IMZICOND-NEXT: czero.nez a0, a2, a01896; RV64IMZICOND-NEXT: sraw a0, a1, a01897; RV64IMZICOND-NEXT: ret1898;1899; RV32IXQCI-LABEL: select_ashr_2:1900; RV32IXQCI: # %bb.0: # %entry1901; RV32IXQCI-NEXT: bnez a0, .LBB38_21902; RV32IXQCI-NEXT: # %bb.1: # %entry1903; RV32IXQCI-NEXT: sra a1, a1, a21904; RV32IXQCI-NEXT: .LBB38_2: # %entry1905; RV32IXQCI-NEXT: mv a0, a11906; RV32IXQCI-NEXT: ret1907entry:1908 %c = ashr i32 %a, %b1909 %res = select i1 %cond, i32 %a, i32 %c1910 ret i32 %res1911}1912 1913define i32 @select_ashr_3(i1 zeroext %cond, i32 %a) {1914; CHECK-LABEL: select_ashr_3:1915; CHECK: # %bb.0: # %entry1916; CHECK-NEXT: mv a0, a11917; CHECK-NEXT: ret1918;1919; RV32IXQCI-LABEL: select_ashr_3:1920; RV32IXQCI: # %bb.0: # %entry1921; RV32IXQCI-NEXT: mv a0, a11922; RV32IXQCI-NEXT: ret1923entry:1924 %c = ashr i32 %a, 421925 %res = select i1 %cond, i32 %a, i32 %c1926 ret i32 %res1927}1928 1929define i32 @select_lshr_1(i1 zeroext %cond, i32 %a, i32 %b) {1930; RV32IM-LABEL: select_lshr_1:1931; RV32IM: # %bb.0: # %entry1932; RV32IM-NEXT: beqz a0, .LBB40_21933; RV32IM-NEXT: # %bb.1:1934; RV32IM-NEXT: srl a2, a1, a21935; RV32IM-NEXT: .LBB40_2: # %entry1936; RV32IM-NEXT: mv a0, a21937; RV32IM-NEXT: ret1938;1939; RV64IM-LABEL: select_lshr_1:1940; RV64IM: # %bb.0: # %entry1941; RV64IM-NEXT: beqz a0, .LBB40_21942; RV64IM-NEXT: # %bb.1:1943; RV64IM-NEXT: srlw a2, a1, a21944; RV64IM-NEXT: .LBB40_2: # %entry1945; RV64IM-NEXT: mv a0, a21946; RV64IM-NEXT: ret1947;1948; RV64IMXVTCONDOPS-LABEL: select_lshr_1:1949; RV64IMXVTCONDOPS: # %bb.0: # %entry1950; RV64IMXVTCONDOPS-NEXT: srlw a1, a1, a21951; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a01952; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a1, a01953; RV64IMXVTCONDOPS-NEXT: or a0, a0, a21954; RV64IMXVTCONDOPS-NEXT: ret1955;1956; RV32IMZICOND-LABEL: select_lshr_1:1957; RV32IMZICOND: # %bb.0: # %entry1958; RV32IMZICOND-NEXT: srl a1, a1, a21959; RV32IMZICOND-NEXT: czero.nez a2, a2, a01960; RV32IMZICOND-NEXT: czero.eqz a0, a1, a01961; RV32IMZICOND-NEXT: or a0, a0, a21962; RV32IMZICOND-NEXT: ret1963;1964; RV64IMZICOND-LABEL: select_lshr_1:1965; RV64IMZICOND: # %bb.0: # %entry1966; RV64IMZICOND-NEXT: srlw a1, a1, a21967; RV64IMZICOND-NEXT: czero.nez a2, a2, a01968; RV64IMZICOND-NEXT: czero.eqz a0, a1, a01969; RV64IMZICOND-NEXT: or a0, a0, a21970; RV64IMZICOND-NEXT: ret1971;1972; RV32IXQCI-LABEL: select_lshr_1:1973; RV32IXQCI: # %bb.0: # %entry1974; RV32IXQCI-NEXT: beqz a0, .LBB40_21975; RV32IXQCI-NEXT: # %bb.1: # %entry1976; RV32IXQCI-NEXT: srl a2, a1, a21977; RV32IXQCI-NEXT: .LBB40_2: # %entry1978; RV32IXQCI-NEXT: mv a0, a21979; RV32IXQCI-NEXT: ret1980entry:1981 %c = lshr i32 %a, %b1982 %res = select i1 %cond, i32 %c, i32 %b1983 ret i32 %res1984}1985 1986define i32 @select_lshr_2(i1 zeroext %cond, i32 %a, i32 %b) {1987; RV32IM-LABEL: select_lshr_2:1988; RV32IM: # %bb.0: # %entry1989; RV32IM-NEXT: addi a0, a0, -11990; RV32IM-NEXT: and a0, a0, a21991; RV32IM-NEXT: srl a0, a1, a01992; RV32IM-NEXT: ret1993;1994; RV64IM-LABEL: select_lshr_2:1995; RV64IM: # %bb.0: # %entry1996; RV64IM-NEXT: addi a0, a0, -11997; RV64IM-NEXT: and a0, a0, a21998; RV64IM-NEXT: srlw a0, a1, a01999; RV64IM-NEXT: ret2000;2001; RV64IMXVTCONDOPS-LABEL: select_lshr_2:2002; RV64IMXVTCONDOPS: # %bb.0: # %entry2003; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a02004; RV64IMXVTCONDOPS-NEXT: srlw a0, a1, a02005; RV64IMXVTCONDOPS-NEXT: ret2006;2007; RV32IMZICOND-LABEL: select_lshr_2:2008; RV32IMZICOND: # %bb.0: # %entry2009; RV32IMZICOND-NEXT: czero.nez a0, a2, a02010; RV32IMZICOND-NEXT: srl a0, a1, a02011; RV32IMZICOND-NEXT: ret2012;2013; RV64IMZICOND-LABEL: select_lshr_2:2014; RV64IMZICOND: # %bb.0: # %entry2015; RV64IMZICOND-NEXT: czero.nez a0, a2, a02016; RV64IMZICOND-NEXT: srlw a0, a1, a02017; RV64IMZICOND-NEXT: ret2018;2019; RV32IXQCI-LABEL: select_lshr_2:2020; RV32IXQCI: # %bb.0: # %entry2021; RV32IXQCI-NEXT: bnez a0, .LBB41_22022; RV32IXQCI-NEXT: # %bb.1: # %entry2023; RV32IXQCI-NEXT: srl a1, a1, a22024; RV32IXQCI-NEXT: .LBB41_2: # %entry2025; RV32IXQCI-NEXT: mv a0, a12026; RV32IXQCI-NEXT: ret2027entry:2028 %c = lshr i32 %a, %b2029 %res = select i1 %cond, i32 %a, i32 %c2030 ret i32 %res2031}2032 2033define i32 @select_lshr_3(i1 zeroext %cond, i32 %a) {2034; CHECK-LABEL: select_lshr_3:2035; CHECK: # %bb.0: # %entry2036; CHECK-NEXT: mv a0, a12037; CHECK-NEXT: ret2038;2039; RV32IXQCI-LABEL: select_lshr_3:2040; RV32IXQCI: # %bb.0: # %entry2041; RV32IXQCI-NEXT: mv a0, a12042; RV32IXQCI-NEXT: ret2043entry:2044 %c = lshr i32 %a, 422045 %res = select i1 %cond, i32 %a, i32 %c2046 ret i32 %res2047}2048 2049define i32 @select_cst_not1(i32 signext %a, i32 signext %b) {2050; CHECK-LABEL: select_cst_not1:2051; CHECK: # %bb.0:2052; CHECK-NEXT: slt a0, a0, a12053; CHECK-NEXT: neg a0, a02054; CHECK-NEXT: xori a0, a0, -62055; CHECK-NEXT: ret2056;2057; RV32IXQCI-LABEL: select_cst_not1:2058; RV32IXQCI: # %bb.0:2059; RV32IXQCI-NEXT: slt a0, a0, a12060; RV32IXQCI-NEXT: neg a0, a02061; RV32IXQCI-NEXT: xori a0, a0, -62062; RV32IXQCI-NEXT: ret2063 %cond = icmp slt i32 %a, %b2064 %ret = select i1 %cond, i32 5, i32 -62065 ret i32 %ret2066}2067 2068define i32 @select_cst_not2(i32 signext %a) {2069; CHECK-LABEL: select_cst_not2:2070; CHECK: # %bb.0:2071; CHECK-NEXT: srai a0, a0, 312072; CHECK-NEXT: xori a0, a0, -62073; CHECK-NEXT: ret2074;2075; RV32IXQCI-LABEL: select_cst_not2:2076; RV32IXQCI: # %bb.0:2077; RV32IXQCI-NEXT: srai a0, a0, 312078; RV32IXQCI-NEXT: xori a0, a0, -62079; RV32IXQCI-NEXT: ret2080 %cond = icmp slt i32 %a, 02081 %ret = select i1 %cond, i32 5, i32 -62082 ret i32 %ret2083}2084 2085define i32 @select_cst_not3(i32 signext %a) {2086; CHECK-LABEL: select_cst_not3:2087; CHECK: # %bb.0:2088; CHECK-NEXT: srai a0, a0, 312089; CHECK-NEXT: xori a0, a0, 52090; CHECK-NEXT: ret2091;2092; RV32IXQCI-LABEL: select_cst_not3:2093; RV32IXQCI: # %bb.0:2094; RV32IXQCI-NEXT: srai a0, a0, 312095; RV32IXQCI-NEXT: xori a0, a0, 52096; RV32IXQCI-NEXT: ret2097 %cond = icmp sgt i32 %a, -12098 %ret = select i1 %cond, i32 5, i32 -62099 ret i32 %ret2100}2101 2102define i32 @select_cst_not4(i32 signext %a, i32 signext %b) {2103; RV32IM-LABEL: select_cst_not4:2104; RV32IM: # %bb.0:2105; RV32IM-NEXT: slt a0, a0, a12106; RV32IM-NEXT: lui a1, 5242882107; RV32IM-NEXT: addi a1, a1, -12108; RV32IM-NEXT: add a0, a0, a12109; RV32IM-NEXT: ret2110;2111; RV64IM-LABEL: select_cst_not4:2112; RV64IM: # %bb.0:2113; RV64IM-NEXT: slt a0, a0, a12114; RV64IM-NEXT: lui a1, 5242882115; RV64IM-NEXT: neg a0, a02116; RV64IM-NEXT: addiw a1, a1, -12117; RV64IM-NEXT: xor a0, a0, a12118; RV64IM-NEXT: ret2119;2120; RV64IMXVTCONDOPS-LABEL: select_cst_not4:2121; RV64IMXVTCONDOPS: # %bb.0:2122; RV64IMXVTCONDOPS-NEXT: slt a0, a0, a12123; RV64IMXVTCONDOPS-NEXT: lui a1, 5242882124; RV64IMXVTCONDOPS-NEXT: neg a0, a02125; RV64IMXVTCONDOPS-NEXT: addiw a1, a1, -12126; RV64IMXVTCONDOPS-NEXT: xor a0, a0, a12127; RV64IMXVTCONDOPS-NEXT: ret2128;2129; RV32IMZICOND-LABEL: select_cst_not4:2130; RV32IMZICOND: # %bb.0:2131; RV32IMZICOND-NEXT: slt a0, a0, a12132; RV32IMZICOND-NEXT: lui a1, 5242882133; RV32IMZICOND-NEXT: addi a1, a1, -12134; RV32IMZICOND-NEXT: add a0, a0, a12135; RV32IMZICOND-NEXT: ret2136;2137; RV64IMZICOND-LABEL: select_cst_not4:2138; RV64IMZICOND: # %bb.0:2139; RV64IMZICOND-NEXT: slt a0, a0, a12140; RV64IMZICOND-NEXT: lui a1, 5242882141; RV64IMZICOND-NEXT: neg a0, a02142; RV64IMZICOND-NEXT: addiw a1, a1, -12143; RV64IMZICOND-NEXT: xor a0, a0, a12144; RV64IMZICOND-NEXT: ret2145;2146; RV32IXQCI-LABEL: select_cst_not4:2147; RV32IXQCI: # %bb.0:2148; RV32IXQCI-NEXT: slt a0, a0, a12149; RV32IXQCI-NEXT: lui a1, 5242882150; RV32IXQCI-NEXT: addi a1, a1, -12151; RV32IXQCI-NEXT: add a0, a0, a12152; RV32IXQCI-NEXT: ret2153 %cond = icmp slt i32 %a, %b2154 %ret = select i1 %cond, i32 -2147483648, i32 21474836472155 ret i32 %ret2156}2157 2158define i32 @select_cst_not5(i32 signext %a, i32 signext %b) {2159; CHECK-LABEL: select_cst_not5:2160; CHECK: # %bb.0:2161; CHECK-NEXT: slt a0, a0, a12162; CHECK-NEXT: lui a1, 162163; CHECK-NEXT: neg a0, a02164; CHECK-NEXT: addi a1, a1, -52165; CHECK-NEXT: xor a0, a0, a12166; CHECK-NEXT: ret2167;2168; RV32IXQCI-LABEL: select_cst_not5:2169; RV32IXQCI: # %bb.0:2170; RV32IXQCI-NEXT: slt a0, a0, a12171; RV32IXQCI-NEXT: lui a1, 162172; RV32IXQCI-NEXT: neg a0, a02173; RV32IXQCI-NEXT: addi a1, a1, -52174; RV32IXQCI-NEXT: xor a0, a0, a12175; RV32IXQCI-NEXT: ret2176 %cond = icmp slt i32 %a, %b2177 %ret = select i1 %cond, i32 -65532, i32 655312178 ret i32 %ret2179}2180 2181define i32 @select_cst_unknown(i32 signext %a, i32 signext %b) {2182; RV32IM-LABEL: select_cst_unknown:2183; RV32IM: # %bb.0:2184; RV32IM-NEXT: blt a0, a1, .LBB48_22185; RV32IM-NEXT: # %bb.1:2186; RV32IM-NEXT: li a0, -72187; RV32IM-NEXT: ret2188; RV32IM-NEXT: .LBB48_2:2189; RV32IM-NEXT: li a0, 52190; RV32IM-NEXT: ret2191;2192; RV64IM-LABEL: select_cst_unknown:2193; RV64IM: # %bb.0:2194; RV64IM-NEXT: blt a0, a1, .LBB48_22195; RV64IM-NEXT: # %bb.1:2196; RV64IM-NEXT: li a0, -72197; RV64IM-NEXT: ret2198; RV64IM-NEXT: .LBB48_2:2199; RV64IM-NEXT: li a0, 52200; RV64IM-NEXT: ret2201;2202; RV64IMXVTCONDOPS-LABEL: select_cst_unknown:2203; RV64IMXVTCONDOPS: # %bb.0:2204; RV64IMXVTCONDOPS-NEXT: slt a0, a0, a12205; RV64IMXVTCONDOPS-NEXT: li a1, -122206; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a02207; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 52208; RV64IMXVTCONDOPS-NEXT: ret2209;2210; CHECKZICOND-LABEL: select_cst_unknown:2211; CHECKZICOND: # %bb.0:2212; CHECKZICOND-NEXT: slt a0, a0, a12213; CHECKZICOND-NEXT: li a1, -122214; CHECKZICOND-NEXT: czero.nez a0, a1, a02215; CHECKZICOND-NEXT: addi a0, a0, 52216; CHECKZICOND-NEXT: ret2217;2218; RV32IXQCI-LABEL: select_cst_unknown:2219; RV32IXQCI: # %bb.0:2220; RV32IXQCI-NEXT: li a2, -72221; RV32IXQCI-NEXT: qc.lilt a2, a0, a1, 52222; RV32IXQCI-NEXT: mv a0, a22223; RV32IXQCI-NEXT: ret2224 %cond = icmp slt i32 %a, %b2225 %ret = select i1 %cond, i32 5, i32 -72226 ret i32 %ret2227}2228 2229define i32 @select_cst1(i1 zeroext %cond) {2230; RV32IM-LABEL: select_cst1:2231; RV32IM: # %bb.0:2232; RV32IM-NEXT: bnez a0, .LBB49_22233; RV32IM-NEXT: # %bb.1:2234; RV32IM-NEXT: li a0, 202235; RV32IM-NEXT: ret2236; RV32IM-NEXT: .LBB49_2:2237; RV32IM-NEXT: li a0, 102238; RV32IM-NEXT: ret2239;2240; RV64IM-LABEL: select_cst1:2241; RV64IM: # %bb.0:2242; RV64IM-NEXT: bnez a0, .LBB49_22243; RV64IM-NEXT: # %bb.1:2244; RV64IM-NEXT: li a0, 202245; RV64IM-NEXT: ret2246; RV64IM-NEXT: .LBB49_2:2247; RV64IM-NEXT: li a0, 102248; RV64IM-NEXT: ret2249;2250; RV64IMXVTCONDOPS-LABEL: select_cst1:2251; RV64IMXVTCONDOPS: # %bb.0:2252; RV64IMXVTCONDOPS-NEXT: li a1, 102253; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a02254; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 102255; RV64IMXVTCONDOPS-NEXT: ret2256;2257; CHECKZICOND-LABEL: select_cst1:2258; CHECKZICOND: # %bb.0:2259; CHECKZICOND-NEXT: li a1, 102260; CHECKZICOND-NEXT: czero.nez a0, a1, a02261; CHECKZICOND-NEXT: addi a0, a0, 102262; CHECKZICOND-NEXT: ret2263;2264; RV32IXQCI-LABEL: select_cst1:2265; RV32IXQCI: # %bb.0:2266; RV32IXQCI-NEXT: li a1, 202267; RV32IXQCI-NEXT: qc.selectieqi a0, 0, a1, 102268; RV32IXQCI-NEXT: ret2269 %ret = select i1 %cond, i32 10, i32 202270 ret i32 %ret2271}2272 2273define i32 @select_cst2(i1 zeroext %cond) {2274; RV32IM-LABEL: select_cst2:2275; RV32IM: # %bb.0:2276; RV32IM-NEXT: bnez a0, .LBB50_22277; RV32IM-NEXT: # %bb.1:2278; RV32IM-NEXT: lui a0, 52279; RV32IM-NEXT: addi a0, a0, -4802280; RV32IM-NEXT: ret2281; RV32IM-NEXT: .LBB50_2:2282; RV32IM-NEXT: li a0, 102283; RV32IM-NEXT: ret2284;2285; RV64IM-LABEL: select_cst2:2286; RV64IM: # %bb.0:2287; RV64IM-NEXT: bnez a0, .LBB50_22288; RV64IM-NEXT: # %bb.1:2289; RV64IM-NEXT: lui a0, 52290; RV64IM-NEXT: addi a0, a0, -4802291; RV64IM-NEXT: ret2292; RV64IM-NEXT: .LBB50_2:2293; RV64IM-NEXT: li a0, 102294; RV64IM-NEXT: ret2295;2296; RV64IMXVTCONDOPS-LABEL: select_cst2:2297; RV64IMXVTCONDOPS: # %bb.0:2298; RV64IMXVTCONDOPS-NEXT: lui a1, 52299; RV64IMXVTCONDOPS-NEXT: addi a1, a1, -4902300; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a02301; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 102302; RV64IMXVTCONDOPS-NEXT: ret2303;2304; CHECKZICOND-LABEL: select_cst2:2305; CHECKZICOND: # %bb.0:2306; CHECKZICOND-NEXT: lui a1, 52307; CHECKZICOND-NEXT: addi a1, a1, -4902308; CHECKZICOND-NEXT: czero.nez a0, a1, a02309; CHECKZICOND-NEXT: addi a0, a0, 102310; CHECKZICOND-NEXT: ret2311;2312; RV32IXQCI-LABEL: select_cst2:2313; RV32IXQCI: # %bb.0:2314; RV32IXQCI-NEXT: lui a1, 52315; RV32IXQCI-NEXT: addi a1, a1, -4802316; RV32IXQCI-NEXT: qc.selectieqi a0, 0, a1, 102317; RV32IXQCI-NEXT: ret2318 %ret = select i1 %cond, i32 10, i32 200002319 ret i32 %ret2320}2321 2322define i32 @select_cst3(i1 zeroext %cond) {2323; RV32IM-LABEL: select_cst3:2324; RV32IM: # %bb.0:2325; RV32IM-NEXT: bnez a0, .LBB51_22326; RV32IM-NEXT: # %bb.1:2327; RV32IM-NEXT: lui a0, 52328; RV32IM-NEXT: addi a0, a0, -4802329; RV32IM-NEXT: ret2330; RV32IM-NEXT: .LBB51_2:2331; RV32IM-NEXT: lui a0, 72332; RV32IM-NEXT: addi a0, a0, 13282333; RV32IM-NEXT: ret2334;2335; RV64IM-LABEL: select_cst3:2336; RV64IM: # %bb.0:2337; RV64IM-NEXT: bnez a0, .LBB51_22338; RV64IM-NEXT: # %bb.1:2339; RV64IM-NEXT: lui a0, 52340; RV64IM-NEXT: addi a0, a0, -4802341; RV64IM-NEXT: ret2342; RV64IM-NEXT: .LBB51_2:2343; RV64IM-NEXT: lui a0, 72344; RV64IM-NEXT: addi a0, a0, 13282345; RV64IM-NEXT: ret2346;2347; RV64IMXVTCONDOPS-LABEL: select_cst3:2348; RV64IMXVTCONDOPS: # %bb.0:2349; RV64IMXVTCONDOPS-NEXT: lui a1, 10485742350; RV64IMXVTCONDOPS-NEXT: addi a1, a1, -18082351; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a02352; RV64IMXVTCONDOPS-NEXT: lui a1, 72353; RV64IMXVTCONDOPS-NEXT: addi a1, a1, 13282354; RV64IMXVTCONDOPS-NEXT: add a0, a0, a12355; RV64IMXVTCONDOPS-NEXT: ret2356;2357; CHECKZICOND-LABEL: select_cst3:2358; CHECKZICOND: # %bb.0:2359; CHECKZICOND-NEXT: lui a1, 10485742360; CHECKZICOND-NEXT: addi a1, a1, -18082361; CHECKZICOND-NEXT: czero.nez a0, a1, a02362; CHECKZICOND-NEXT: lui a1, 72363; CHECKZICOND-NEXT: addi a1, a1, 13282364; CHECKZICOND-NEXT: add a0, a0, a12365; CHECKZICOND-NEXT: ret2366;2367; RV32IXQCI-LABEL: select_cst3:2368; RV32IXQCI: # %bb.0:2369; RV32IXQCI-NEXT: lui a2, 72370; RV32IXQCI-NEXT: lui a1, 52371; RV32IXQCI-NEXT: addi a1, a1, -4802372; RV32IXQCI-NEXT: beqz a0, .LBB51_22373; RV32IXQCI-NEXT: # %bb.1:2374; RV32IXQCI-NEXT: addi a1, a2, 13282375; RV32IXQCI-NEXT: .LBB51_2:2376; RV32IXQCI-NEXT: mv a0, a12377; RV32IXQCI-NEXT: ret2378 %ret = select i1 %cond, i32 30000, i32 200002379 ret i32 %ret2380}2381 2382define i32 @select_cst4(i1 zeroext %cond) {2383; CHECK-LABEL: select_cst4:2384; CHECK: # %bb.0:2385; CHECK-NEXT: neg a0, a02386; CHECK-NEXT: xori a0, a0, 20472387; CHECK-NEXT: ret2388;2389; RV32IXQCI-LABEL: select_cst4:2390; RV32IXQCI: # %bb.0:2391; RV32IXQCI-NEXT: neg a0, a02392; RV32IXQCI-NEXT: xori a0, a0, 20472393; RV32IXQCI-NEXT: ret2394 %ret = select i1 %cond, i32 -2048, i32 20472395 ret i32 %ret2396}2397 2398define i32 @select_cst5(i1 zeroext %cond) {2399; RV32IM-LABEL: select_cst5:2400; RV32IM: # %bb.0:2401; RV32IM-NEXT: bnez a0, .LBB53_22402; RV32IM-NEXT: # %bb.1:2403; RV32IM-NEXT: lui a0, 12404; RV32IM-NEXT: addi a0, a0, -20472405; RV32IM-NEXT: ret2406; RV32IM-NEXT: .LBB53_2:2407; RV32IM-NEXT: li a0, 20472408; RV32IM-NEXT: ret2409;2410; RV64IM-LABEL: select_cst5:2411; RV64IM: # %bb.0:2412; RV64IM-NEXT: bnez a0, .LBB53_22413; RV64IM-NEXT: # %bb.1:2414; RV64IM-NEXT: lui a0, 12415; RV64IM-NEXT: addi a0, a0, -20472416; RV64IM-NEXT: ret2417; RV64IM-NEXT: .LBB53_2:2418; RV64IM-NEXT: li a0, 20472419; RV64IM-NEXT: ret2420;2421; RV64IMXVTCONDOPS-LABEL: select_cst5:2422; RV64IMXVTCONDOPS: # %bb.0:2423; RV64IMXVTCONDOPS-NEXT: xori a0, a0, 12424; RV64IMXVTCONDOPS-NEXT: slli a0, a0, 12425; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 20472426; RV64IMXVTCONDOPS-NEXT: ret2427;2428; CHECKZICOND-LABEL: select_cst5:2429; CHECKZICOND: # %bb.0:2430; CHECKZICOND-NEXT: xori a0, a0, 12431; CHECKZICOND-NEXT: slli a0, a0, 12432; CHECKZICOND-NEXT: addi a0, a0, 20472433; CHECKZICOND-NEXT: ret2434;2435; RV32IXQCI-LABEL: select_cst5:2436; RV32IXQCI: # %bb.0:2437; RV32IXQCI-NEXT: lui a2, 12438; RV32IXQCI-NEXT: li a1, 20472439; RV32IXQCI-NEXT: bnez a0, .LBB53_22440; RV32IXQCI-NEXT: # %bb.1:2441; RV32IXQCI-NEXT: addi a1, a2, -20472442; RV32IXQCI-NEXT: .LBB53_2:2443; RV32IXQCI-NEXT: mv a0, a12444; RV32IXQCI-NEXT: ret2445 %ret = select i1 %cond, i32 2047, i32 20492446 ret i32 %ret2447}2448 2449define i32 @select_cst5_invert(i1 zeroext %cond) {2450; RV32IM-LABEL: select_cst5_invert:2451; RV32IM: # %bb.0:2452; RV32IM-NEXT: bnez a0, .LBB54_22453; RV32IM-NEXT: # %bb.1:2454; RV32IM-NEXT: li a0, 20472455; RV32IM-NEXT: ret2456; RV32IM-NEXT: .LBB54_2:2457; RV32IM-NEXT: lui a0, 12458; RV32IM-NEXT: addi a0, a0, -20472459; RV32IM-NEXT: ret2460;2461; RV64IM-LABEL: select_cst5_invert:2462; RV64IM: # %bb.0:2463; RV64IM-NEXT: bnez a0, .LBB54_22464; RV64IM-NEXT: # %bb.1:2465; RV64IM-NEXT: li a0, 20472466; RV64IM-NEXT: ret2467; RV64IM-NEXT: .LBB54_2:2468; RV64IM-NEXT: lui a0, 12469; RV64IM-NEXT: addi a0, a0, -20472470; RV64IM-NEXT: ret2471;2472; RV64IMXVTCONDOPS-LABEL: select_cst5_invert:2473; RV64IMXVTCONDOPS: # %bb.0:2474; RV64IMXVTCONDOPS-NEXT: slli a0, a0, 12475; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 20472476; RV64IMXVTCONDOPS-NEXT: ret2477;2478; CHECKZICOND-LABEL: select_cst5_invert:2479; CHECKZICOND: # %bb.0:2480; CHECKZICOND-NEXT: slli a0, a0, 12481; CHECKZICOND-NEXT: addi a0, a0, 20472482; CHECKZICOND-NEXT: ret2483;2484; RV32IXQCI-LABEL: select_cst5_invert:2485; RV32IXQCI: # %bb.0:2486; RV32IXQCI-NEXT: lui a2, 12487; RV32IXQCI-NEXT: li a1, 20472488; RV32IXQCI-NEXT: beqz a0, .LBB54_22489; RV32IXQCI-NEXT: # %bb.1:2490; RV32IXQCI-NEXT: addi a1, a2, -20472491; RV32IXQCI-NEXT: .LBB54_2:2492; RV32IXQCI-NEXT: mv a0, a12493; RV32IXQCI-NEXT: ret2494 %ret = select i1 %cond, i32 2049, i32 20472495 ret i32 %ret2496}2497 2498define i32 @select_cst_diff2(i1 zeroext %cond) {2499; RV32IM-LABEL: select_cst_diff2:2500; RV32IM: # %bb.0:2501; RV32IM-NEXT: bnez a0, .LBB55_22502; RV32IM-NEXT: # %bb.1:2503; RV32IM-NEXT: li a0, 1222504; RV32IM-NEXT: ret2505; RV32IM-NEXT: .LBB55_2:2506; RV32IM-NEXT: li a0, 1202507; RV32IM-NEXT: ret2508;2509; RV64IM-LABEL: select_cst_diff2:2510; RV64IM: # %bb.0:2511; RV64IM-NEXT: bnez a0, .LBB55_22512; RV64IM-NEXT: # %bb.1:2513; RV64IM-NEXT: li a0, 1222514; RV64IM-NEXT: ret2515; RV64IM-NEXT: .LBB55_2:2516; RV64IM-NEXT: li a0, 1202517; RV64IM-NEXT: ret2518;2519; RV64IMXVTCONDOPS-LABEL: select_cst_diff2:2520; RV64IMXVTCONDOPS: # %bb.0:2521; RV64IMXVTCONDOPS-NEXT: xori a0, a0, 12522; RV64IMXVTCONDOPS-NEXT: slli a0, a0, 12523; RV64IMXVTCONDOPS-NEXT: addiw a0, a0, 1202524; RV64IMXVTCONDOPS-NEXT: ret2525;2526; RV32IMZICOND-LABEL: select_cst_diff2:2527; RV32IMZICOND: # %bb.0:2528; RV32IMZICOND-NEXT: xori a0, a0, 12529; RV32IMZICOND-NEXT: slli a0, a0, 12530; RV32IMZICOND-NEXT: addi a0, a0, 1202531; RV32IMZICOND-NEXT: ret2532;2533; RV64IMZICOND-LABEL: select_cst_diff2:2534; RV64IMZICOND: # %bb.0:2535; RV64IMZICOND-NEXT: xori a0, a0, 12536; RV64IMZICOND-NEXT: slli a0, a0, 12537; RV64IMZICOND-NEXT: addiw a0, a0, 1202538; RV64IMZICOND-NEXT: ret2539;2540; RV32IXQCI-LABEL: select_cst_diff2:2541; RV32IXQCI: # %bb.0:2542; RV32IXQCI-NEXT: li a2, 1202543; RV32IXQCI-NEXT: li a1, 1222544; RV32IXQCI-NEXT: qc.mvnei a1, a0, 0, a22545; RV32IXQCI-NEXT: mv a0, a12546; RV32IXQCI-NEXT: ret2547 %ret = select i1 %cond, i32 120, i32 1222548 ret i32 %ret2549}2550 2551define i32 @select_cst_diff2_invert(i1 zeroext %cond) {2552; RV32IM-LABEL: select_cst_diff2_invert:2553; RV32IM: # %bb.0:2554; RV32IM-NEXT: bnez a0, .LBB56_22555; RV32IM-NEXT: # %bb.1:2556; RV32IM-NEXT: li a0, 1202557; RV32IM-NEXT: ret2558; RV32IM-NEXT: .LBB56_2:2559; RV32IM-NEXT: li a0, 1222560; RV32IM-NEXT: ret2561;2562; RV64IM-LABEL: select_cst_diff2_invert:2563; RV64IM: # %bb.0:2564; RV64IM-NEXT: bnez a0, .LBB56_22565; RV64IM-NEXT: # %bb.1:2566; RV64IM-NEXT: li a0, 1202567; RV64IM-NEXT: ret2568; RV64IM-NEXT: .LBB56_2:2569; RV64IM-NEXT: li a0, 1222570; RV64IM-NEXT: ret2571;2572; RV64IMXVTCONDOPS-LABEL: select_cst_diff2_invert:2573; RV64IMXVTCONDOPS: # %bb.0:2574; RV64IMXVTCONDOPS-NEXT: slli a0, a0, 12575; RV64IMXVTCONDOPS-NEXT: addiw a0, a0, 1202576; RV64IMXVTCONDOPS-NEXT: ret2577;2578; RV32IMZICOND-LABEL: select_cst_diff2_invert:2579; RV32IMZICOND: # %bb.0:2580; RV32IMZICOND-NEXT: slli a0, a0, 12581; RV32IMZICOND-NEXT: addi a0, a0, 1202582; RV32IMZICOND-NEXT: ret2583;2584; RV64IMZICOND-LABEL: select_cst_diff2_invert:2585; RV64IMZICOND: # %bb.0:2586; RV64IMZICOND-NEXT: slli a0, a0, 12587; RV64IMZICOND-NEXT: addiw a0, a0, 1202588; RV64IMZICOND-NEXT: ret2589;2590; RV32IXQCI-LABEL: select_cst_diff2_invert:2591; RV32IXQCI: # %bb.0:2592; RV32IXQCI-NEXT: li a2, 1222593; RV32IXQCI-NEXT: li a1, 1202594; RV32IXQCI-NEXT: qc.mvnei a1, a0, 0, a22595; RV32IXQCI-NEXT: mv a0, a12596; RV32IXQCI-NEXT: ret2597 %ret = select i1 %cond, i32 122, i32 1202598 ret i32 %ret2599}2600 2601define i32 @select_cst_diff4(i1 zeroext %cond) {2602; RV32IM-LABEL: select_cst_diff4:2603; RV32IM: # %bb.0:2604; RV32IM-NEXT: bnez a0, .LBB57_22605; RV32IM-NEXT: # %bb.1:2606; RV32IM-NEXT: li a0, 62607; RV32IM-NEXT: ret2608; RV32IM-NEXT: .LBB57_2:2609; RV32IM-NEXT: li a0, 102610; RV32IM-NEXT: ret2611;2612; RV64IM-LABEL: select_cst_diff4:2613; RV64IM: # %bb.0:2614; RV64IM-NEXT: bnez a0, .LBB57_22615; RV64IM-NEXT: # %bb.1:2616; RV64IM-NEXT: li a0, 62617; RV64IM-NEXT: ret2618; RV64IM-NEXT: .LBB57_2:2619; RV64IM-NEXT: li a0, 102620; RV64IM-NEXT: ret2621;2622; RV64IMXVTCONDOPS-LABEL: select_cst_diff4:2623; RV64IMXVTCONDOPS: # %bb.0:2624; RV64IMXVTCONDOPS-NEXT: slli a0, a0, 22625; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 62626; RV64IMXVTCONDOPS-NEXT: ret2627;2628; CHECKZICOND-LABEL: select_cst_diff4:2629; CHECKZICOND: # %bb.0:2630; CHECKZICOND-NEXT: slli a0, a0, 22631; CHECKZICOND-NEXT: addi a0, a0, 62632; CHECKZICOND-NEXT: ret2633;2634; RV32IXQCI-LABEL: select_cst_diff4:2635; RV32IXQCI: # %bb.0:2636; RV32IXQCI-NEXT: li a1, 102637; RV32IXQCI-NEXT: qc.selectinei a0, 0, a1, 62638; RV32IXQCI-NEXT: ret2639 %ret = select i1 %cond, i32 10, i32 62640 ret i32 %ret2641}2642 2643define i32 @select_cst_diff4_invert(i1 zeroext %cond) {2644; RV32IM-LABEL: select_cst_diff4_invert:2645; RV32IM: # %bb.0:2646; RV32IM-NEXT: bnez a0, .LBB58_22647; RV32IM-NEXT: # %bb.1:2648; RV32IM-NEXT: li a0, 102649; RV32IM-NEXT: ret2650; RV32IM-NEXT: .LBB58_2:2651; RV32IM-NEXT: li a0, 62652; RV32IM-NEXT: ret2653;2654; RV64IM-LABEL: select_cst_diff4_invert:2655; RV64IM: # %bb.0:2656; RV64IM-NEXT: bnez a0, .LBB58_22657; RV64IM-NEXT: # %bb.1:2658; RV64IM-NEXT: li a0, 102659; RV64IM-NEXT: ret2660; RV64IM-NEXT: .LBB58_2:2661; RV64IM-NEXT: li a0, 62662; RV64IM-NEXT: ret2663;2664; RV64IMXVTCONDOPS-LABEL: select_cst_diff4_invert:2665; RV64IMXVTCONDOPS: # %bb.0:2666; RV64IMXVTCONDOPS-NEXT: xori a0, a0, 12667; RV64IMXVTCONDOPS-NEXT: slli a0, a0, 22668; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 62669; RV64IMXVTCONDOPS-NEXT: ret2670;2671; CHECKZICOND-LABEL: select_cst_diff4_invert:2672; CHECKZICOND: # %bb.0:2673; CHECKZICOND-NEXT: xori a0, a0, 12674; CHECKZICOND-NEXT: slli a0, a0, 22675; CHECKZICOND-NEXT: addi a0, a0, 62676; CHECKZICOND-NEXT: ret2677;2678; RV32IXQCI-LABEL: select_cst_diff4_invert:2679; RV32IXQCI: # %bb.0:2680; RV32IXQCI-NEXT: li a1, 62681; RV32IXQCI-NEXT: qc.selectinei a0, 0, a1, 102682; RV32IXQCI-NEXT: ret2683 %ret = select i1 %cond, i32 6, i32 102684 ret i32 %ret2685}2686 2687define i32 @select_cst_diff8(i1 zeroext %cond) {2688; RV32IM-LABEL: select_cst_diff8:2689; RV32IM: # %bb.0:2690; RV32IM-NEXT: bnez a0, .LBB59_22691; RV32IM-NEXT: # %bb.1:2692; RV32IM-NEXT: li a0, 62693; RV32IM-NEXT: ret2694; RV32IM-NEXT: .LBB59_2:2695; RV32IM-NEXT: li a0, 142696; RV32IM-NEXT: ret2697;2698; RV64IM-LABEL: select_cst_diff8:2699; RV64IM: # %bb.0:2700; RV64IM-NEXT: bnez a0, .LBB59_22701; RV64IM-NEXT: # %bb.1:2702; RV64IM-NEXT: li a0, 62703; RV64IM-NEXT: ret2704; RV64IM-NEXT: .LBB59_2:2705; RV64IM-NEXT: li a0, 142706; RV64IM-NEXT: ret2707;2708; RV64IMXVTCONDOPS-LABEL: select_cst_diff8:2709; RV64IMXVTCONDOPS: # %bb.0:2710; RV64IMXVTCONDOPS-NEXT: slli a0, a0, 32711; RV64IMXVTCONDOPS-NEXT: addiw a0, a0, 62712; RV64IMXVTCONDOPS-NEXT: ret2713;2714; RV32IMZICOND-LABEL: select_cst_diff8:2715; RV32IMZICOND: # %bb.0:2716; RV32IMZICOND-NEXT: slli a0, a0, 32717; RV32IMZICOND-NEXT: addi a0, a0, 62718; RV32IMZICOND-NEXT: ret2719;2720; RV64IMZICOND-LABEL: select_cst_diff8:2721; RV64IMZICOND: # %bb.0:2722; RV64IMZICOND-NEXT: slli a0, a0, 32723; RV64IMZICOND-NEXT: addiw a0, a0, 62724; RV64IMZICOND-NEXT: ret2725;2726; RV32IXQCI-LABEL: select_cst_diff8:2727; RV32IXQCI: # %bb.0:2728; RV32IXQCI-NEXT: li a1, 142729; RV32IXQCI-NEXT: qc.selectinei a0, 0, a1, 62730; RV32IXQCI-NEXT: ret2731 %ret = select i1 %cond, i32 14, i32 62732 ret i32 %ret2733}2734 2735define i32 @select_cst_diff8_invert(i1 zeroext %cond) {2736; RV32IM-LABEL: select_cst_diff8_invert:2737; RV32IM: # %bb.0:2738; RV32IM-NEXT: bnez a0, .LBB60_22739; RV32IM-NEXT: # %bb.1:2740; RV32IM-NEXT: li a0, 142741; RV32IM-NEXT: ret2742; RV32IM-NEXT: .LBB60_2:2743; RV32IM-NEXT: li a0, 62744; RV32IM-NEXT: ret2745;2746; RV64IM-LABEL: select_cst_diff8_invert:2747; RV64IM: # %bb.0:2748; RV64IM-NEXT: bnez a0, .LBB60_22749; RV64IM-NEXT: # %bb.1:2750; RV64IM-NEXT: li a0, 142751; RV64IM-NEXT: ret2752; RV64IM-NEXT: .LBB60_2:2753; RV64IM-NEXT: li a0, 62754; RV64IM-NEXT: ret2755;2756; RV64IMXVTCONDOPS-LABEL: select_cst_diff8_invert:2757; RV64IMXVTCONDOPS: # %bb.0:2758; RV64IMXVTCONDOPS-NEXT: xori a0, a0, 12759; RV64IMXVTCONDOPS-NEXT: slli a0, a0, 32760; RV64IMXVTCONDOPS-NEXT: addiw a0, a0, 62761; RV64IMXVTCONDOPS-NEXT: ret2762;2763; RV32IMZICOND-LABEL: select_cst_diff8_invert:2764; RV32IMZICOND: # %bb.0:2765; RV32IMZICOND-NEXT: xori a0, a0, 12766; RV32IMZICOND-NEXT: slli a0, a0, 32767; RV32IMZICOND-NEXT: addi a0, a0, 62768; RV32IMZICOND-NEXT: ret2769;2770; RV64IMZICOND-LABEL: select_cst_diff8_invert:2771; RV64IMZICOND: # %bb.0:2772; RV64IMZICOND-NEXT: xori a0, a0, 12773; RV64IMZICOND-NEXT: slli a0, a0, 32774; RV64IMZICOND-NEXT: addiw a0, a0, 62775; RV64IMZICOND-NEXT: ret2776;2777; RV32IXQCI-LABEL: select_cst_diff8_invert:2778; RV32IXQCI: # %bb.0:2779; RV32IXQCI-NEXT: li a1, 62780; RV32IXQCI-NEXT: qc.selectinei a0, 0, a1, 142781; RV32IXQCI-NEXT: ret2782 %ret = select i1 %cond, i32 6, i32 142783 ret i32 %ret2784}2785 2786 2787define i32 @select_cst_diff1024(i1 zeroext %cond) {2788; RV32IM-LABEL: select_cst_diff1024:2789; RV32IM: # %bb.0:2790; RV32IM-NEXT: bnez a0, .LBB61_22791; RV32IM-NEXT: # %bb.1:2792; RV32IM-NEXT: li a0, 62793; RV32IM-NEXT: ret2794; RV32IM-NEXT: .LBB61_2:2795; RV32IM-NEXT: li a0, 10302796; RV32IM-NEXT: ret2797;2798; RV64IM-LABEL: select_cst_diff1024:2799; RV64IM: # %bb.0:2800; RV64IM-NEXT: bnez a0, .LBB61_22801; RV64IM-NEXT: # %bb.1:2802; RV64IM-NEXT: li a0, 62803; RV64IM-NEXT: ret2804; RV64IM-NEXT: .LBB61_2:2805; RV64IM-NEXT: li a0, 10302806; RV64IM-NEXT: ret2807;2808; RV64IMXVTCONDOPS-LABEL: select_cst_diff1024:2809; RV64IMXVTCONDOPS: # %bb.0:2810; RV64IMXVTCONDOPS-NEXT: slli a0, a0, 102811; RV64IMXVTCONDOPS-NEXT: addiw a0, a0, 62812; RV64IMXVTCONDOPS-NEXT: ret2813;2814; RV32IMZICOND-LABEL: select_cst_diff1024:2815; RV32IMZICOND: # %bb.0:2816; RV32IMZICOND-NEXT: slli a0, a0, 102817; RV32IMZICOND-NEXT: addi a0, a0, 62818; RV32IMZICOND-NEXT: ret2819;2820; RV64IMZICOND-LABEL: select_cst_diff1024:2821; RV64IMZICOND: # %bb.0:2822; RV64IMZICOND-NEXT: slli a0, a0, 102823; RV64IMZICOND-NEXT: addiw a0, a0, 62824; RV64IMZICOND-NEXT: ret2825;2826; RV32IXQCI-LABEL: select_cst_diff1024:2827; RV32IXQCI: # %bb.0:2828; RV32IXQCI-NEXT: li a1, 10302829; RV32IXQCI-NEXT: qc.selectinei a0, 0, a1, 62830; RV32IXQCI-NEXT: ret2831 %ret = select i1 %cond, i32 1030, i32 62832 ret i32 %ret2833}2834 2835define i32 @select_cst_diff1024_invert(i1 zeroext %cond) {2836; RV32IM-LABEL: select_cst_diff1024_invert:2837; RV32IM: # %bb.0:2838; RV32IM-NEXT: bnez a0, .LBB62_22839; RV32IM-NEXT: # %bb.1:2840; RV32IM-NEXT: li a0, 10302841; RV32IM-NEXT: ret2842; RV32IM-NEXT: .LBB62_2:2843; RV32IM-NEXT: li a0, 62844; RV32IM-NEXT: ret2845;2846; RV64IM-LABEL: select_cst_diff1024_invert:2847; RV64IM: # %bb.0:2848; RV64IM-NEXT: bnez a0, .LBB62_22849; RV64IM-NEXT: # %bb.1:2850; RV64IM-NEXT: li a0, 10302851; RV64IM-NEXT: ret2852; RV64IM-NEXT: .LBB62_2:2853; RV64IM-NEXT: li a0, 62854; RV64IM-NEXT: ret2855;2856; RV64IMXVTCONDOPS-LABEL: select_cst_diff1024_invert:2857; RV64IMXVTCONDOPS: # %bb.0:2858; RV64IMXVTCONDOPS-NEXT: xori a0, a0, 12859; RV64IMXVTCONDOPS-NEXT: slli a0, a0, 102860; RV64IMXVTCONDOPS-NEXT: addiw a0, a0, 62861; RV64IMXVTCONDOPS-NEXT: ret2862;2863; RV32IMZICOND-LABEL: select_cst_diff1024_invert:2864; RV32IMZICOND: # %bb.0:2865; RV32IMZICOND-NEXT: xori a0, a0, 12866; RV32IMZICOND-NEXT: slli a0, a0, 102867; RV32IMZICOND-NEXT: addi a0, a0, 62868; RV32IMZICOND-NEXT: ret2869;2870; RV64IMZICOND-LABEL: select_cst_diff1024_invert:2871; RV64IMZICOND: # %bb.0:2872; RV64IMZICOND-NEXT: xori a0, a0, 12873; RV64IMZICOND-NEXT: slli a0, a0, 102874; RV64IMZICOND-NEXT: addiw a0, a0, 62875; RV64IMZICOND-NEXT: ret2876;2877; RV32IXQCI-LABEL: select_cst_diff1024_invert:2878; RV32IXQCI: # %bb.0:2879; RV32IXQCI-NEXT: li a1, 10302880; RV32IXQCI-NEXT: qc.selectieqi a0, 0, a1, 62881; RV32IXQCI-NEXT: ret2882 %ret = select i1 %cond, i32 6, i32 10302883 ret i32 %ret2884}2885 2886 2887@select_redundant_czero_eqz_data = global i32 0, align 42888 2889define void @select_redundant_czero_eqz1(ptr %0, ptr %1) {2890; RV32IM-LABEL: select_redundant_czero_eqz1:2891; RV32IM: # %bb.0: # %entry2892; RV32IM-NEXT: bnez a0, .LBB63_22893; RV32IM-NEXT: # %bb.1:2894; RV32IM-NEXT: lui a0, %hi(select_redundant_czero_eqz_data)2895; RV32IM-NEXT: addi a0, a0, %lo(select_redundant_czero_eqz_data)2896; RV32IM-NEXT: .LBB63_2: # %entry2897; RV32IM-NEXT: sw a0, 0(a1)2898; RV32IM-NEXT: ret2899;2900; RV64IM-LABEL: select_redundant_czero_eqz1:2901; RV64IM: # %bb.0: # %entry2902; RV64IM-NEXT: bnez a0, .LBB63_22903; RV64IM-NEXT: # %bb.1:2904; RV64IM-NEXT: lui a0, %hi(select_redundant_czero_eqz_data)2905; RV64IM-NEXT: addi a0, a0, %lo(select_redundant_czero_eqz_data)2906; RV64IM-NEXT: .LBB63_2: # %entry2907; RV64IM-NEXT: sd a0, 0(a1)2908; RV64IM-NEXT: ret2909;2910; RV64IMXVTCONDOPS-LABEL: select_redundant_czero_eqz1:2911; RV64IMXVTCONDOPS: # %bb.0: # %entry2912; RV64IMXVTCONDOPS-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)2913; RV64IMXVTCONDOPS-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)2914; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a02915; RV64IMXVTCONDOPS-NEXT: or a0, a2, a02916; RV64IMXVTCONDOPS-NEXT: sd a0, 0(a1)2917; RV64IMXVTCONDOPS-NEXT: ret2918;2919; RV32IMZICOND-LABEL: select_redundant_czero_eqz1:2920; RV32IMZICOND: # %bb.0: # %entry2921; RV32IMZICOND-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)2922; RV32IMZICOND-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)2923; RV32IMZICOND-NEXT: czero.nez a2, a2, a02924; RV32IMZICOND-NEXT: or a0, a2, a02925; RV32IMZICOND-NEXT: sw a0, 0(a1)2926; RV32IMZICOND-NEXT: ret2927;2928; RV64IMZICOND-LABEL: select_redundant_czero_eqz1:2929; RV64IMZICOND: # %bb.0: # %entry2930; RV64IMZICOND-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)2931; RV64IMZICOND-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)2932; RV64IMZICOND-NEXT: czero.nez a2, a2, a02933; RV64IMZICOND-NEXT: or a0, a2, a02934; RV64IMZICOND-NEXT: sd a0, 0(a1)2935; RV64IMZICOND-NEXT: ret2936;2937; RV32IXQCI-LABEL: select_redundant_czero_eqz1:2938; RV32IXQCI: # %bb.0: # %entry2939; RV32IXQCI-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)2940; RV32IXQCI-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)2941; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a02942; RV32IXQCI-NEXT: sw a2, 0(a1)2943; RV32IXQCI-NEXT: ret2944entry:2945 %3 = icmp eq ptr %0, null2946 %4 = select i1 %3, ptr @select_redundant_czero_eqz_data, ptr %02947 store ptr %4, ptr %1, align 82948 ret void2949}2950 2951define void @select_redundant_czero_eqz2(ptr %0, ptr %1) {2952; RV32IM-LABEL: select_redundant_czero_eqz2:2953; RV32IM: # %bb.0: # %entry2954; RV32IM-NEXT: bnez a0, .LBB64_22955; RV32IM-NEXT: # %bb.1: # %entry2956; RV32IM-NEXT: lui a0, %hi(select_redundant_czero_eqz_data)2957; RV32IM-NEXT: addi a0, a0, %lo(select_redundant_czero_eqz_data)2958; RV32IM-NEXT: .LBB64_2: # %entry2959; RV32IM-NEXT: sw a0, 0(a1)2960; RV32IM-NEXT: ret2961;2962; RV64IM-LABEL: select_redundant_czero_eqz2:2963; RV64IM: # %bb.0: # %entry2964; RV64IM-NEXT: bnez a0, .LBB64_22965; RV64IM-NEXT: # %bb.1: # %entry2966; RV64IM-NEXT: lui a0, %hi(select_redundant_czero_eqz_data)2967; RV64IM-NEXT: addi a0, a0, %lo(select_redundant_czero_eqz_data)2968; RV64IM-NEXT: .LBB64_2: # %entry2969; RV64IM-NEXT: sd a0, 0(a1)2970; RV64IM-NEXT: ret2971;2972; RV64IMXVTCONDOPS-LABEL: select_redundant_czero_eqz2:2973; RV64IMXVTCONDOPS: # %bb.0: # %entry2974; RV64IMXVTCONDOPS-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)2975; RV64IMXVTCONDOPS-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)2976; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a02977; RV64IMXVTCONDOPS-NEXT: or a0, a0, a22978; RV64IMXVTCONDOPS-NEXT: sd a0, 0(a1)2979; RV64IMXVTCONDOPS-NEXT: ret2980;2981; RV32IMZICOND-LABEL: select_redundant_czero_eqz2:2982; RV32IMZICOND: # %bb.0: # %entry2983; RV32IMZICOND-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)2984; RV32IMZICOND-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)2985; RV32IMZICOND-NEXT: czero.nez a2, a2, a02986; RV32IMZICOND-NEXT: or a0, a0, a22987; RV32IMZICOND-NEXT: sw a0, 0(a1)2988; RV32IMZICOND-NEXT: ret2989;2990; RV64IMZICOND-LABEL: select_redundant_czero_eqz2:2991; RV64IMZICOND: # %bb.0: # %entry2992; RV64IMZICOND-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)2993; RV64IMZICOND-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)2994; RV64IMZICOND-NEXT: czero.nez a2, a2, a02995; RV64IMZICOND-NEXT: or a0, a0, a22996; RV64IMZICOND-NEXT: sd a0, 0(a1)2997; RV64IMZICOND-NEXT: ret2998;2999; RV32IXQCI-LABEL: select_redundant_czero_eqz2:3000; RV32IXQCI: # %bb.0: # %entry3001; RV32IXQCI-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)3002; RV32IXQCI-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)3003; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a03004; RV32IXQCI-NEXT: sw a2, 0(a1)3005; RV32IXQCI-NEXT: ret3006entry:3007 %3 = icmp ne ptr %0, null3008 %4 = select i1 %3, ptr %0, ptr @select_redundant_czero_eqz_data3009 store ptr %4, ptr %1, align 83010 ret void3011}3012