1220 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV32I4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefix=RV64I6 7define i1 @and_icmp_eq(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {8; RV32I-LABEL: and_icmp_eq:9; RV32I: # %bb.0:10; RV32I-NEXT: xor a0, a0, a111; RV32I-NEXT: xor a2, a2, a312; RV32I-NEXT: or a0, a0, a213; RV32I-NEXT: seqz a0, a014; RV32I-NEXT: ret15;16; RV64I-LABEL: and_icmp_eq:17; RV64I: # %bb.0:18; RV64I-NEXT: xor a0, a0, a119; RV64I-NEXT: xor a2, a2, a320; RV64I-NEXT: or a0, a0, a221; RV64I-NEXT: seqz a0, a022; RV64I-NEXT: ret23 %cmp1 = icmp eq i32 %a, %b24 %cmp2 = icmp eq i32 %c, %d25 %and = and i1 %cmp1, %cmp226 ret i1 %and27}28 29define i1 @or_icmp_ne(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {30; RV32I-LABEL: or_icmp_ne:31; RV32I: # %bb.0:32; RV32I-NEXT: xor a0, a0, a133; RV32I-NEXT: xor a2, a2, a334; RV32I-NEXT: or a0, a0, a235; RV32I-NEXT: snez a0, a036; RV32I-NEXT: ret37;38; RV64I-LABEL: or_icmp_ne:39; RV64I: # %bb.0:40; RV64I-NEXT: xor a0, a0, a141; RV64I-NEXT: xor a2, a2, a342; RV64I-NEXT: or a0, a0, a243; RV64I-NEXT: snez a0, a044; RV64I-NEXT: ret45 %cmp1 = icmp ne i32 %a, %b46 %cmp2 = icmp ne i32 %c, %d47 %or = or i1 %cmp1, %cmp248 ret i1 %or49}50 51define i1 @or_icmps_const_1bit_diff(i64 %x) nounwind {52; RV32I-LABEL: or_icmps_const_1bit_diff:53; RV32I: # %bb.0:54; RV32I-NEXT: addi a2, a0, -1355; RV32I-NEXT: sltu a0, a2, a056; RV32I-NEXT: add a0, a1, a057; RV32I-NEXT: addi a0, a0, -158; RV32I-NEXT: andi a2, a2, -559; RV32I-NEXT: or a0, a2, a060; RV32I-NEXT: seqz a0, a061; RV32I-NEXT: ret62;63; RV64I-LABEL: or_icmps_const_1bit_diff:64; RV64I: # %bb.0:65; RV64I-NEXT: addi a0, a0, -1366; RV64I-NEXT: andi a0, a0, -567; RV64I-NEXT: seqz a0, a068; RV64I-NEXT: ret69 %a = icmp eq i64 %x, 1770 %b = icmp eq i64 %x, 1371 %r = or i1 %a, %b72 ret i1 %r73}74 75define i1 @and_icmps_const_1bit_diff(i32 %x) nounwind {76; RV32I-LABEL: and_icmps_const_1bit_diff:77; RV32I: # %bb.0:78; RV32I-NEXT: addi a0, a0, -4479; RV32I-NEXT: andi a0, a0, -1780; RV32I-NEXT: snez a0, a081; RV32I-NEXT: ret82;83; RV64I-LABEL: and_icmps_const_1bit_diff:84; RV64I: # %bb.0:85; RV64I-NEXT: addiw a0, a0, -4486; RV64I-NEXT: andi a0, a0, -1787; RV64I-NEXT: snez a0, a088; RV64I-NEXT: ret89 %a = icmp ne i32 %x, 4490 %b = icmp ne i32 %x, 6091 %r = and i1 %a, %b92 ret i1 %r93}94 95define i1 @and_icmps_const_not1bit_diff(i32 %x) nounwind {96; RV32I-LABEL: and_icmps_const_not1bit_diff:97; RV32I: # %bb.0:98; RV32I-NEXT: addi a1, a0, -4499; RV32I-NEXT: addi a0, a0, -92100; RV32I-NEXT: snez a1, a1101; RV32I-NEXT: snez a0, a0102; RV32I-NEXT: and a0, a1, a0103; RV32I-NEXT: ret104;105; RV64I-LABEL: and_icmps_const_not1bit_diff:106; RV64I: # %bb.0:107; RV64I-NEXT: addiw a1, a0, -44108; RV64I-NEXT: addiw a0, a0, -92109; RV64I-NEXT: snez a1, a1110; RV64I-NEXT: snez a0, a0111; RV64I-NEXT: and a0, a1, a0112; RV64I-NEXT: ret113 %a = icmp ne i32 %x, 44114 %b = icmp ne i32 %x, 92115 %r = and i1 %a, %b116 ret i1 %r117}118 119define i1 @and_icmp_sge(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {120; RV32I-LABEL: and_icmp_sge:121; RV32I: # %bb.0:122; RV32I-NEXT: slt a0, a0, a1123; RV32I-NEXT: slt a1, a2, a3124; RV32I-NEXT: or a0, a0, a1125; RV32I-NEXT: xori a0, a0, 1126; RV32I-NEXT: ret127;128; RV64I-LABEL: and_icmp_sge:129; RV64I: # %bb.0:130; RV64I-NEXT: slt a0, a0, a1131; RV64I-NEXT: slt a1, a2, a3132; RV64I-NEXT: or a0, a0, a1133; RV64I-NEXT: xori a0, a0, 1134; RV64I-NEXT: ret135 %cmp1 = icmp sge i32 %a, %b136 %cmp2 = icmp sge i32 %c, %d137 %and = and i1 %cmp1, %cmp2138 ret i1 %and139}140 141define i1 @and_icmp_sle(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {142; RV32I-LABEL: and_icmp_sle:143; RV32I: # %bb.0:144; RV32I-NEXT: slt a0, a1, a0145; RV32I-NEXT: slt a1, a3, a2146; RV32I-NEXT: or a0, a0, a1147; RV32I-NEXT: xori a0, a0, 1148; RV32I-NEXT: ret149;150; RV64I-LABEL: and_icmp_sle:151; RV64I: # %bb.0:152; RV64I-NEXT: slt a0, a1, a0153; RV64I-NEXT: slt a1, a3, a2154; RV64I-NEXT: or a0, a0, a1155; RV64I-NEXT: xori a0, a0, 1156; RV64I-NEXT: ret157 %cmp1 = icmp sle i32 %a, %b158 %cmp2 = icmp sle i32 %c, %d159 %and = and i1 %cmp1, %cmp2160 ret i1 %and161}162 163define i1 @and_icmp_uge(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {164; RV32I-LABEL: and_icmp_uge:165; RV32I: # %bb.0:166; RV32I-NEXT: sltu a0, a0, a1167; RV32I-NEXT: sltu a1, a2, a3168; RV32I-NEXT: or a0, a0, a1169; RV32I-NEXT: xori a0, a0, 1170; RV32I-NEXT: ret171;172; RV64I-LABEL: and_icmp_uge:173; RV64I: # %bb.0:174; RV64I-NEXT: sltu a0, a0, a1175; RV64I-NEXT: sltu a1, a2, a3176; RV64I-NEXT: or a0, a0, a1177; RV64I-NEXT: xori a0, a0, 1178; RV64I-NEXT: ret179 %cmp1 = icmp uge i32 %a, %b180 %cmp2 = icmp uge i32 %c, %d181 %and = and i1 %cmp1, %cmp2182 ret i1 %and183}184 185define i1 @and_icmp_ule(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {186; RV32I-LABEL: and_icmp_ule:187; RV32I: # %bb.0:188; RV32I-NEXT: sltu a0, a1, a0189; RV32I-NEXT: sltu a1, a3, a2190; RV32I-NEXT: or a0, a0, a1191; RV32I-NEXT: xori a0, a0, 1192; RV32I-NEXT: ret193;194; RV64I-LABEL: and_icmp_ule:195; RV64I: # %bb.0:196; RV64I-NEXT: sltu a0, a1, a0197; RV64I-NEXT: sltu a1, a3, a2198; RV64I-NEXT: or a0, a0, a1199; RV64I-NEXT: xori a0, a0, 1200; RV64I-NEXT: ret201 %cmp1 = icmp ule i32 %a, %b202 %cmp2 = icmp ule i32 %c, %d203 %and = and i1 %cmp1, %cmp2204 ret i1 %and205}206 207define i1 @or_icmp_sge(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {208; RV32I-LABEL: or_icmp_sge:209; RV32I: # %bb.0:210; RV32I-NEXT: slt a0, a0, a1211; RV32I-NEXT: slt a1, a2, a3212; RV32I-NEXT: and a0, a0, a1213; RV32I-NEXT: xori a0, a0, 1214; RV32I-NEXT: ret215;216; RV64I-LABEL: or_icmp_sge:217; RV64I: # %bb.0:218; RV64I-NEXT: slt a0, a0, a1219; RV64I-NEXT: slt a1, a2, a3220; RV64I-NEXT: and a0, a0, a1221; RV64I-NEXT: xori a0, a0, 1222; RV64I-NEXT: ret223 %cmp1 = icmp sge i32 %a, %b224 %cmp2 = icmp sge i32 %c, %d225 %and = or i1 %cmp1, %cmp2226 ret i1 %and227}228 229define i1 @or_icmp_sle(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {230; RV32I-LABEL: or_icmp_sle:231; RV32I: # %bb.0:232; RV32I-NEXT: slt a0, a1, a0233; RV32I-NEXT: slt a1, a3, a2234; RV32I-NEXT: and a0, a0, a1235; RV32I-NEXT: xori a0, a0, 1236; RV32I-NEXT: ret237;238; RV64I-LABEL: or_icmp_sle:239; RV64I: # %bb.0:240; RV64I-NEXT: slt a0, a1, a0241; RV64I-NEXT: slt a1, a3, a2242; RV64I-NEXT: and a0, a0, a1243; RV64I-NEXT: xori a0, a0, 1244; RV64I-NEXT: ret245 %cmp1 = icmp sle i32 %a, %b246 %cmp2 = icmp sle i32 %c, %d247 %and = or i1 %cmp1, %cmp2248 ret i1 %and249}250 251define i1 @or_icmp_uge(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {252; RV32I-LABEL: or_icmp_uge:253; RV32I: # %bb.0:254; RV32I-NEXT: sltu a0, a0, a1255; RV32I-NEXT: sltu a1, a2, a3256; RV32I-NEXT: and a0, a0, a1257; RV32I-NEXT: xori a0, a0, 1258; RV32I-NEXT: ret259;260; RV64I-LABEL: or_icmp_uge:261; RV64I: # %bb.0:262; RV64I-NEXT: sltu a0, a0, a1263; RV64I-NEXT: sltu a1, a2, a3264; RV64I-NEXT: and a0, a0, a1265; RV64I-NEXT: xori a0, a0, 1266; RV64I-NEXT: ret267 %cmp1 = icmp uge i32 %a, %b268 %cmp2 = icmp uge i32 %c, %d269 %and = or i1 %cmp1, %cmp2270 ret i1 %and271}272 273define i1 @or_icmp_ule(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {274; RV32I-LABEL: or_icmp_ule:275; RV32I: # %bb.0:276; RV32I-NEXT: sltu a0, a1, a0277; RV32I-NEXT: sltu a1, a3, a2278; RV32I-NEXT: and a0, a0, a1279; RV32I-NEXT: xori a0, a0, 1280; RV32I-NEXT: ret281;282; RV64I-LABEL: or_icmp_ule:283; RV64I: # %bb.0:284; RV64I-NEXT: sltu a0, a1, a0285; RV64I-NEXT: sltu a1, a3, a2286; RV64I-NEXT: and a0, a0, a1287; RV64I-NEXT: xori a0, a0, 1288; RV64I-NEXT: ret289 %cmp1 = icmp ule i32 %a, %b290 %cmp2 = icmp ule i32 %c, %d291 %and = or i1 %cmp1, %cmp2292 ret i1 %and293}294 295declare void @bar(...)296 297define void @and_sge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {298; RV32I-LABEL: and_sge_eq:299; RV32I: # %bb.0:300; RV32I-NEXT: blt a0, a1, .LBB13_3301; RV32I-NEXT: # %bb.1:302; RV32I-NEXT: bne a2, a3, .LBB13_3303; RV32I-NEXT: # %bb.2:304; RV32I-NEXT: ret305; RV32I-NEXT: .LBB13_3:306; RV32I-NEXT: tail bar307;308; RV64I-LABEL: and_sge_eq:309; RV64I: # %bb.0:310; RV64I-NEXT: blt a0, a1, .LBB13_3311; RV64I-NEXT: # %bb.1:312; RV64I-NEXT: bne a2, a3, .LBB13_3313; RV64I-NEXT: # %bb.2:314; RV64I-NEXT: ret315; RV64I-NEXT: .LBB13_3:316; RV64I-NEXT: tail bar317 %5 = icmp sge i32 %0, %1318 %6 = icmp eq i32 %2, %3319 %7 = and i1 %5, %6320 br i1 %7, label %9, label %8321 3228: ; preds = %4323 tail call void @bar()324 br label %9325 3269: ; preds = %8, %4327 ret void328}329 330define void @and_sle_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {331; RV32I-LABEL: and_sle_eq:332; RV32I: # %bb.0:333; RV32I-NEXT: blt a1, a0, .LBB14_3334; RV32I-NEXT: # %bb.1:335; RV32I-NEXT: bne a2, a3, .LBB14_3336; RV32I-NEXT: # %bb.2:337; RV32I-NEXT: ret338; RV32I-NEXT: .LBB14_3:339; RV32I-NEXT: tail bar340;341; RV64I-LABEL: and_sle_eq:342; RV64I: # %bb.0:343; RV64I-NEXT: blt a1, a0, .LBB14_3344; RV64I-NEXT: # %bb.1:345; RV64I-NEXT: bne a2, a3, .LBB14_3346; RV64I-NEXT: # %bb.2:347; RV64I-NEXT: ret348; RV64I-NEXT: .LBB14_3:349; RV64I-NEXT: tail bar350 %5 = icmp sle i32 %0, %1351 %6 = icmp eq i32 %2, %3352 %7 = and i1 %5, %6353 br i1 %7, label %9, label %8354 3558: ; preds = %4356 tail call void @bar()357 br label %9358 3599: ; preds = %8, %4360 ret void361}362 363define void @and_uge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {364; RV32I-LABEL: and_uge_eq:365; RV32I: # %bb.0:366; RV32I-NEXT: bltu a0, a1, .LBB15_3367; RV32I-NEXT: # %bb.1:368; RV32I-NEXT: bne a2, a3, .LBB15_3369; RV32I-NEXT: # %bb.2:370; RV32I-NEXT: ret371; RV32I-NEXT: .LBB15_3:372; RV32I-NEXT: tail bar373;374; RV64I-LABEL: and_uge_eq:375; RV64I: # %bb.0:376; RV64I-NEXT: bltu a0, a1, .LBB15_3377; RV64I-NEXT: # %bb.1:378; RV64I-NEXT: bne a2, a3, .LBB15_3379; RV64I-NEXT: # %bb.2:380; RV64I-NEXT: ret381; RV64I-NEXT: .LBB15_3:382; RV64I-NEXT: tail bar383 %5 = icmp uge i32 %0, %1384 %6 = icmp eq i32 %2, %3385 %7 = and i1 %5, %6386 br i1 %7, label %9, label %8387 3888: ; preds = %4389 tail call void @bar()390 br label %9391 3929: ; preds = %8, %4393 ret void394}395 396define void @and_ule_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {397; RV32I-LABEL: and_ule_eq:398; RV32I: # %bb.0:399; RV32I-NEXT: bltu a1, a0, .LBB16_3400; RV32I-NEXT: # %bb.1:401; RV32I-NEXT: bne a2, a3, .LBB16_3402; RV32I-NEXT: # %bb.2:403; RV32I-NEXT: ret404; RV32I-NEXT: .LBB16_3:405; RV32I-NEXT: tail bar406;407; RV64I-LABEL: and_ule_eq:408; RV64I: # %bb.0:409; RV64I-NEXT: bltu a1, a0, .LBB16_3410; RV64I-NEXT: # %bb.1:411; RV64I-NEXT: bne a2, a3, .LBB16_3412; RV64I-NEXT: # %bb.2:413; RV64I-NEXT: ret414; RV64I-NEXT: .LBB16_3:415; RV64I-NEXT: tail bar416 %5 = icmp ule i32 %0, %1417 %6 = icmp eq i32 %2, %3418 %7 = and i1 %5, %6419 br i1 %7, label %9, label %8420 4218: ; preds = %4422 tail call void @bar()423 br label %9424 4259: ; preds = %8, %4426 ret void427}428 429define void @and_sge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {430; RV32I-LABEL: and_sge_ne:431; RV32I: # %bb.0:432; RV32I-NEXT: blt a0, a1, .LBB17_3433; RV32I-NEXT: # %bb.1:434; RV32I-NEXT: beq a2, a3, .LBB17_3435; RV32I-NEXT: # %bb.2:436; RV32I-NEXT: ret437; RV32I-NEXT: .LBB17_3:438; RV32I-NEXT: tail bar439;440; RV64I-LABEL: and_sge_ne:441; RV64I: # %bb.0:442; RV64I-NEXT: blt a0, a1, .LBB17_3443; RV64I-NEXT: # %bb.1:444; RV64I-NEXT: beq a2, a3, .LBB17_3445; RV64I-NEXT: # %bb.2:446; RV64I-NEXT: ret447; RV64I-NEXT: .LBB17_3:448; RV64I-NEXT: tail bar449 %5 = icmp sge i32 %0, %1450 %6 = icmp ne i32 %2, %3451 %7 = and i1 %5, %6452 br i1 %7, label %9, label %8453 4548: ; preds = %4455 tail call void @bar()456 br label %9457 4589: ; preds = %8, %4459 ret void460}461 462define void @and_sle_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {463; RV32I-LABEL: and_sle_ne:464; RV32I: # %bb.0:465; RV32I-NEXT: blt a1, a0, .LBB18_3466; RV32I-NEXT: # %bb.1:467; RV32I-NEXT: beq a2, a3, .LBB18_3468; RV32I-NEXT: # %bb.2:469; RV32I-NEXT: ret470; RV32I-NEXT: .LBB18_3:471; RV32I-NEXT: tail bar472;473; RV64I-LABEL: and_sle_ne:474; RV64I: # %bb.0:475; RV64I-NEXT: blt a1, a0, .LBB18_3476; RV64I-NEXT: # %bb.1:477; RV64I-NEXT: beq a2, a3, .LBB18_3478; RV64I-NEXT: # %bb.2:479; RV64I-NEXT: ret480; RV64I-NEXT: .LBB18_3:481; RV64I-NEXT: tail bar482 %5 = icmp sle i32 %0, %1483 %6 = icmp ne i32 %2, %3484 %7 = and i1 %5, %6485 br i1 %7, label %9, label %8486 4878: ; preds = %4488 tail call void @bar()489 br label %9490 4919: ; preds = %8, %4492 ret void493}494 495define void @and_uge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {496; RV32I-LABEL: and_uge_ne:497; RV32I: # %bb.0:498; RV32I-NEXT: bltu a0, a1, .LBB19_3499; RV32I-NEXT: # %bb.1:500; RV32I-NEXT: beq a2, a3, .LBB19_3501; RV32I-NEXT: # %bb.2:502; RV32I-NEXT: ret503; RV32I-NEXT: .LBB19_3:504; RV32I-NEXT: tail bar505;506; RV64I-LABEL: and_uge_ne:507; RV64I: # %bb.0:508; RV64I-NEXT: bltu a0, a1, .LBB19_3509; RV64I-NEXT: # %bb.1:510; RV64I-NEXT: beq a2, a3, .LBB19_3511; RV64I-NEXT: # %bb.2:512; RV64I-NEXT: ret513; RV64I-NEXT: .LBB19_3:514; RV64I-NEXT: tail bar515 %5 = icmp uge i32 %0, %1516 %6 = icmp ne i32 %2, %3517 %7 = and i1 %5, %6518 br i1 %7, label %9, label %8519 5208: ; preds = %4521 tail call void @bar()522 br label %9523 5249: ; preds = %8, %4525 ret void526}527 528define void @and_ule_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {529; RV32I-LABEL: and_ule_ne:530; RV32I: # %bb.0:531; RV32I-NEXT: bltu a1, a0, .LBB20_3532; RV32I-NEXT: # %bb.1:533; RV32I-NEXT: beq a2, a3, .LBB20_3534; RV32I-NEXT: # %bb.2:535; RV32I-NEXT: ret536; RV32I-NEXT: .LBB20_3:537; RV32I-NEXT: tail bar538;539; RV64I-LABEL: and_ule_ne:540; RV64I: # %bb.0:541; RV64I-NEXT: bltu a1, a0, .LBB20_3542; RV64I-NEXT: # %bb.1:543; RV64I-NEXT: beq a2, a3, .LBB20_3544; RV64I-NEXT: # %bb.2:545; RV64I-NEXT: ret546; RV64I-NEXT: .LBB20_3:547; RV64I-NEXT: tail bar548 %5 = icmp ule i32 %0, %1549 %6 = icmp ne i32 %2, %3550 %7 = and i1 %5, %6551 br i1 %7, label %9, label %8552 5538: ; preds = %4554 tail call void @bar()555 br label %9556 5579: ; preds = %8, %4558 ret void559}560 561define void @or_sge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {562; RV32I-LABEL: or_sge_eq:563; RV32I: # %bb.0:564; RV32I-NEXT: bge a0, a1, .LBB21_3565; RV32I-NEXT: # %bb.1:566; RV32I-NEXT: beq a2, a3, .LBB21_3567; RV32I-NEXT: # %bb.2:568; RV32I-NEXT: tail bar569; RV32I-NEXT: .LBB21_3:570; RV32I-NEXT: ret571;572; RV64I-LABEL: or_sge_eq:573; RV64I: # %bb.0:574; RV64I-NEXT: bge a0, a1, .LBB21_3575; RV64I-NEXT: # %bb.1:576; RV64I-NEXT: beq a2, a3, .LBB21_3577; RV64I-NEXT: # %bb.2:578; RV64I-NEXT: tail bar579; RV64I-NEXT: .LBB21_3:580; RV64I-NEXT: ret581 %5 = icmp sge i32 %0, %1582 %6 = icmp eq i32 %2, %3583 %7 = or i1 %5, %6584 br i1 %7, label %9, label %8585 5868: ; preds = %4587 tail call void @bar()588 br label %9589 5909: ; preds = %8, %4591 ret void592}593 594define void @or_sle_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {595; RV32I-LABEL: or_sle_eq:596; RV32I: # %bb.0:597; RV32I-NEXT: bge a1, a0, .LBB22_3598; RV32I-NEXT: # %bb.1:599; RV32I-NEXT: beq a2, a3, .LBB22_3600; RV32I-NEXT: # %bb.2:601; RV32I-NEXT: tail bar602; RV32I-NEXT: .LBB22_3:603; RV32I-NEXT: ret604;605; RV64I-LABEL: or_sle_eq:606; RV64I: # %bb.0:607; RV64I-NEXT: bge a1, a0, .LBB22_3608; RV64I-NEXT: # %bb.1:609; RV64I-NEXT: beq a2, a3, .LBB22_3610; RV64I-NEXT: # %bb.2:611; RV64I-NEXT: tail bar612; RV64I-NEXT: .LBB22_3:613; RV64I-NEXT: ret614 %5 = icmp sle i32 %0, %1615 %6 = icmp eq i32 %2, %3616 %7 = or i1 %5, %6617 br i1 %7, label %9, label %8618 6198: ; preds = %4620 tail call void @bar()621 br label %9622 6239: ; preds = %8, %4624 ret void625}626 627define void @or_uge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {628; RV32I-LABEL: or_uge_eq:629; RV32I: # %bb.0:630; RV32I-NEXT: bgeu a0, a1, .LBB23_3631; RV32I-NEXT: # %bb.1:632; RV32I-NEXT: beq a2, a3, .LBB23_3633; RV32I-NEXT: # %bb.2:634; RV32I-NEXT: tail bar635; RV32I-NEXT: .LBB23_3:636; RV32I-NEXT: ret637;638; RV64I-LABEL: or_uge_eq:639; RV64I: # %bb.0:640; RV64I-NEXT: bgeu a0, a1, .LBB23_3641; RV64I-NEXT: # %bb.1:642; RV64I-NEXT: beq a2, a3, .LBB23_3643; RV64I-NEXT: # %bb.2:644; RV64I-NEXT: tail bar645; RV64I-NEXT: .LBB23_3:646; RV64I-NEXT: ret647 %5 = icmp uge i32 %0, %1648 %6 = icmp eq i32 %2, %3649 %7 = or i1 %5, %6650 br i1 %7, label %9, label %8651 6528: ; preds = %4653 tail call void @bar()654 br label %9655 6569: ; preds = %8, %4657 ret void658}659 660define void @or_ule_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {661; RV32I-LABEL: or_ule_eq:662; RV32I: # %bb.0:663; RV32I-NEXT: bgeu a1, a0, .LBB24_3664; RV32I-NEXT: # %bb.1:665; RV32I-NEXT: beq a2, a3, .LBB24_3666; RV32I-NEXT: # %bb.2:667; RV32I-NEXT: tail bar668; RV32I-NEXT: .LBB24_3:669; RV32I-NEXT: ret670;671; RV64I-LABEL: or_ule_eq:672; RV64I: # %bb.0:673; RV64I-NEXT: bgeu a1, a0, .LBB24_3674; RV64I-NEXT: # %bb.1:675; RV64I-NEXT: beq a2, a3, .LBB24_3676; RV64I-NEXT: # %bb.2:677; RV64I-NEXT: tail bar678; RV64I-NEXT: .LBB24_3:679; RV64I-NEXT: ret680 %5 = icmp ule i32 %0, %1681 %6 = icmp eq i32 %2, %3682 %7 = or i1 %5, %6683 br i1 %7, label %9, label %8684 6858: ; preds = %4686 tail call void @bar()687 br label %9688 6899: ; preds = %8, %4690 ret void691}692 693define void @or_sge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {694; RV32I-LABEL: or_sge_ne:695; RV32I: # %bb.0:696; RV32I-NEXT: bge a0, a1, .LBB25_3697; RV32I-NEXT: # %bb.1:698; RV32I-NEXT: bne a2, a3, .LBB25_3699; RV32I-NEXT: # %bb.2:700; RV32I-NEXT: tail bar701; RV32I-NEXT: .LBB25_3:702; RV32I-NEXT: ret703;704; RV64I-LABEL: or_sge_ne:705; RV64I: # %bb.0:706; RV64I-NEXT: bge a0, a1, .LBB25_3707; RV64I-NEXT: # %bb.1:708; RV64I-NEXT: bne a2, a3, .LBB25_3709; RV64I-NEXT: # %bb.2:710; RV64I-NEXT: tail bar711; RV64I-NEXT: .LBB25_3:712; RV64I-NEXT: ret713 %5 = icmp sge i32 %0, %1714 %6 = icmp ne i32 %2, %3715 %7 = or i1 %5, %6716 br i1 %7, label %9, label %8717 7188: ; preds = %4719 tail call void @bar()720 br label %9721 7229: ; preds = %8, %4723 ret void724}725 726define void @or_sle_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {727; RV32I-LABEL: or_sle_ne:728; RV32I: # %bb.0:729; RV32I-NEXT: bge a1, a0, .LBB26_3730; RV32I-NEXT: # %bb.1:731; RV32I-NEXT: bne a2, a3, .LBB26_3732; RV32I-NEXT: # %bb.2:733; RV32I-NEXT: tail bar734; RV32I-NEXT: .LBB26_3:735; RV32I-NEXT: ret736;737; RV64I-LABEL: or_sle_ne:738; RV64I: # %bb.0:739; RV64I-NEXT: bge a1, a0, .LBB26_3740; RV64I-NEXT: # %bb.1:741; RV64I-NEXT: bne a2, a3, .LBB26_3742; RV64I-NEXT: # %bb.2:743; RV64I-NEXT: tail bar744; RV64I-NEXT: .LBB26_3:745; RV64I-NEXT: ret746 %5 = icmp sle i32 %0, %1747 %6 = icmp ne i32 %2, %3748 %7 = or i1 %5, %6749 br i1 %7, label %9, label %8750 7518: ; preds = %4752 tail call void @bar()753 br label %9754 7559: ; preds = %8, %4756 ret void757}758 759define void @or_uge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {760; RV32I-LABEL: or_uge_ne:761; RV32I: # %bb.0:762; RV32I-NEXT: bgeu a0, a1, .LBB27_3763; RV32I-NEXT: # %bb.1:764; RV32I-NEXT: bne a2, a3, .LBB27_3765; RV32I-NEXT: # %bb.2:766; RV32I-NEXT: tail bar767; RV32I-NEXT: .LBB27_3:768; RV32I-NEXT: ret769;770; RV64I-LABEL: or_uge_ne:771; RV64I: # %bb.0:772; RV64I-NEXT: bgeu a0, a1, .LBB27_3773; RV64I-NEXT: # %bb.1:774; RV64I-NEXT: bne a2, a3, .LBB27_3775; RV64I-NEXT: # %bb.2:776; RV64I-NEXT: tail bar777; RV64I-NEXT: .LBB27_3:778; RV64I-NEXT: ret779 %5 = icmp uge i32 %0, %1780 %6 = icmp ne i32 %2, %3781 %7 = or i1 %5, %6782 br i1 %7, label %9, label %8783 7848: ; preds = %4785 tail call void @bar()786 br label %9787 7889: ; preds = %8, %4789 ret void790}791 792define void @or_ule_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {793; RV32I-LABEL: or_ule_ne:794; RV32I: # %bb.0:795; RV32I-NEXT: bgeu a1, a0, .LBB28_3796; RV32I-NEXT: # %bb.1:797; RV32I-NEXT: bne a2, a3, .LBB28_3798; RV32I-NEXT: # %bb.2:799; RV32I-NEXT: tail bar800; RV32I-NEXT: .LBB28_3:801; RV32I-NEXT: ret802;803; RV64I-LABEL: or_ule_ne:804; RV64I: # %bb.0:805; RV64I-NEXT: bgeu a1, a0, .LBB28_3806; RV64I-NEXT: # %bb.1:807; RV64I-NEXT: bne a2, a3, .LBB28_3808; RV64I-NEXT: # %bb.2:809; RV64I-NEXT: tail bar810; RV64I-NEXT: .LBB28_3:811; RV64I-NEXT: ret812 %5 = icmp ule i32 %0, %1813 %6 = icmp ne i32 %2, %3814 %7 = or i1 %5, %6815 br i1 %7, label %9, label %8816 8178: ; preds = %4818 tail call void @bar()819 br label %9820 8219: ; preds = %8, %4822 ret void823}824 825define void @and_eq_sge(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {826; RV32I-LABEL: and_eq_sge:827; RV32I: # %bb.0:828; RV32I-NEXT: bne a0, a1, .LBB29_3829; RV32I-NEXT: # %bb.1:830; RV32I-NEXT: blt a2, a3, .LBB29_3831; RV32I-NEXT: # %bb.2:832; RV32I-NEXT: ret833; RV32I-NEXT: .LBB29_3:834; RV32I-NEXT: tail bar835;836; RV64I-LABEL: and_eq_sge:837; RV64I: # %bb.0:838; RV64I-NEXT: bne a0, a1, .LBB29_3839; RV64I-NEXT: # %bb.1:840; RV64I-NEXT: blt a2, a3, .LBB29_3841; RV64I-NEXT: # %bb.2:842; RV64I-NEXT: ret843; RV64I-NEXT: .LBB29_3:844; RV64I-NEXT: tail bar845 %5 = icmp eq i32 %0, %1846 %6 = icmp sge i32 %2, %3847 %7 = and i1 %5, %6848 br i1 %7, label %9, label %8849 8508: ; preds = %4851 tail call void @bar()852 br label %9853 8549: ; preds = %8, %4855 ret void856}857 858define void @and_eq_sle(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {859; RV32I-LABEL: and_eq_sle:860; RV32I: # %bb.0:861; RV32I-NEXT: bne a0, a1, .LBB30_3862; RV32I-NEXT: # %bb.1:863; RV32I-NEXT: blt a3, a2, .LBB30_3864; RV32I-NEXT: # %bb.2:865; RV32I-NEXT: ret866; RV32I-NEXT: .LBB30_3:867; RV32I-NEXT: tail bar868;869; RV64I-LABEL: and_eq_sle:870; RV64I: # %bb.0:871; RV64I-NEXT: bne a0, a1, .LBB30_3872; RV64I-NEXT: # %bb.1:873; RV64I-NEXT: blt a3, a2, .LBB30_3874; RV64I-NEXT: # %bb.2:875; RV64I-NEXT: ret876; RV64I-NEXT: .LBB30_3:877; RV64I-NEXT: tail bar878 %5 = icmp eq i32 %0, %1879 %6 = icmp sle i32 %2, %3880 %7 = and i1 %5, %6881 br i1 %7, label %9, label %8882 8838: ; preds = %4884 tail call void @bar()885 br label %9886 8879: ; preds = %8, %4888 ret void889}890 891define void @and_eq_uge(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {892; RV32I-LABEL: and_eq_uge:893; RV32I: # %bb.0:894; RV32I-NEXT: bne a0, a1, .LBB31_3895; RV32I-NEXT: # %bb.1:896; RV32I-NEXT: bltu a2, a3, .LBB31_3897; RV32I-NEXT: # %bb.2:898; RV32I-NEXT: ret899; RV32I-NEXT: .LBB31_3:900; RV32I-NEXT: tail bar901;902; RV64I-LABEL: and_eq_uge:903; RV64I: # %bb.0:904; RV64I-NEXT: bne a0, a1, .LBB31_3905; RV64I-NEXT: # %bb.1:906; RV64I-NEXT: bltu a2, a3, .LBB31_3907; RV64I-NEXT: # %bb.2:908; RV64I-NEXT: ret909; RV64I-NEXT: .LBB31_3:910; RV64I-NEXT: tail bar911 %5 = icmp eq i32 %0, %1912 %6 = icmp uge i32 %2, %3913 %7 = and i1 %5, %6914 br i1 %7, label %9, label %8915 9168: ; preds = %4917 tail call void @bar()918 br label %9919 9209: ; preds = %8, %4921 ret void922}923 924define void @and_eq_ule(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {925; RV32I-LABEL: and_eq_ule:926; RV32I: # %bb.0:927; RV32I-NEXT: bne a0, a1, .LBB32_3928; RV32I-NEXT: # %bb.1:929; RV32I-NEXT: bltu a3, a2, .LBB32_3930; RV32I-NEXT: # %bb.2:931; RV32I-NEXT: ret932; RV32I-NEXT: .LBB32_3:933; RV32I-NEXT: tail bar934;935; RV64I-LABEL: and_eq_ule:936; RV64I: # %bb.0:937; RV64I-NEXT: bne a0, a1, .LBB32_3938; RV64I-NEXT: # %bb.1:939; RV64I-NEXT: bltu a3, a2, .LBB32_3940; RV64I-NEXT: # %bb.2:941; RV64I-NEXT: ret942; RV64I-NEXT: .LBB32_3:943; RV64I-NEXT: tail bar944 %5 = icmp eq i32 %0, %1945 %6 = icmp ule i32 %2, %3946 %7 = and i1 %5, %6947 br i1 %7, label %9, label %8948 9498: ; preds = %4950 tail call void @bar()951 br label %9952 9539: ; preds = %8, %4954 ret void955}956 957define void @and_ne_sge(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {958; RV32I-LABEL: and_ne_sge:959; RV32I: # %bb.0:960; RV32I-NEXT: beq a0, a1, .LBB33_3961; RV32I-NEXT: # %bb.1:962; RV32I-NEXT: blt a2, a3, .LBB33_3963; RV32I-NEXT: # %bb.2:964; RV32I-NEXT: ret965; RV32I-NEXT: .LBB33_3:966; RV32I-NEXT: tail bar967;968; RV64I-LABEL: and_ne_sge:969; RV64I: # %bb.0:970; RV64I-NEXT: beq a0, a1, .LBB33_3971; RV64I-NEXT: # %bb.1:972; RV64I-NEXT: blt a2, a3, .LBB33_3973; RV64I-NEXT: # %bb.2:974; RV64I-NEXT: ret975; RV64I-NEXT: .LBB33_3:976; RV64I-NEXT: tail bar977 %5 = icmp ne i32 %0, %1978 %6 = icmp sge i32 %2, %3979 %7 = and i1 %5, %6980 br i1 %7, label %9, label %8981 9828: ; preds = %4983 tail call void @bar()984 br label %9985 9869: ; preds = %8, %4987 ret void988}989 990define void @and_ne_sle(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {991; RV32I-LABEL: and_ne_sle:992; RV32I: # %bb.0:993; RV32I-NEXT: beq a0, a1, .LBB34_3994; RV32I-NEXT: # %bb.1:995; RV32I-NEXT: blt a3, a2, .LBB34_3996; RV32I-NEXT: # %bb.2:997; RV32I-NEXT: ret998; RV32I-NEXT: .LBB34_3:999; RV32I-NEXT: tail bar1000;1001; RV64I-LABEL: and_ne_sle:1002; RV64I: # %bb.0:1003; RV64I-NEXT: beq a0, a1, .LBB34_31004; RV64I-NEXT: # %bb.1:1005; RV64I-NEXT: blt a3, a2, .LBB34_31006; RV64I-NEXT: # %bb.2:1007; RV64I-NEXT: ret1008; RV64I-NEXT: .LBB34_3:1009; RV64I-NEXT: tail bar1010 %5 = icmp ne i32 %0, %11011 %6 = icmp sle i32 %2, %31012 %7 = and i1 %5, %61013 br i1 %7, label %9, label %81014 10158: ; preds = %41016 tail call void @bar()1017 br label %91018 10199: ; preds = %8, %41020 ret void1021}1022 1023define void @and_ne_uge(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {1024; RV32I-LABEL: and_ne_uge:1025; RV32I: # %bb.0:1026; RV32I-NEXT: beq a0, a1, .LBB35_31027; RV32I-NEXT: # %bb.1:1028; RV32I-NEXT: bltu a2, a3, .LBB35_31029; RV32I-NEXT: # %bb.2:1030; RV32I-NEXT: ret1031; RV32I-NEXT: .LBB35_3:1032; RV32I-NEXT: tail bar1033;1034; RV64I-LABEL: and_ne_uge:1035; RV64I: # %bb.0:1036; RV64I-NEXT: beq a0, a1, .LBB35_31037; RV64I-NEXT: # %bb.1:1038; RV64I-NEXT: bltu a2, a3, .LBB35_31039; RV64I-NEXT: # %bb.2:1040; RV64I-NEXT: ret1041; RV64I-NEXT: .LBB35_3:1042; RV64I-NEXT: tail bar1043 %5 = icmp ne i32 %0, %11044 %6 = icmp uge i32 %2, %31045 %7 = and i1 %5, %61046 br i1 %7, label %9, label %81047 10488: ; preds = %41049 tail call void @bar()1050 br label %91051 10529: ; preds = %8, %41053 ret void1054}1055 1056define void @and_ne_ule(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {1057; RV32I-LABEL: and_ne_ule:1058; RV32I: # %bb.0:1059; RV32I-NEXT: beq a0, a1, .LBB36_31060; RV32I-NEXT: # %bb.1:1061; RV32I-NEXT: bltu a3, a2, .LBB36_31062; RV32I-NEXT: # %bb.2:1063; RV32I-NEXT: ret1064; RV32I-NEXT: .LBB36_3:1065; RV32I-NEXT: tail bar1066;1067; RV64I-LABEL: and_ne_ule:1068; RV64I: # %bb.0:1069; RV64I-NEXT: beq a0, a1, .LBB36_31070; RV64I-NEXT: # %bb.1:1071; RV64I-NEXT: bltu a3, a2, .LBB36_31072; RV64I-NEXT: # %bb.2:1073; RV64I-NEXT: ret1074; RV64I-NEXT: .LBB36_3:1075; RV64I-NEXT: tail bar1076 %5 = icmp ne i32 %0, %11077 %6 = icmp ule i32 %2, %31078 %7 = and i1 %5, %61079 br i1 %7, label %9, label %81080 10818: ; preds = %41082 tail call void @bar()1083 br label %91084 10859: ; preds = %8, %41086 ret void1087}1088 1089define void @and_sge_gt0(i32 signext %0, i32 signext %1, i32 signext %2) {1090; RV32I-LABEL: and_sge_gt0:1091; RV32I: # %bb.0:1092; RV32I-NEXT: blt a0, a1, .LBB37_31093; RV32I-NEXT: # %bb.1:1094; RV32I-NEXT: blez a2, .LBB37_31095; RV32I-NEXT: # %bb.2:1096; RV32I-NEXT: ret1097; RV32I-NEXT: .LBB37_3:1098; RV32I-NEXT: tail bar1099;1100; RV64I-LABEL: and_sge_gt0:1101; RV64I: # %bb.0:1102; RV64I-NEXT: blt a0, a1, .LBB37_31103; RV64I-NEXT: # %bb.1:1104; RV64I-NEXT: blez a2, .LBB37_31105; RV64I-NEXT: # %bb.2:1106; RV64I-NEXT: ret1107; RV64I-NEXT: .LBB37_3:1108; RV64I-NEXT: tail bar1109 %4 = icmp sge i32 %0, %11110 %5 = icmp sgt i32 %2, 01111 %6 = and i1 %4, %51112 br i1 %6, label %8, label %71113 11147: ; preds = %41115 tail call void @bar()1116 br label %81117 11188: ; preds = %8, %41119 ret void1120}1121 1122define void @and_sle_lt1(i32 signext %0, i32 signext %1, i32 signext %2) {1123; RV32I-LABEL: and_sle_lt1:1124; RV32I: # %bb.0:1125; RV32I-NEXT: blt a1, a0, .LBB38_31126; RV32I-NEXT: # %bb.1:1127; RV32I-NEXT: bgtz a2, .LBB38_31128; RV32I-NEXT: # %bb.2:1129; RV32I-NEXT: ret1130; RV32I-NEXT: .LBB38_3:1131; RV32I-NEXT: tail bar1132;1133; RV64I-LABEL: and_sle_lt1:1134; RV64I: # %bb.0:1135; RV64I-NEXT: blt a1, a0, .LBB38_31136; RV64I-NEXT: # %bb.1:1137; RV64I-NEXT: bgtz a2, .LBB38_31138; RV64I-NEXT: # %bb.2:1139; RV64I-NEXT: ret1140; RV64I-NEXT: .LBB38_3:1141; RV64I-NEXT: tail bar1142 %4 = icmp sle i32 %0, %11143 %5 = icmp slt i32 %2, 11144 %6 = and i1 %4, %51145 br i1 %6, label %8, label %71146 11477: ; preds = %41148 tail call void @bar()1149 br label %81150 11518: ; preds = %8, %41152 ret void1153}1154 1155define void @or_uge_gt0(i32 signext %0, i32 signext %1, i32 signext %2) {1156; RV32I-LABEL: or_uge_gt0:1157; RV32I: # %bb.0:1158; RV32I-NEXT: bgeu a0, a1, .LBB39_31159; RV32I-NEXT: # %bb.1:1160; RV32I-NEXT: bgtz a2, .LBB39_31161; RV32I-NEXT: # %bb.2:1162; RV32I-NEXT: tail bar1163; RV32I-NEXT: .LBB39_3:1164; RV32I-NEXT: ret1165;1166; RV64I-LABEL: or_uge_gt0:1167; RV64I: # %bb.0:1168; RV64I-NEXT: bgeu a0, a1, .LBB39_31169; RV64I-NEXT: # %bb.1:1170; RV64I-NEXT: bgtz a2, .LBB39_31171; RV64I-NEXT: # %bb.2:1172; RV64I-NEXT: tail bar1173; RV64I-NEXT: .LBB39_3:1174; RV64I-NEXT: ret1175 %4 = icmp uge i32 %0, %11176 %5 = icmp sgt i32 %2, 01177 %6 = or i1 %4, %51178 br i1 %6, label %8, label %71179 11807: ; preds = %41181 tail call void @bar()1182 br label %81183 11848: ; preds = %8, %41185 ret void1186}1187 1188define void @or_ule_lt1(i32 signext %0, i32 signext %1, i32 signext %2) {1189; RV32I-LABEL: or_ule_lt1:1190; RV32I: # %bb.0:1191; RV32I-NEXT: bgeu a1, a0, .LBB40_31192; RV32I-NEXT: # %bb.1:1193; RV32I-NEXT: blez a2, .LBB40_31194; RV32I-NEXT: # %bb.2:1195; RV32I-NEXT: tail bar1196; RV32I-NEXT: .LBB40_3:1197; RV32I-NEXT: ret1198;1199; RV64I-LABEL: or_ule_lt1:1200; RV64I: # %bb.0:1201; RV64I-NEXT: bgeu a1, a0, .LBB40_31202; RV64I-NEXT: # %bb.1:1203; RV64I-NEXT: blez a2, .LBB40_31204; RV64I-NEXT: # %bb.2:1205; RV64I-NEXT: tail bar1206; RV64I-NEXT: .LBB40_3:1207; RV64I-NEXT: ret1208 %4 = icmp ule i32 %0, %11209 %5 = icmp slt i32 %2, 11210 %6 = or i1 %4, %51211 br i1 %6, label %8, label %71212 12137: ; preds = %41214 tail call void @bar()1215 br label %81216 12178: ; preds = %8, %41218 ret void1219}1220