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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV32I4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefixes=RV64,RV64I6; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \7; RUN: | FileCheck %s -check-prefixes=RV64,RV64ZBB8 9define i8 @sext_i1_to_i8(i1 %a) nounwind {10; RV32I-LABEL: sext_i1_to_i8:11; RV32I: # %bb.0:12; RV32I-NEXT: slli a0, a0, 3113; RV32I-NEXT: srai a0, a0, 3114; RV32I-NEXT: ret15;16; RV64-LABEL: sext_i1_to_i8:17; RV64: # %bb.0:18; RV64-NEXT: slli a0, a0, 6319; RV64-NEXT: srai a0, a0, 6320; RV64-NEXT: ret21 %1 = sext i1 %a to i822 ret i8 %123}24 25define i16 @sext_i1_to_i16(i1 %a) nounwind {26; RV32I-LABEL: sext_i1_to_i16:27; RV32I: # %bb.0:28; RV32I-NEXT: slli a0, a0, 3129; RV32I-NEXT: srai a0, a0, 3130; RV32I-NEXT: ret31;32; RV64-LABEL: sext_i1_to_i16:33; RV64: # %bb.0:34; RV64-NEXT: slli a0, a0, 6335; RV64-NEXT: srai a0, a0, 6336; RV64-NEXT: ret37 %1 = sext i1 %a to i1638 ret i16 %139}40 41define i32 @sext_i1_to_i32(i1 %a) nounwind {42; RV32I-LABEL: sext_i1_to_i32:43; RV32I: # %bb.0:44; RV32I-NEXT: slli a0, a0, 3145; RV32I-NEXT: srai a0, a0, 3146; RV32I-NEXT: ret47;48; RV64-LABEL: sext_i1_to_i32:49; RV64: # %bb.0:50; RV64-NEXT: slli a0, a0, 6351; RV64-NEXT: srai a0, a0, 6352; RV64-NEXT: ret53 %1 = sext i1 %a to i3254 ret i32 %155}56 57define i64 @sext_i1_to_i64(i1 %a) nounwind {58; RV32I-LABEL: sext_i1_to_i64:59; RV32I: # %bb.0:60; RV32I-NEXT: slli a0, a0, 3161; RV32I-NEXT: srai a0, a0, 3162; RV32I-NEXT: mv a1, a063; RV32I-NEXT: ret64;65; RV64-LABEL: sext_i1_to_i64:66; RV64: # %bb.0:67; RV64-NEXT: slli a0, a0, 6368; RV64-NEXT: srai a0, a0, 6369; RV64-NEXT: ret70 %1 = sext i1 %a to i6471 ret i64 %172}73 74define i16 @sext_i8_to_i16(i8 %a) nounwind {75; RV32I-LABEL: sext_i8_to_i16:76; RV32I: # %bb.0:77; RV32I-NEXT: slli a0, a0, 2478; RV32I-NEXT: srai a0, a0, 2479; RV32I-NEXT: ret80;81; RV64I-LABEL: sext_i8_to_i16:82; RV64I: # %bb.0:83; RV64I-NEXT: slli a0, a0, 5684; RV64I-NEXT: srai a0, a0, 5685; RV64I-NEXT: ret86;87; RV64ZBB-LABEL: sext_i8_to_i16:88; RV64ZBB: # %bb.0:89; RV64ZBB-NEXT: sext.b a0, a090; RV64ZBB-NEXT: ret91 %1 = sext i8 %a to i1692 ret i16 %193}94 95define i32 @sext_i8_to_i32(i8 %a) nounwind {96; RV32I-LABEL: sext_i8_to_i32:97; RV32I: # %bb.0:98; RV32I-NEXT: slli a0, a0, 2499; RV32I-NEXT: srai a0, a0, 24100; RV32I-NEXT: ret101;102; RV64I-LABEL: sext_i8_to_i32:103; RV64I: # %bb.0:104; RV64I-NEXT: slli a0, a0, 56105; RV64I-NEXT: srai a0, a0, 56106; RV64I-NEXT: ret107;108; RV64ZBB-LABEL: sext_i8_to_i32:109; RV64ZBB: # %bb.0:110; RV64ZBB-NEXT: sext.b a0, a0111; RV64ZBB-NEXT: ret112 %1 = sext i8 %a to i32113 ret i32 %1114}115 116define i64 @sext_i8_to_i64(i8 %a) nounwind {117; RV32I-LABEL: sext_i8_to_i64:118; RV32I: # %bb.0:119; RV32I-NEXT: slli a1, a0, 24120; RV32I-NEXT: srai a0, a1, 24121; RV32I-NEXT: srai a1, a1, 31122; RV32I-NEXT: ret123;124; RV64I-LABEL: sext_i8_to_i64:125; RV64I: # %bb.0:126; RV64I-NEXT: slli a0, a0, 56127; RV64I-NEXT: srai a0, a0, 56128; RV64I-NEXT: ret129;130; RV64ZBB-LABEL: sext_i8_to_i64:131; RV64ZBB: # %bb.0:132; RV64ZBB-NEXT: sext.b a0, a0133; RV64ZBB-NEXT: ret134 %1 = sext i8 %a to i64135 ret i64 %1136}137 138define i32 @sext_i16_to_i32(i16 %a) nounwind {139; RV32I-LABEL: sext_i16_to_i32:140; RV32I: # %bb.0:141; RV32I-NEXT: slli a0, a0, 16142; RV32I-NEXT: srai a0, a0, 16143; RV32I-NEXT: ret144;145; RV64I-LABEL: sext_i16_to_i32:146; RV64I: # %bb.0:147; RV64I-NEXT: slli a0, a0, 48148; RV64I-NEXT: srai a0, a0, 48149; RV64I-NEXT: ret150;151; RV64ZBB-LABEL: sext_i16_to_i32:152; RV64ZBB: # %bb.0:153; RV64ZBB-NEXT: sext.h a0, a0154; RV64ZBB-NEXT: ret155 %1 = sext i16 %a to i32156 ret i32 %1157}158 159define i64 @sext_i16_to_i64(i16 %a) nounwind {160; RV32I-LABEL: sext_i16_to_i64:161; RV32I: # %bb.0:162; RV32I-NEXT: slli a1, a0, 16163; RV32I-NEXT: srai a0, a1, 16164; RV32I-NEXT: srai a1, a1, 31165; RV32I-NEXT: ret166;167; RV64I-LABEL: sext_i16_to_i64:168; RV64I: # %bb.0:169; RV64I-NEXT: slli a0, a0, 48170; RV64I-NEXT: srai a0, a0, 48171; RV64I-NEXT: ret172;173; RV64ZBB-LABEL: sext_i16_to_i64:174; RV64ZBB: # %bb.0:175; RV64ZBB-NEXT: sext.h a0, a0176; RV64ZBB-NEXT: ret177 %1 = sext i16 %a to i64178 ret i64 %1179}180 181define i64 @sext_i32_to_i64(i32 %a) nounwind {182; RV32I-LABEL: sext_i32_to_i64:183; RV32I: # %bb.0:184; RV32I-NEXT: srai a1, a0, 31185; RV32I-NEXT: ret186;187; RV64-LABEL: sext_i32_to_i64:188; RV64: # %bb.0:189; RV64-NEXT: sext.w a0, a0190; RV64-NEXT: ret191 %1 = sext i32 %a to i64192 ret i64 %1193}194 195define i8 @zext_i1_to_i8(i1 %a) nounwind {196; RV32I-LABEL: zext_i1_to_i8:197; RV32I: # %bb.0:198; RV32I-NEXT: andi a0, a0, 1199; RV32I-NEXT: ret200;201; RV64-LABEL: zext_i1_to_i8:202; RV64: # %bb.0:203; RV64-NEXT: andi a0, a0, 1204; RV64-NEXT: ret205 %1 = zext i1 %a to i8206 ret i8 %1207}208 209define i16 @zext_i1_to_i16(i1 %a) nounwind {210; RV32I-LABEL: zext_i1_to_i16:211; RV32I: # %bb.0:212; RV32I-NEXT: andi a0, a0, 1213; RV32I-NEXT: ret214;215; RV64-LABEL: zext_i1_to_i16:216; RV64: # %bb.0:217; RV64-NEXT: andi a0, a0, 1218; RV64-NEXT: ret219 %1 = zext i1 %a to i16220 ret i16 %1221}222 223define i32 @zext_i1_to_i32(i1 %a) nounwind {224; RV32I-LABEL: zext_i1_to_i32:225; RV32I: # %bb.0:226; RV32I-NEXT: andi a0, a0, 1227; RV32I-NEXT: ret228;229; RV64-LABEL: zext_i1_to_i32:230; RV64: # %bb.0:231; RV64-NEXT: andi a0, a0, 1232; RV64-NEXT: ret233 %1 = zext i1 %a to i32234 ret i32 %1235}236 237define i64 @zext_i1_to_i64(i1 %a) nounwind {238; RV32I-LABEL: zext_i1_to_i64:239; RV32I: # %bb.0:240; RV32I-NEXT: andi a0, a0, 1241; RV32I-NEXT: li a1, 0242; RV32I-NEXT: ret243;244; RV64-LABEL: zext_i1_to_i64:245; RV64: # %bb.0:246; RV64-NEXT: andi a0, a0, 1247; RV64-NEXT: ret248 %1 = zext i1 %a to i64249 ret i64 %1250}251 252define i16 @zext_i8_to_i16(i8 %a) nounwind {253; RV32I-LABEL: zext_i8_to_i16:254; RV32I: # %bb.0:255; RV32I-NEXT: zext.b a0, a0256; RV32I-NEXT: ret257;258; RV64-LABEL: zext_i8_to_i16:259; RV64: # %bb.0:260; RV64-NEXT: zext.b a0, a0261; RV64-NEXT: ret262 %1 = zext i8 %a to i16263 ret i16 %1264}265 266define i32 @zext_i8_to_i32(i8 %a) nounwind {267; RV32I-LABEL: zext_i8_to_i32:268; RV32I: # %bb.0:269; RV32I-NEXT: zext.b a0, a0270; RV32I-NEXT: ret271;272; RV64-LABEL: zext_i8_to_i32:273; RV64: # %bb.0:274; RV64-NEXT: zext.b a0, a0275; RV64-NEXT: ret276 %1 = zext i8 %a to i32277 ret i32 %1278}279 280define i64 @zext_i8_to_i64(i8 %a) nounwind {281; RV32I-LABEL: zext_i8_to_i64:282; RV32I: # %bb.0:283; RV32I-NEXT: zext.b a0, a0284; RV32I-NEXT: li a1, 0285; RV32I-NEXT: ret286;287; RV64-LABEL: zext_i8_to_i64:288; RV64: # %bb.0:289; RV64-NEXT: zext.b a0, a0290; RV64-NEXT: ret291 %1 = zext i8 %a to i64292 ret i64 %1293}294 295define i32 @zext_i16_to_i32(i16 %a) nounwind {296; RV32I-LABEL: zext_i16_to_i32:297; RV32I: # %bb.0:298; RV32I-NEXT: slli a0, a0, 16299; RV32I-NEXT: srli a0, a0, 16300; RV32I-NEXT: ret301;302; RV64I-LABEL: zext_i16_to_i32:303; RV64I: # %bb.0:304; RV64I-NEXT: slli a0, a0, 48305; RV64I-NEXT: srli a0, a0, 48306; RV64I-NEXT: ret307;308; RV64ZBB-LABEL: zext_i16_to_i32:309; RV64ZBB: # %bb.0:310; RV64ZBB-NEXT: zext.h a0, a0311; RV64ZBB-NEXT: ret312 %1 = zext i16 %a to i32313 ret i32 %1314}315 316define i64 @zext_i16_to_i64(i16 %a) nounwind {317; RV32I-LABEL: zext_i16_to_i64:318; RV32I: # %bb.0:319; RV32I-NEXT: slli a0, a0, 16320; RV32I-NEXT: srli a0, a0, 16321; RV32I-NEXT: li a1, 0322; RV32I-NEXT: ret323;324; RV64I-LABEL: zext_i16_to_i64:325; RV64I: # %bb.0:326; RV64I-NEXT: slli a0, a0, 48327; RV64I-NEXT: srli a0, a0, 48328; RV64I-NEXT: ret329;330; RV64ZBB-LABEL: zext_i16_to_i64:331; RV64ZBB: # %bb.0:332; RV64ZBB-NEXT: zext.h a0, a0333; RV64ZBB-NEXT: ret334 %1 = zext i16 %a to i64335 ret i64 %1336}337 338define i64 @zext_i32_to_i64(i32 %a) nounwind {339; RV32I-LABEL: zext_i32_to_i64:340; RV32I: # %bb.0:341; RV32I-NEXT: li a1, 0342; RV32I-NEXT: ret343;344; RV64-LABEL: zext_i32_to_i64:345; RV64: # %bb.0:346; RV64-NEXT: slli a0, a0, 32347; RV64-NEXT: srli a0, a0, 32348; RV64-NEXT: ret349 %1 = zext i32 %a to i64350 ret i64 %1351}352 353define i8 @zext_nneg_i1_to_i8(i1 %a) nounwind {354; RV32I-LABEL: zext_nneg_i1_to_i8:355; RV32I: # %bb.0:356; RV32I-NEXT: andi a0, a0, 1357; RV32I-NEXT: ret358;359; RV64-LABEL: zext_nneg_i1_to_i8:360; RV64: # %bb.0:361; RV64-NEXT: andi a0, a0, 1362; RV64-NEXT: ret363 %1 = zext nneg i1 %a to i8364 ret i8 %1365}366 367define i16 @zext_nneg_i1_to_i16(i1 %a) nounwind {368; RV32I-LABEL: zext_nneg_i1_to_i16:369; RV32I: # %bb.0:370; RV32I-NEXT: andi a0, a0, 1371; RV32I-NEXT: ret372;373; RV64-LABEL: zext_nneg_i1_to_i16:374; RV64: # %bb.0:375; RV64-NEXT: andi a0, a0, 1376; RV64-NEXT: ret377 %1 = zext nneg i1 %a to i16378 ret i16 %1379}380 381define i32 @zext_nneg_i1_to_i32(i1 %a) nounwind {382; RV32I-LABEL: zext_nneg_i1_to_i32:383; RV32I: # %bb.0:384; RV32I-NEXT: andi a0, a0, 1385; RV32I-NEXT: ret386;387; RV64-LABEL: zext_nneg_i1_to_i32:388; RV64: # %bb.0:389; RV64-NEXT: andi a0, a0, 1390; RV64-NEXT: ret391 %1 = zext nneg i1 %a to i32392 ret i32 %1393}394 395define i64 @zext_nneg_i1_to_i64(i1 %a) nounwind {396; RV32I-LABEL: zext_nneg_i1_to_i64:397; RV32I: # %bb.0:398; RV32I-NEXT: andi a0, a0, 1399; RV32I-NEXT: li a1, 0400; RV32I-NEXT: ret401;402; RV64-LABEL: zext_nneg_i1_to_i64:403; RV64: # %bb.0:404; RV64-NEXT: andi a0, a0, 1405; RV64-NEXT: ret406 %1 = zext nneg i1 %a to i64407 ret i64 %1408}409 410define i16 @zext_nneg_i8_to_i16(i8 %a) nounwind {411; RV32I-LABEL: zext_nneg_i8_to_i16:412; RV32I: # %bb.0:413; RV32I-NEXT: zext.b a0, a0414; RV32I-NEXT: ret415;416; RV64-LABEL: zext_nneg_i8_to_i16:417; RV64: # %bb.0:418; RV64-NEXT: zext.b a0, a0419; RV64-NEXT: ret420 %1 = zext nneg i8 %a to i16421 ret i16 %1422}423 424define i32 @zext_nneg_i8_to_i32(i8 %a) nounwind {425; RV32I-LABEL: zext_nneg_i8_to_i32:426; RV32I: # %bb.0:427; RV32I-NEXT: zext.b a0, a0428; RV32I-NEXT: ret429;430; RV64-LABEL: zext_nneg_i8_to_i32:431; RV64: # %bb.0:432; RV64-NEXT: zext.b a0, a0433; RV64-NEXT: ret434 %1 = zext nneg i8 %a to i32435 ret i32 %1436}437 438define i64 @zext_nneg_i8_to_i64(i8 %a) nounwind {439; RV32I-LABEL: zext_nneg_i8_to_i64:440; RV32I: # %bb.0:441; RV32I-NEXT: zext.b a0, a0442; RV32I-NEXT: li a1, 0443; RV32I-NEXT: ret444;445; RV64-LABEL: zext_nneg_i8_to_i64:446; RV64: # %bb.0:447; RV64-NEXT: zext.b a0, a0448; RV64-NEXT: ret449 %1 = zext nneg i8 %a to i64450 ret i64 %1451}452 453define i32 @zext_nneg_i16_to_i32(i16 %a) nounwind {454; RV32I-LABEL: zext_nneg_i16_to_i32:455; RV32I: # %bb.0:456; RV32I-NEXT: slli a0, a0, 16457; RV32I-NEXT: srli a0, a0, 16458; RV32I-NEXT: ret459;460; RV64I-LABEL: zext_nneg_i16_to_i32:461; RV64I: # %bb.0:462; RV64I-NEXT: slli a0, a0, 48463; RV64I-NEXT: srli a0, a0, 48464; RV64I-NEXT: ret465;466; RV64ZBB-LABEL: zext_nneg_i16_to_i32:467; RV64ZBB: # %bb.0:468; RV64ZBB-NEXT: zext.h a0, a0469; RV64ZBB-NEXT: ret470 %1 = zext nneg i16 %a to i32471 ret i32 %1472}473 474define i64 @zext_nneg_i16_to_i64(i16 %a) nounwind {475; RV32I-LABEL: zext_nneg_i16_to_i64:476; RV32I: # %bb.0:477; RV32I-NEXT: slli a0, a0, 16478; RV32I-NEXT: srli a0, a0, 16479; RV32I-NEXT: li a1, 0480; RV32I-NEXT: ret481;482; RV64I-LABEL: zext_nneg_i16_to_i64:483; RV64I: # %bb.0:484; RV64I-NEXT: slli a0, a0, 48485; RV64I-NEXT: srli a0, a0, 48486; RV64I-NEXT: ret487;488; RV64ZBB-LABEL: zext_nneg_i16_to_i64:489; RV64ZBB: # %bb.0:490; RV64ZBB-NEXT: zext.h a0, a0491; RV64ZBB-NEXT: ret492 %1 = zext nneg i16 %a to i64493 ret i64 %1494}495 496define i64 @zext_nneg_i32_to_i64(i32 %a) nounwind {497; RV32I-LABEL: zext_nneg_i32_to_i64:498; RV32I: # %bb.0:499; RV32I-NEXT: li a1, 0500; RV32I-NEXT: ret501;502; RV64-LABEL: zext_nneg_i32_to_i64:503; RV64: # %bb.0:504; RV64-NEXT: sext.w a0, a0505; RV64-NEXT: ret506 %1 = zext nneg i32 %a to i64507 ret i64 %1508}509 510define i1 @trunc_i8_to_i1(i8 %a) nounwind {511; RV32I-LABEL: trunc_i8_to_i1:512; RV32I: # %bb.0:513; RV32I-NEXT: ret514;515; RV64-LABEL: trunc_i8_to_i1:516; RV64: # %bb.0:517; RV64-NEXT: ret518 %1 = trunc i8 %a to i1519 ret i1 %1520}521 522define i1 @trunc_i16_to_i1(i16 %a) nounwind {523; RV32I-LABEL: trunc_i16_to_i1:524; RV32I: # %bb.0:525; RV32I-NEXT: ret526;527; RV64-LABEL: trunc_i16_to_i1:528; RV64: # %bb.0:529; RV64-NEXT: ret530 %1 = trunc i16 %a to i1531 ret i1 %1532}533 534define i1 @trunc_i32_to_i1(i32 %a) nounwind {535; RV32I-LABEL: trunc_i32_to_i1:536; RV32I: # %bb.0:537; RV32I-NEXT: ret538;539; RV64-LABEL: trunc_i32_to_i1:540; RV64: # %bb.0:541; RV64-NEXT: ret542 %1 = trunc i32 %a to i1543 ret i1 %1544}545 546define i1 @trunc_i64_to_i1(i64 %a) nounwind {547; RV32I-LABEL: trunc_i64_to_i1:548; RV32I: # %bb.0:549; RV32I-NEXT: ret550;551; RV64-LABEL: trunc_i64_to_i1:552; RV64: # %bb.0:553; RV64-NEXT: ret554 %1 = trunc i64 %a to i1555 ret i1 %1556}557 558define i8 @trunc_i16_to_i8(i16 %a) nounwind {559; RV32I-LABEL: trunc_i16_to_i8:560; RV32I: # %bb.0:561; RV32I-NEXT: ret562;563; RV64-LABEL: trunc_i16_to_i8:564; RV64: # %bb.0:565; RV64-NEXT: ret566 %1 = trunc i16 %a to i8567 ret i8 %1568}569 570define i8 @trunc_i32_to_i8(i32 %a) nounwind {571; RV32I-LABEL: trunc_i32_to_i8:572; RV32I: # %bb.0:573; RV32I-NEXT: ret574;575; RV64-LABEL: trunc_i32_to_i8:576; RV64: # %bb.0:577; RV64-NEXT: ret578 %1 = trunc i32 %a to i8579 ret i8 %1580}581 582define i8 @trunc_i64_to_i8(i64 %a) nounwind {583; RV32I-LABEL: trunc_i64_to_i8:584; RV32I: # %bb.0:585; RV32I-NEXT: ret586;587; RV64-LABEL: trunc_i64_to_i8:588; RV64: # %bb.0:589; RV64-NEXT: ret590 %1 = trunc i64 %a to i8591 ret i8 %1592}593 594define i16 @trunc_i32_to_i16(i32 %a) nounwind {595; RV32I-LABEL: trunc_i32_to_i16:596; RV32I: # %bb.0:597; RV32I-NEXT: ret598;599; RV64-LABEL: trunc_i32_to_i16:600; RV64: # %bb.0:601; RV64-NEXT: ret602 %1 = trunc i32 %a to i16603 ret i16 %1604}605 606define i16 @trunc_i64_to_i16(i64 %a) nounwind {607; RV32I-LABEL: trunc_i64_to_i16:608; RV32I: # %bb.0:609; RV32I-NEXT: ret610;611; RV64-LABEL: trunc_i64_to_i16:612; RV64: # %bb.0:613; RV64-NEXT: ret614 %1 = trunc i64 %a to i16615 ret i16 %1616}617 618define i32 @trunc_i64_to_i32(i64 %a) nounwind {619; RV32I-LABEL: trunc_i64_to_i32:620; RV32I: # %bb.0:621; RV32I-NEXT: ret622;623; RV64-LABEL: trunc_i64_to_i32:624; RV64: # %bb.0:625; RV64-NEXT: ret626 %1 = trunc i64 %a to i32627 ret i32 %1628}629 630;; fold (sext (not x)) -> (add (zext x) -1)631define i32 @sext_of_not_i32(i1 %x) {632; RV32I-LABEL: sext_of_not_i32:633; RV32I: # %bb.0:634; RV32I-NEXT: andi a0, a0, 1635; RV32I-NEXT: addi a0, a0, -1636; RV32I-NEXT: ret637;638; RV64-LABEL: sext_of_not_i32:639; RV64: # %bb.0:640; RV64-NEXT: andi a0, a0, 1641; RV64-NEXT: addi a0, a0, -1642; RV64-NEXT: ret643 %xor = xor i1 %x, 1644 %sext = sext i1 %xor to i32645 ret i32 %sext646}647 648define i64 @sext_of_not_i64(i1 %x) {649; RV32I-LABEL: sext_of_not_i64:650; RV32I: # %bb.0:651; RV32I-NEXT: andi a0, a0, 1652; RV32I-NEXT: addi a0, a0, -1653; RV32I-NEXT: mv a1, a0654; RV32I-NEXT: ret655;656; RV64-LABEL: sext_of_not_i64:657; RV64: # %bb.0:658; RV64-NEXT: andi a0, a0, 1659; RV64-NEXT: addi a0, a0, -1660; RV64-NEXT: ret661 %xor = xor i1 %x, 1662 %sext = sext i1 %xor to i64663 ret i64 %sext664}665 666;; fold (sext (not (setcc a, b, cc))) -> (sext (setcc a, b, !cc))667define i32 @sext_of_not_cmp_i32(i32 %x) {668; RV32I-LABEL: sext_of_not_cmp_i32:669; RV32I: # %bb.0:670; RV32I-NEXT: addi a0, a0, -7671; RV32I-NEXT: seqz a0, a0672; RV32I-NEXT: addi a0, a0, -1673; RV32I-NEXT: ret674;675; RV64-LABEL: sext_of_not_cmp_i32:676; RV64: # %bb.0:677; RV64-NEXT: addiw a0, a0, -7678; RV64-NEXT: seqz a0, a0679; RV64-NEXT: addi a0, a0, -1680; RV64-NEXT: ret681 %cmp = icmp eq i32 %x, 7682 %xor = xor i1 %cmp, 1683 %sext = sext i1 %xor to i32684 ret i32 %sext685}686 687define i64 @sext_of_not_cmp_i64(i64 %x) {688; RV32I-LABEL: sext_of_not_cmp_i64:689; RV32I: # %bb.0:690; RV32I-NEXT: xori a0, a0, 7691; RV32I-NEXT: or a0, a0, a1692; RV32I-NEXT: seqz a0, a0693; RV32I-NEXT: addi a0, a0, -1694; RV32I-NEXT: mv a1, a0695; RV32I-NEXT: ret696;697; RV64-LABEL: sext_of_not_cmp_i64:698; RV64: # %bb.0:699; RV64-NEXT: addi a0, a0, -7700; RV64-NEXT: seqz a0, a0701; RV64-NEXT: addi a0, a0, -1702; RV64-NEXT: ret703 %cmp = icmp eq i64 %x, 7704 %xor = xor i1 %cmp, 1705 %sext = sext i1 %xor to i64706 ret i64 %sext707}708 709;; TODO: fold (add (zext (setcc a, b, cc)), -1) -> (sext (setcc a, b, !cc))710define i32 @dec_of_zexted_cmp_i32(i32 %x) {711; RV32I-LABEL: dec_of_zexted_cmp_i32:712; RV32I: # %bb.0:713; RV32I-NEXT: addi a0, a0, -7714; RV32I-NEXT: seqz a0, a0715; RV32I-NEXT: addi a0, a0, -1716; RV32I-NEXT: ret717;718; RV64-LABEL: dec_of_zexted_cmp_i32:719; RV64: # %bb.0:720; RV64-NEXT: addiw a0, a0, -7721; RV64-NEXT: seqz a0, a0722; RV64-NEXT: addi a0, a0, -1723; RV64-NEXT: ret724 %cmp = icmp eq i32 %x, 7725 %zext = zext i1 %cmp to i32726 %dec = sub i32 %zext, 1727 ret i32 %dec728}729 730define i64 @dec_of_zexted_cmp_i64(i64 %x) {731; RV32I-LABEL: dec_of_zexted_cmp_i64:732; RV32I: # %bb.0:733; RV32I-NEXT: xori a0, a0, 7734; RV32I-NEXT: or a0, a0, a1735; RV32I-NEXT: seqz a0, a0736; RV32I-NEXT: addi a0, a0, -1737; RV32I-NEXT: mv a1, a0738; RV32I-NEXT: ret739;740; RV64-LABEL: dec_of_zexted_cmp_i64:741; RV64: # %bb.0:742; RV64-NEXT: addi a0, a0, -7743; RV64-NEXT: seqz a0, a0744; RV64-NEXT: addi a0, a0, -1745; RV64-NEXT: ret746 %cmp = icmp eq i64 %x, 7747 %zext = zext i1 %cmp to i64748 %dec = sub i64 %zext, 1749 ret i64 %dec750}751 752define void @zext_nneg_dominating_icmp_i64(i16 signext %0) {753; RV32I-LABEL: zext_nneg_dominating_icmp_i64:754; RV32I: # %bb.0:755; RV32I-NEXT: bltz a0, .LBB46_2756; RV32I-NEXT: # %bb.1:757; RV32I-NEXT: srai a1, a0, 31758; RV32I-NEXT: tail bar_i64759; RV32I-NEXT: .LBB46_2:760; RV32I-NEXT: ret761;762; RV64-LABEL: zext_nneg_dominating_icmp_i64:763; RV64: # %bb.0:764; RV64-NEXT: bltz a0, .LBB46_2765; RV64-NEXT: # %bb.1:766; RV64-NEXT: tail bar_i64767; RV64-NEXT: .LBB46_2:768; RV64-NEXT: ret769 %2 = icmp sgt i16 %0, -1770 br i1 %2, label %3, label %5771 7723:773 %4 = zext nneg i16 %0 to i64774 tail call void @bar_i64(i64 %4)775 br label %5776 7775:778 ret void779}780 781declare void @bar_i64(i64)782 783define void @zext_nneg_dominating_icmp_i32(i16 signext %0) {784; RV32I-LABEL: zext_nneg_dominating_icmp_i32:785; RV32I: # %bb.0:786; RV32I-NEXT: bltz a0, .LBB47_2787; RV32I-NEXT: # %bb.1:788; RV32I-NEXT: tail bar_i32789; RV32I-NEXT: .LBB47_2:790; RV32I-NEXT: ret791;792; RV64-LABEL: zext_nneg_dominating_icmp_i32:793; RV64: # %bb.0:794; RV64-NEXT: bltz a0, .LBB47_2795; RV64-NEXT: # %bb.1:796; RV64-NEXT: tail bar_i32797; RV64-NEXT: .LBB47_2:798; RV64-NEXT: ret799 %2 = icmp sgt i16 %0, -1800 br i1 %2, label %3, label %5801 8023:803 %4 = zext nneg i16 %0 to i32804 tail call void @bar_i32(i32 %4)805 br label %5806 8075:808 ret void809}810 811declare void @bar_i32(i32)812 813; Test that we propage zext nneg when we sign extend it on RV64 for the call to814; bar_i32.815define void @zext_nneg_dominating_icmp_i32_signext(i16 signext %0) {816; RV32I-LABEL: zext_nneg_dominating_icmp_i32_signext:817; RV32I: # %bb.0:818; RV32I-NEXT: bltz a0, .LBB48_2819; RV32I-NEXT: # %bb.1:820; RV32I-NEXT: tail bar_i32821; RV32I-NEXT: .LBB48_2:822; RV32I-NEXT: ret823;824; RV64-LABEL: zext_nneg_dominating_icmp_i32_signext:825; RV64: # %bb.0:826; RV64-NEXT: bltz a0, .LBB48_2827; RV64-NEXT: # %bb.1:828; RV64-NEXT: tail bar_i32829; RV64-NEXT: .LBB48_2:830; RV64-NEXT: ret831 %2 = icmp sgt i16 %0, -1832 br i1 %2, label %3, label %5833 8343:835 %4 = zext nneg i16 %0 to i32836 tail call void @bar_i32(i32 signext %4)837 br label %5838 8395:840 ret void841}842 843; Test that we propage zext nneg when we zero extend it on RV64 for the call to844; bar_i32.845define void @zext_nneg_dominating_icmp_i32_zeroext(i16 signext %0) {846; RV32I-LABEL: zext_nneg_dominating_icmp_i32_zeroext:847; RV32I: # %bb.0:848; RV32I-NEXT: bltz a0, .LBB49_2849; RV32I-NEXT: # %bb.1:850; RV32I-NEXT: tail bar_i32851; RV32I-NEXT: .LBB49_2:852; RV32I-NEXT: ret853;854; RV64-LABEL: zext_nneg_dominating_icmp_i32_zeroext:855; RV64: # %bb.0:856; RV64-NEXT: bltz a0, .LBB49_2857; RV64-NEXT: # %bb.1:858; RV64-NEXT: tail bar_i32859; RV64-NEXT: .LBB49_2:860; RV64-NEXT: ret861 %2 = icmp sgt i16 %0, -1862 br i1 %2, label %3, label %5863 8643:865 %4 = zext nneg i16 %0 to i32866 tail call void @bar_i32(i32 signext %4)867 br label %5868 8695:870 ret void871}872 873; The load is used extended and non-extended in the successor basic block. The874; signed compare will cause the non-extended value to exported out of the first875; basic block using a sext to XLen. We need to CSE the zext nneg with the sext876; so that we can form a sextload.877define void @load_zext_nneg_sext_cse(ptr %p) nounwind {878; RV32I-LABEL: load_zext_nneg_sext_cse:879; RV32I: # %bb.0:880; RV32I-NEXT: addi sp, sp, -16881; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill882; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill883; RV32I-NEXT: lh s0, 0(a0)884; RV32I-NEXT: bltz s0, .LBB50_2885; RV32I-NEXT: # %bb.1: # %bb1886; RV32I-NEXT: mv a0, s0887; RV32I-NEXT: call bar_i16888; RV32I-NEXT: mv a0, s0889; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload890; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload891; RV32I-NEXT: addi sp, sp, 16892; RV32I-NEXT: tail bar_i32893; RV32I-NEXT: .LBB50_2: # %bb2894; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload895; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload896; RV32I-NEXT: addi sp, sp, 16897; RV32I-NEXT: ret898;899; RV64-LABEL: load_zext_nneg_sext_cse:900; RV64: # %bb.0:901; RV64-NEXT: addi sp, sp, -16902; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill903; RV64-NEXT: sd s0, 0(sp) # 8-byte Folded Spill904; RV64-NEXT: lh s0, 0(a0)905; RV64-NEXT: bltz s0, .LBB50_2906; RV64-NEXT: # %bb.1: # %bb1907; RV64-NEXT: mv a0, s0908; RV64-NEXT: call bar_i16909; RV64-NEXT: mv a0, s0910; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload911; RV64-NEXT: ld s0, 0(sp) # 8-byte Folded Reload912; RV64-NEXT: addi sp, sp, 16913; RV64-NEXT: tail bar_i32914; RV64-NEXT: .LBB50_2: # %bb2915; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload916; RV64-NEXT: ld s0, 0(sp) # 8-byte Folded Reload917; RV64-NEXT: addi sp, sp, 16918; RV64-NEXT: ret919 %load = load i16, ptr %p920 %zext = zext nneg i16 %load to i32921 %cmp = icmp sgt i16 %load, -1922 br i1 %cmp, label %bb1, label %bb2923 924bb1:925 tail call void @bar_i16(i16 signext %load)926 tail call void @bar_i32(i32 signext %zext)927 br label %bb2928 929bb2:930 ret void931}932declare void @bar_i16(i16);933