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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV32I4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefix=RV64I6 7define i32 @shl_by_complemented_32(i32 %x) {8; RV32I-LABEL: shl_by_complemented_32:9; RV32I: # %bb.0:10; RV32I-NEXT: not a1, a011; RV32I-NEXT: sll a0, a0, a112; RV32I-NEXT: ret13;14; RV64I-LABEL: shl_by_complemented_32:15; RV64I: # %bb.0:16; RV64I-NEXT: not a1, a017; RV64I-NEXT: sllw a0, a0, a118; RV64I-NEXT: ret19 %a = sub i32 31, %x20 %b = shl i32 %x, %a21 ret i32 %b22}23 24define i64 @shl_by_complemented_64(i64 %x) {25; RV32I-LABEL: shl_by_complemented_64:26; RV32I: # %bb.0:27; RV32I-NEXT: not a4, a028; RV32I-NEXT: li a2, 3129; RV32I-NEXT: sub a2, a2, a030; RV32I-NEXT: sll a3, a0, a431; RV32I-NEXT: bltz a2, .LBB1_232; RV32I-NEXT: # %bb.1:33; RV32I-NEXT: mv a1, a334; RV32I-NEXT: j .LBB1_335; RV32I-NEXT: .LBB1_2:36; RV32I-NEXT: sll a1, a1, a437; RV32I-NEXT: li a4, 6338; RV32I-NEXT: sub a4, a4, a039; RV32I-NEXT: not a4, a440; RV32I-NEXT: srli a0, a0, 141; RV32I-NEXT: srl a0, a0, a442; RV32I-NEXT: or a1, a1, a043; RV32I-NEXT: .LBB1_3:44; RV32I-NEXT: srai a0, a2, 3145; RV32I-NEXT: and a0, a0, a346; RV32I-NEXT: ret47;48; RV64I-LABEL: shl_by_complemented_64:49; RV64I: # %bb.0:50; RV64I-NEXT: not a1, a051; RV64I-NEXT: sll a0, a0, a152; RV64I-NEXT: ret53 %a = sub i64 63, %x54 %b = shl i64 %x, %a55 ret i64 %b56}57 58define i32 @lshr_by_complemented_32(i32 %x) {59; RV32I-LABEL: lshr_by_complemented_32:60; RV32I: # %bb.0:61; RV32I-NEXT: not a1, a062; RV32I-NEXT: srl a0, a0, a163; RV32I-NEXT: ret64;65; RV64I-LABEL: lshr_by_complemented_32:66; RV64I: # %bb.0:67; RV64I-NEXT: not a1, a068; RV64I-NEXT: srlw a0, a0, a169; RV64I-NEXT: ret70 %a = sub i32 31, %x71 %b = lshr i32 %x, %a72 ret i32 %b73}74 75define i64 @lshr_by_complemented_64(i64 %x) {76; RV32I-LABEL: lshr_by_complemented_64:77; RV32I: # %bb.0:78; RV32I-NEXT: not a4, a079; RV32I-NEXT: li a2, 3180; RV32I-NEXT: sub a2, a2, a081; RV32I-NEXT: srl a3, a1, a482; RV32I-NEXT: bltz a2, .LBB3_283; RV32I-NEXT: # %bb.1:84; RV32I-NEXT: mv a0, a385; RV32I-NEXT: j .LBB3_386; RV32I-NEXT: .LBB3_2:87; RV32I-NEXT: srl a4, a0, a488; RV32I-NEXT: li a5, 6389; RV32I-NEXT: sub a5, a5, a090; RV32I-NEXT: not a0, a591; RV32I-NEXT: slli a1, a1, 192; RV32I-NEXT: sll a0, a1, a093; RV32I-NEXT: or a0, a4, a094; RV32I-NEXT: .LBB3_3:95; RV32I-NEXT: srai a1, a2, 3196; RV32I-NEXT: and a1, a1, a397; RV32I-NEXT: ret98;99; RV64I-LABEL: lshr_by_complemented_64:100; RV64I: # %bb.0:101; RV64I-NEXT: not a1, a0102; RV64I-NEXT: srl a0, a0, a1103; RV64I-NEXT: ret104 %a = sub i64 63, %x105 %b = lshr i64 %x, %a106 ret i64 %b107}108 109define i32 @ashr_by_complemented_32(i32 %x) {110; RV32I-LABEL: ashr_by_complemented_32:111; RV32I: # %bb.0:112; RV32I-NEXT: not a1, a0113; RV32I-NEXT: sra a0, a0, a1114; RV32I-NEXT: ret115;116; RV64I-LABEL: ashr_by_complemented_32:117; RV64I: # %bb.0:118; RV64I-NEXT: not a1, a0119; RV64I-NEXT: sraw a0, a0, a1120; RV64I-NEXT: ret121 %a = sub i32 31, %x122 %b = ashr i32 %x, %a123 ret i32 %b124}125 126define i64 @ashr_by_complemented_64(i64 %x) {127; RV32I-LABEL: ashr_by_complemented_64:128; RV32I: # %bb.0:129; RV32I-NEXT: mv a2, a0130; RV32I-NEXT: li a0, 31131; RV32I-NEXT: sub a4, a0, a2132; RV32I-NEXT: not a3, a2133; RV32I-NEXT: sra a0, a1, a3134; RV32I-NEXT: bltz a4, .LBB5_2135; RV32I-NEXT: # %bb.1:136; RV32I-NEXT: srai a1, a1, 31137; RV32I-NEXT: ret138; RV32I-NEXT: .LBB5_2:139; RV32I-NEXT: srl a3, a2, a3140; RV32I-NEXT: li a4, 63141; RV32I-NEXT: sub a4, a4, a2142; RV32I-NEXT: not a2, a4143; RV32I-NEXT: slli a1, a1, 1144; RV32I-NEXT: sll a1, a1, a2145; RV32I-NEXT: or a3, a3, a1146; RV32I-NEXT: mv a1, a0147; RV32I-NEXT: mv a0, a3148; RV32I-NEXT: ret149;150; RV64I-LABEL: ashr_by_complemented_64:151; RV64I: # %bb.0:152; RV64I-NEXT: not a1, a0153; RV64I-NEXT: sra a0, a0, a1154; RV64I-NEXT: ret155 %a = sub i64 63, %x156 %b = ashr i64 %x, %a157 ret i64 %b158}159 160define i32 @shl_by_masked_complemented_32(i32 %x) {161; RV32I-LABEL: shl_by_masked_complemented_32:162; RV32I: # %bb.0:163; RV32I-NEXT: not a1, a0164; RV32I-NEXT: sll a0, a0, a1165; RV32I-NEXT: ret166;167; RV64I-LABEL: shl_by_masked_complemented_32:168; RV64I: # %bb.0:169; RV64I-NEXT: not a1, a0170; RV64I-NEXT: sllw a0, a0, a1171; RV64I-NEXT: ret172 %a = sub i32 31, %x173 %b = and i32 %a, 31174 %c = shl i32 %x, %b175 ret i32 %c176}177 178define i64 @shl_by_masked_complemented_64(i64 %x) {179; RV32I-LABEL: shl_by_masked_complemented_64:180; RV32I: # %bb.0:181; RV32I-NEXT: li a2, 63182; RV32I-NEXT: sub a2, a2, a0183; RV32I-NEXT: andi a4, a2, 63184; RV32I-NEXT: addi a2, a4, -32185; RV32I-NEXT: not a3, a0186; RV32I-NEXT: bltz a2, .LBB7_2187; RV32I-NEXT: # %bb.1:188; RV32I-NEXT: sll a1, a0, a4189; RV32I-NEXT: j .LBB7_3190; RV32I-NEXT: .LBB7_2:191; RV32I-NEXT: sll a1, a1, a3192; RV32I-NEXT: not a4, a4193; RV32I-NEXT: srli a5, a0, 1194; RV32I-NEXT: srl a4, a5, a4195; RV32I-NEXT: or a1, a1, a4196; RV32I-NEXT: .LBB7_3:197; RV32I-NEXT: sll a0, a0, a3198; RV32I-NEXT: srai a2, a2, 31199; RV32I-NEXT: and a0, a2, a0200; RV32I-NEXT: ret201;202; RV64I-LABEL: shl_by_masked_complemented_64:203; RV64I: # %bb.0:204; RV64I-NEXT: not a1, a0205; RV64I-NEXT: sll a0, a0, a1206; RV64I-NEXT: ret207 %a = sub i64 63, %x208 %b = and i64 %a, 63209 %c = shl i64 %x, %b210 ret i64 %c211}212 213define i64 @lshr_by_masked_complemented_64(i64 %x) {214; RV32I-LABEL: lshr_by_masked_complemented_64:215; RV32I: # %bb.0:216; RV32I-NEXT: li a2, 63217; RV32I-NEXT: sub a2, a2, a0218; RV32I-NEXT: andi a4, a2, 63219; RV32I-NEXT: addi a2, a4, -32220; RV32I-NEXT: not a3, a0221; RV32I-NEXT: bltz a2, .LBB8_2222; RV32I-NEXT: # %bb.1:223; RV32I-NEXT: srl a0, a1, a4224; RV32I-NEXT: j .LBB8_3225; RV32I-NEXT: .LBB8_2:226; RV32I-NEXT: srl a0, a0, a3227; RV32I-NEXT: not a4, a4228; RV32I-NEXT: slli a5, a1, 1229; RV32I-NEXT: sll a4, a5, a4230; RV32I-NEXT: or a0, a0, a4231; RV32I-NEXT: .LBB8_3:232; RV32I-NEXT: srl a1, a1, a3233; RV32I-NEXT: srai a2, a2, 31234; RV32I-NEXT: and a1, a2, a1235; RV32I-NEXT: ret236;237; RV64I-LABEL: lshr_by_masked_complemented_64:238; RV64I: # %bb.0:239; RV64I-NEXT: not a1, a0240; RV64I-NEXT: srl a0, a0, a1241; RV64I-NEXT: ret242 %a = sub i64 63, %x243 %b = and i64 %a, 63244 %c = lshr i64 %x, %b245 ret i64 %c246}247 248define i64 @ashr_by_masked_complemented_64(i64 %x) {249; RV32I-LABEL: ashr_by_masked_complemented_64:250; RV32I: # %bb.0:251; RV32I-NEXT: li a2, 63252; RV32I-NEXT: sub a2, a2, a0253; RV32I-NEXT: andi a2, a2, 63254; RV32I-NEXT: addi a3, a2, -32255; RV32I-NEXT: bltz a3, .LBB9_2256; RV32I-NEXT: # %bb.1:257; RV32I-NEXT: mv a0, a1258; RV32I-NEXT: srai a1, a1, 31259; RV32I-NEXT: sra a0, a0, a2260; RV32I-NEXT: ret261; RV32I-NEXT: .LBB9_2:262; RV32I-NEXT: not a3, a0263; RV32I-NEXT: not a2, a2264; RV32I-NEXT: slli a4, a1, 1265; RV32I-NEXT: sra a1, a1, a3266; RV32I-NEXT: srl a0, a0, a3267; RV32I-NEXT: sll a2, a4, a2268; RV32I-NEXT: or a0, a0, a2269; RV32I-NEXT: ret270;271; RV64I-LABEL: ashr_by_masked_complemented_64:272; RV64I: # %bb.0:273; RV64I-NEXT: not a1, a0274; RV64I-NEXT: sra a0, a0, a1275; RV64I-NEXT: ret276 %a = sub i64 63, %x277 %b = and i64 %a, 63278 %c = ashr i64 %x, %b279 ret i64 %c280}281