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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV32I4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefix=RV64I6 7; Test for handling of AND with constant followed by a shift by constant. Often8; we can replace these with a pair of shifts to avoid materializing a constant9; for the and.10 11define i32 @test1(i32 %x) {12; RV32I-LABEL: test1:13; RV32I: # %bb.0:14; RV32I-NEXT: srli a0, a0, 515; RV32I-NEXT: andi a0, a0, -816; RV32I-NEXT: ret17;18; RV64I-LABEL: test1:19; RV64I: # %bb.0:20; RV64I-NEXT: srliw a0, a0, 821; RV64I-NEXT: slli a0, a0, 322; RV64I-NEXT: ret23 %a = lshr i32 %x, 524 %b = and i32 %a, 13421772025 ret i32 %b26}27 28define i64 @test2(i64 %x) {29; RV32I-LABEL: test2:30; RV32I: # %bb.0:31; RV32I-NEXT: slli a2, a1, 2732; RV32I-NEXT: srli a0, a0, 533; RV32I-NEXT: or a0, a0, a234; RV32I-NEXT: srli a1, a1, 535; RV32I-NEXT: andi a0, a0, -836; RV32I-NEXT: ret37;38; RV64I-LABEL: test2:39; RV64I: # %bb.0:40; RV64I-NEXT: srli a0, a0, 541; RV64I-NEXT: andi a0, a0, -842; RV64I-NEXT: ret43 %a = lshr i64 %x, 544 %b = and i64 %a, 57646075230342348045 ret i64 %b46}47 48define i32 @test3(i32 %x) {49; RV32I-LABEL: test3:50; RV32I: # %bb.0:51; RV32I-NEXT: srli a0, a0, 2052; RV32I-NEXT: slli a0, a0, 1453; RV32I-NEXT: ret54;55; RV64I-LABEL: test3:56; RV64I: # %bb.0:57; RV64I-NEXT: srliw a0, a0, 2058; RV64I-NEXT: slli a0, a0, 1459; RV64I-NEXT: ret60 %a = lshr i32 %x, 661 %b = and i32 %a, 6709248062 ret i32 %b63}64 65define i64 @test4(i64 %x) {66; RV32I-LABEL: test4:67; RV32I: # %bb.0:68; RV32I-NEXT: slli a2, a1, 2669; RV32I-NEXT: srli a0, a0, 670; RV32I-NEXT: srli a1, a1, 671; RV32I-NEXT: or a0, a0, a272; RV32I-NEXT: lui a2, 104857273; RV32I-NEXT: and a0, a0, a274; RV32I-NEXT: ret75;76; RV64I-LABEL: test4:77; RV64I: # %bb.0:78; RV64I-NEXT: srli a0, a0, 2079; RV64I-NEXT: slli a0, a0, 1480; RV64I-NEXT: ret81 %a = lshr i64 %x, 682 %b = and i64 %a, 28823037615169536083 ret i64 %b84}85 86define i32 @test5(i32 %x) {87; RV32I-LABEL: test5:88; RV32I: # %bb.0:89; RV32I-NEXT: srli a0, a0, 1090; RV32I-NEXT: slli a0, a0, 1691; RV32I-NEXT: ret92;93; RV64I-LABEL: test5:94; RV64I: # %bb.0:95; RV64I-NEXT: andi a0, a0, -102496; RV64I-NEXT: slliw a0, a0, 697; RV64I-NEXT: ret98 %a = shl i32 %x, 699 %b = and i32 %a, -65536100 ret i32 %b101}102 103define i64 @test6(i64 %x) {104; RV32I-LABEL: test6:105; RV32I: # %bb.0:106; RV32I-NEXT: srli a2, a0, 26107; RV32I-NEXT: slli a1, a1, 6108; RV32I-NEXT: srli a0, a0, 10109; RV32I-NEXT: or a1, a1, a2110; RV32I-NEXT: slli a0, a0, 16111; RV32I-NEXT: ret112;113; RV64I-LABEL: test6:114; RV64I: # %bb.0:115; RV64I-NEXT: srli a0, a0, 10116; RV64I-NEXT: slli a0, a0, 16117; RV64I-NEXT: ret118 %a = shl i64 %x, 6119 %b = and i64 %a, -65536120 ret i64 %b121}122