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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV32I4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefix=RV64I6 7; This test checks that unnecessary masking of shift amount operands is8; eliminated during instruction selection. The test needs to ensure that the9; masking is not removed if it may affect the shift amount.10 11define i32 @sll_redundant_mask(i32 %a, i32 %b) nounwind {12; RV32I-LABEL: sll_redundant_mask:13; RV32I: # %bb.0:14; RV32I-NEXT: sll a0, a0, a115; RV32I-NEXT: ret16;17; RV64I-LABEL: sll_redundant_mask:18; RV64I: # %bb.0:19; RV64I-NEXT: sllw a0, a0, a120; RV64I-NEXT: ret21 %1 = and i32 %b, 3122 %2 = shl i32 %a, %123 ret i32 %224}25 26define i32 @sll_non_redundant_mask(i32 %a, i32 %b) nounwind {27; RV32I-LABEL: sll_non_redundant_mask:28; RV32I: # %bb.0:29; RV32I-NEXT: andi a1, a1, 1530; RV32I-NEXT: sll a0, a0, a131; RV32I-NEXT: ret32;33; RV64I-LABEL: sll_non_redundant_mask:34; RV64I: # %bb.0:35; RV64I-NEXT: andi a1, a1, 1536; RV64I-NEXT: sllw a0, a0, a137; RV64I-NEXT: ret38 %1 = and i32 %b, 1539 %2 = shl i32 %a, %140 ret i32 %241}42 43define i32 @srl_redundant_mask(i32 %a, i32 %b) nounwind {44; RV32I-LABEL: srl_redundant_mask:45; RV32I: # %bb.0:46; RV32I-NEXT: srl a0, a0, a147; RV32I-NEXT: ret48;49; RV64I-LABEL: srl_redundant_mask:50; RV64I: # %bb.0:51; RV64I-NEXT: srlw a0, a0, a152; RV64I-NEXT: ret53 %1 = and i32 %b, 409554 %2 = lshr i32 %a, %155 ret i32 %256}57 58define i32 @srl_non_redundant_mask(i32 %a, i32 %b) nounwind {59; RV32I-LABEL: srl_non_redundant_mask:60; RV32I: # %bb.0:61; RV32I-NEXT: andi a1, a1, 762; RV32I-NEXT: srl a0, a0, a163; RV32I-NEXT: ret64;65; RV64I-LABEL: srl_non_redundant_mask:66; RV64I: # %bb.0:67; RV64I-NEXT: andi a1, a1, 768; RV64I-NEXT: srlw a0, a0, a169; RV64I-NEXT: ret70 %1 = and i32 %b, 771 %2 = lshr i32 %a, %172 ret i32 %273}74 75define i32 @sra_redundant_mask(i32 %a, i32 %b) nounwind {76; RV32I-LABEL: sra_redundant_mask:77; RV32I: # %bb.0:78; RV32I-NEXT: sra a0, a0, a179; RV32I-NEXT: ret80;81; RV64I-LABEL: sra_redundant_mask:82; RV64I: # %bb.0:83; RV64I-NEXT: sraw a0, a0, a184; RV64I-NEXT: ret85 %1 = and i32 %b, 6553586 %2 = ashr i32 %a, %187 ret i32 %288}89 90define i32 @sra_non_redundant_mask(i32 %a, i32 %b) nounwind {91; RV32I-LABEL: sra_non_redundant_mask:92; RV32I: # %bb.0:93; RV32I-NEXT: andi a1, a1, 3294; RV32I-NEXT: sra a0, a0, a195; RV32I-NEXT: ret96;97; RV64I-LABEL: sra_non_redundant_mask:98; RV64I: # %bb.0:99; RV64I-NEXT: sraw a0, a0, zero100; RV64I-NEXT: ret101 %1 = and i32 %b, 32102 %2 = ashr i32 %a, %1103 ret i32 %2104}105 106define i32 @sll_redundant_mask_zeros(i32 %a, i32 %b) nounwind {107; RV32I-LABEL: sll_redundant_mask_zeros:108; RV32I: # %bb.0:109; RV32I-NEXT: slli a1, a1, 1110; RV32I-NEXT: sll a0, a0, a1111; RV32I-NEXT: ret112;113; RV64I-LABEL: sll_redundant_mask_zeros:114; RV64I: # %bb.0:115; RV64I-NEXT: slli a1, a1, 1116; RV64I-NEXT: sllw a0, a0, a1117; RV64I-NEXT: ret118 %1 = shl i32 %b, 1119 %2 = and i32 %1, 30120 %3 = shl i32 %a, %2121 ret i32 %3122}123 124define i32 @srl_redundant_mask_zeros(i32 %a, i32 %b) nounwind {125; RV32I-LABEL: srl_redundant_mask_zeros:126; RV32I: # %bb.0:127; RV32I-NEXT: slli a1, a1, 2128; RV32I-NEXT: srl a0, a0, a1129; RV32I-NEXT: ret130;131; RV64I-LABEL: srl_redundant_mask_zeros:132; RV64I: # %bb.0:133; RV64I-NEXT: slli a1, a1, 2134; RV64I-NEXT: srlw a0, a0, a1135; RV64I-NEXT: ret136 %1 = shl i32 %b, 2137 %2 = and i32 %1, 28138 %3 = lshr i32 %a, %2139 ret i32 %3140}141 142define i32 @sra_redundant_mask_zeros(i32 %a, i32 %b) nounwind {143; RV32I-LABEL: sra_redundant_mask_zeros:144; RV32I: # %bb.0:145; RV32I-NEXT: slli a1, a1, 3146; RV32I-NEXT: sra a0, a0, a1147; RV32I-NEXT: ret148;149; RV64I-LABEL: sra_redundant_mask_zeros:150; RV64I: # %bb.0:151; RV64I-NEXT: slli a1, a1, 3152; RV64I-NEXT: sraw a0, a0, a1153; RV64I-NEXT: ret154 %1 = shl i32 %b, 3155 %2 = and i32 %1, 24156 %3 = ashr i32 %a, %2157 ret i32 %3158}159 160define i64 @sll_redundant_mask_zeros_i64(i64 %a, i64 %b) nounwind {161; RV32I-LABEL: sll_redundant_mask_zeros_i64:162; RV32I: # %bb.0:163; RV32I-NEXT: slli a2, a2, 2164; RV32I-NEXT: andi a4, a2, 60165; RV32I-NEXT: addi a3, a4, -32166; RV32I-NEXT: bltz a3, .LBB9_2167; RV32I-NEXT: # %bb.1:168; RV32I-NEXT: sll a1, a0, a4169; RV32I-NEXT: j .LBB9_3170; RV32I-NEXT: .LBB9_2:171; RV32I-NEXT: sll a1, a1, a2172; RV32I-NEXT: srli a5, a0, 1173; RV32I-NEXT: not a4, a4174; RV32I-NEXT: srl a4, a5, a4175; RV32I-NEXT: or a1, a1, a4176; RV32I-NEXT: .LBB9_3:177; RV32I-NEXT: sll a0, a0, a2178; RV32I-NEXT: srai a3, a3, 31179; RV32I-NEXT: and a0, a3, a0180; RV32I-NEXT: ret181;182; RV64I-LABEL: sll_redundant_mask_zeros_i64:183; RV64I: # %bb.0:184; RV64I-NEXT: slli a1, a1, 2185; RV64I-NEXT: sll a0, a0, a1186; RV64I-NEXT: ret187 %1 = shl i64 %b, 2188 %2 = and i64 %1, 60189 %3 = shl i64 %a, %2190 ret i64 %3191}192 193define i64 @srl_redundant_mask_zeros_i64(i64 %a, i64 %b) nounwind {194; RV32I-LABEL: srl_redundant_mask_zeros_i64:195; RV32I: # %bb.0:196; RV32I-NEXT: slli a2, a2, 3197; RV32I-NEXT: andi a4, a2, 56198; RV32I-NEXT: addi a3, a4, -32199; RV32I-NEXT: bltz a3, .LBB10_2200; RV32I-NEXT: # %bb.1:201; RV32I-NEXT: srl a0, a1, a4202; RV32I-NEXT: j .LBB10_3203; RV32I-NEXT: .LBB10_2:204; RV32I-NEXT: srl a0, a0, a2205; RV32I-NEXT: slli a5, a1, 1206; RV32I-NEXT: not a4, a4207; RV32I-NEXT: sll a4, a5, a4208; RV32I-NEXT: or a0, a0, a4209; RV32I-NEXT: .LBB10_3:210; RV32I-NEXT: srl a1, a1, a2211; RV32I-NEXT: srai a3, a3, 31212; RV32I-NEXT: and a1, a3, a1213; RV32I-NEXT: ret214;215; RV64I-LABEL: srl_redundant_mask_zeros_i64:216; RV64I: # %bb.0:217; RV64I-NEXT: slli a1, a1, 3218; RV64I-NEXT: srl a0, a0, a1219; RV64I-NEXT: ret220 %1 = shl i64 %b, 3221 %2 = and i64 %1, 56222 %3 = lshr i64 %a, %2223 ret i64 %3224}225 226define i64 @sra_redundant_mask_zeros_i64(i64 %a, i64 %b) nounwind {227; RV32I-LABEL: sra_redundant_mask_zeros_i64:228; RV32I: # %bb.0:229; RV32I-NEXT: slli a2, a2, 4230; RV32I-NEXT: andi a3, a2, 48231; RV32I-NEXT: addi a4, a3, -32232; RV32I-NEXT: bltz a4, .LBB11_2233; RV32I-NEXT: # %bb.1:234; RV32I-NEXT: sra a0, a1, a3235; RV32I-NEXT: srai a1, a1, 31236; RV32I-NEXT: ret237; RV32I-NEXT: .LBB11_2:238; RV32I-NEXT: srl a0, a0, a2239; RV32I-NEXT: slli a4, a1, 1240; RV32I-NEXT: not a3, a3241; RV32I-NEXT: sll a3, a4, a3242; RV32I-NEXT: or a0, a0, a3243; RV32I-NEXT: sra a1, a1, a2244; RV32I-NEXT: ret245;246; RV64I-LABEL: sra_redundant_mask_zeros_i64:247; RV64I: # %bb.0:248; RV64I-NEXT: slli a1, a1, 4249; RV64I-NEXT: sra a0, a0, a1250; RV64I-NEXT: ret251 %1 = shl i64 %b, 4252 %2 = and i64 %1, 48253 %3 = ashr i64 %a, %2254 ret i64 %3255}256