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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV32I4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefix=RV64I6 7; Basic shift support is tested as part of ALU.ll. This file ensures that8; shifts which may not be supported natively are lowered properly.9 10define i64 @lshr64(i64 %a, i64 %b) nounwind {11; RV32I-LABEL: lshr64:12; RV32I: # %bb.0:13; RV32I-NEXT: addi a4, a2, -3214; RV32I-NEXT: srl a3, a1, a215; RV32I-NEXT: bltz a4, .LBB0_216; RV32I-NEXT: # %bb.1:17; RV32I-NEXT: mv a0, a318; RV32I-NEXT: j .LBB0_319; RV32I-NEXT: .LBB0_2:20; RV32I-NEXT: srl a0, a0, a221; RV32I-NEXT: not a2, a222; RV32I-NEXT: slli a1, a1, 123; RV32I-NEXT: sll a1, a1, a224; RV32I-NEXT: or a0, a0, a125; RV32I-NEXT: .LBB0_3:26; RV32I-NEXT: srai a1, a4, 3127; RV32I-NEXT: and a1, a1, a328; RV32I-NEXT: ret29;30; RV64I-LABEL: lshr64:31; RV64I: # %bb.0:32; RV64I-NEXT: srl a0, a0, a133; RV64I-NEXT: ret34 %1 = lshr i64 %a, %b35 ret i64 %136}37 38define i64 @lshr64_minsize(i64 %a, i64 %b) minsize nounwind {39; RV32I-LABEL: lshr64_minsize:40; RV32I: # %bb.0:41; RV32I-NEXT: addi sp, sp, -1642; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill43; RV32I-NEXT: call __lshrdi344; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload45; RV32I-NEXT: addi sp, sp, 1646; RV32I-NEXT: ret47;48; RV64I-LABEL: lshr64_minsize:49; RV64I: # %bb.0:50; RV64I-NEXT: srl a0, a0, a151; RV64I-NEXT: ret52 %1 = lshr i64 %a, %b53 ret i64 %154}55 56define i64 @ashr64(i64 %a, i64 %b) nounwind {57; RV32I-LABEL: ashr64:58; RV32I: # %bb.0:59; RV32I-NEXT: mv a3, a160; RV32I-NEXT: addi a4, a2, -3261; RV32I-NEXT: sra a1, a1, a262; RV32I-NEXT: bltz a4, .LBB2_263; RV32I-NEXT: # %bb.1:64; RV32I-NEXT: srai a3, a3, 3165; RV32I-NEXT: mv a0, a166; RV32I-NEXT: mv a1, a367; RV32I-NEXT: ret68; RV32I-NEXT: .LBB2_2:69; RV32I-NEXT: srl a0, a0, a270; RV32I-NEXT: not a2, a271; RV32I-NEXT: slli a3, a3, 172; RV32I-NEXT: sll a2, a3, a273; RV32I-NEXT: or a0, a0, a274; RV32I-NEXT: ret75;76; RV64I-LABEL: ashr64:77; RV64I: # %bb.0:78; RV64I-NEXT: sra a0, a0, a179; RV64I-NEXT: ret80 %1 = ashr i64 %a, %b81 ret i64 %182}83 84define i64 @ashr64_minsize(i64 %a, i64 %b) minsize nounwind {85; RV32I-LABEL: ashr64_minsize:86; RV32I: # %bb.0:87; RV32I-NEXT: addi sp, sp, -1688; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill89; RV32I-NEXT: call __ashrdi390; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload91; RV32I-NEXT: addi sp, sp, 1692; RV32I-NEXT: ret93;94; RV64I-LABEL: ashr64_minsize:95; RV64I: # %bb.0:96; RV64I-NEXT: sra a0, a0, a197; RV64I-NEXT: ret98 %1 = ashr i64 %a, %b99 ret i64 %1100}101 102define i64 @shl64(i64 %a, i64 %b) nounwind {103; RV32I-LABEL: shl64:104; RV32I: # %bb.0:105; RV32I-NEXT: addi a4, a2, -32106; RV32I-NEXT: sll a3, a0, a2107; RV32I-NEXT: bltz a4, .LBB4_2108; RV32I-NEXT: # %bb.1:109; RV32I-NEXT: mv a1, a3110; RV32I-NEXT: j .LBB4_3111; RV32I-NEXT: .LBB4_2:112; RV32I-NEXT: sll a1, a1, a2113; RV32I-NEXT: not a2, a2114; RV32I-NEXT: srli a0, a0, 1115; RV32I-NEXT: srl a0, a0, a2116; RV32I-NEXT: or a1, a1, a0117; RV32I-NEXT: .LBB4_3:118; RV32I-NEXT: srai a0, a4, 31119; RV32I-NEXT: and a0, a0, a3120; RV32I-NEXT: ret121;122; RV64I-LABEL: shl64:123; RV64I: # %bb.0:124; RV64I-NEXT: sll a0, a0, a1125; RV64I-NEXT: ret126 %1 = shl i64 %a, %b127 ret i64 %1128}129 130define i64 @shl64_minsize(i64 %a, i64 %b) minsize nounwind {131; RV32I-LABEL: shl64_minsize:132; RV32I: # %bb.0:133; RV32I-NEXT: addi sp, sp, -16134; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill135; RV32I-NEXT: call __ashldi3136; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload137; RV32I-NEXT: addi sp, sp, 16138; RV32I-NEXT: ret139;140; RV64I-LABEL: shl64_minsize:141; RV64I: # %bb.0:142; RV64I-NEXT: sll a0, a0, a1143; RV64I-NEXT: ret144 %1 = shl i64 %a, %b145 ret i64 %1146}147 148define i128 @lshr128(i128 %a, i128 %b) nounwind {149; RV32I-LABEL: lshr128:150; RV32I: # %bb.0:151; RV32I-NEXT: addi sp, sp, -32152; RV32I-NEXT: lw a2, 0(a2)153; RV32I-NEXT: lw a3, 0(a1)154; RV32I-NEXT: lw a4, 4(a1)155; RV32I-NEXT: lw a5, 8(a1)156; RV32I-NEXT: lw a1, 12(a1)157; RV32I-NEXT: sw zero, 16(sp)158; RV32I-NEXT: sw zero, 20(sp)159; RV32I-NEXT: sw zero, 24(sp)160; RV32I-NEXT: sw zero, 28(sp)161; RV32I-NEXT: mv a6, sp162; RV32I-NEXT: sw a3, 0(sp)163; RV32I-NEXT: sw a4, 4(sp)164; RV32I-NEXT: sw a5, 8(sp)165; RV32I-NEXT: sw a1, 12(sp)166; RV32I-NEXT: srli a1, a2, 3167; RV32I-NEXT: andi a3, a2, 31168; RV32I-NEXT: andi a1, a1, 12169; RV32I-NEXT: xori a3, a3, 31170; RV32I-NEXT: add a1, a6, a1171; RV32I-NEXT: lw a4, 0(a1)172; RV32I-NEXT: lw a5, 4(a1)173; RV32I-NEXT: lw a6, 8(a1)174; RV32I-NEXT: lw a1, 12(a1)175; RV32I-NEXT: srl a4, a4, a2176; RV32I-NEXT: slli a7, a5, 1177; RV32I-NEXT: srl a5, a5, a2178; RV32I-NEXT: slli t0, a6, 1179; RV32I-NEXT: srl a6, a6, a2180; RV32I-NEXT: srl a2, a1, a2181; RV32I-NEXT: slli a1, a1, 1182; RV32I-NEXT: sll a7, a7, a3183; RV32I-NEXT: sll t0, t0, a3184; RV32I-NEXT: sll a1, a1, a3185; RV32I-NEXT: or a3, a4, a7186; RV32I-NEXT: or a4, a5, t0187; RV32I-NEXT: or a1, a6, a1188; RV32I-NEXT: sw a3, 0(a0)189; RV32I-NEXT: sw a4, 4(a0)190; RV32I-NEXT: sw a1, 8(a0)191; RV32I-NEXT: sw a2, 12(a0)192; RV32I-NEXT: addi sp, sp, 32193; RV32I-NEXT: ret194;195; RV64I-LABEL: lshr128:196; RV64I: # %bb.0:197; RV64I-NEXT: addi a4, a2, -64198; RV64I-NEXT: srl a3, a1, a2199; RV64I-NEXT: bltz a4, .LBB6_2200; RV64I-NEXT: # %bb.1:201; RV64I-NEXT: mv a0, a3202; RV64I-NEXT: j .LBB6_3203; RV64I-NEXT: .LBB6_2:204; RV64I-NEXT: srl a0, a0, a2205; RV64I-NEXT: not a2, a2206; RV64I-NEXT: slli a1, a1, 1207; RV64I-NEXT: sll a1, a1, a2208; RV64I-NEXT: or a0, a0, a1209; RV64I-NEXT: .LBB6_3:210; RV64I-NEXT: srai a1, a4, 63211; RV64I-NEXT: and a1, a1, a3212; RV64I-NEXT: ret213 %1 = lshr i128 %a, %b214 ret i128 %1215}216 217define i128 @ashr128(i128 %a, i128 %b) nounwind {218; RV32I-LABEL: ashr128:219; RV32I: # %bb.0:220; RV32I-NEXT: addi sp, sp, -32221; RV32I-NEXT: lw a2, 0(a2)222; RV32I-NEXT: lw a3, 0(a1)223; RV32I-NEXT: lw a4, 4(a1)224; RV32I-NEXT: lw a5, 8(a1)225; RV32I-NEXT: lw a1, 12(a1)226; RV32I-NEXT: mv a6, sp227; RV32I-NEXT: sw a3, 0(sp)228; RV32I-NEXT: sw a4, 4(sp)229; RV32I-NEXT: sw a5, 8(sp)230; RV32I-NEXT: sw a1, 12(sp)231; RV32I-NEXT: srai a1, a1, 31232; RV32I-NEXT: srli a3, a2, 3233; RV32I-NEXT: andi a4, a2, 31234; RV32I-NEXT: sw a1, 16(sp)235; RV32I-NEXT: sw a1, 20(sp)236; RV32I-NEXT: sw a1, 24(sp)237; RV32I-NEXT: sw a1, 28(sp)238; RV32I-NEXT: andi a3, a3, 12239; RV32I-NEXT: xori a1, a4, 31240; RV32I-NEXT: add a3, a6, a3241; RV32I-NEXT: lw a4, 0(a3)242; RV32I-NEXT: lw a5, 4(a3)243; RV32I-NEXT: lw a6, 8(a3)244; RV32I-NEXT: lw a3, 12(a3)245; RV32I-NEXT: srl a4, a4, a2246; RV32I-NEXT: slli a7, a5, 1247; RV32I-NEXT: srl a5, a5, a2248; RV32I-NEXT: slli t0, a6, 1249; RV32I-NEXT: srl a6, a6, a2250; RV32I-NEXT: sra a2, a3, a2251; RV32I-NEXT: slli a3, a3, 1252; RV32I-NEXT: sll a7, a7, a1253; RV32I-NEXT: sll t0, t0, a1254; RV32I-NEXT: sll a1, a3, a1255; RV32I-NEXT: or a3, a4, a7256; RV32I-NEXT: or a4, a5, t0257; RV32I-NEXT: or a1, a6, a1258; RV32I-NEXT: sw a3, 0(a0)259; RV32I-NEXT: sw a4, 4(a0)260; RV32I-NEXT: sw a1, 8(a0)261; RV32I-NEXT: sw a2, 12(a0)262; RV32I-NEXT: addi sp, sp, 32263; RV32I-NEXT: ret264;265; RV64I-LABEL: ashr128:266; RV64I: # %bb.0:267; RV64I-NEXT: mv a3, a1268; RV64I-NEXT: addi a4, a2, -64269; RV64I-NEXT: sra a1, a1, a2270; RV64I-NEXT: bltz a4, .LBB7_2271; RV64I-NEXT: # %bb.1:272; RV64I-NEXT: srai a3, a3, 63273; RV64I-NEXT: mv a0, a1274; RV64I-NEXT: mv a1, a3275; RV64I-NEXT: ret276; RV64I-NEXT: .LBB7_2:277; RV64I-NEXT: srl a0, a0, a2278; RV64I-NEXT: not a2, a2279; RV64I-NEXT: slli a3, a3, 1280; RV64I-NEXT: sll a2, a3, a2281; RV64I-NEXT: or a0, a0, a2282; RV64I-NEXT: ret283 %1 = ashr i128 %a, %b284 ret i128 %1285}286 287define i128 @shl128(i128 %a, i128 %b) nounwind {288; RV32I-LABEL: shl128:289; RV32I: # %bb.0:290; RV32I-NEXT: addi sp, sp, -32291; RV32I-NEXT: lw a2, 0(a2)292; RV32I-NEXT: lw a3, 0(a1)293; RV32I-NEXT: lw a4, 4(a1)294; RV32I-NEXT: lw a5, 8(a1)295; RV32I-NEXT: lw a1, 12(a1)296; RV32I-NEXT: sw zero, 0(sp)297; RV32I-NEXT: sw zero, 4(sp)298; RV32I-NEXT: sw zero, 8(sp)299; RV32I-NEXT: sw zero, 12(sp)300; RV32I-NEXT: addi a6, sp, 16301; RV32I-NEXT: sw a3, 16(sp)302; RV32I-NEXT: sw a4, 20(sp)303; RV32I-NEXT: sw a5, 24(sp)304; RV32I-NEXT: sw a1, 28(sp)305; RV32I-NEXT: srli a1, a2, 3306; RV32I-NEXT: andi a3, a2, 31307; RV32I-NEXT: andi a1, a1, 12308; RV32I-NEXT: sub a1, a6, a1309; RV32I-NEXT: lw a4, 0(a1)310; RV32I-NEXT: lw a5, 4(a1)311; RV32I-NEXT: lw a6, 8(a1)312; RV32I-NEXT: lw a1, 12(a1)313; RV32I-NEXT: xori a3, a3, 31314; RV32I-NEXT: sll a7, a5, a2315; RV32I-NEXT: srli t0, a4, 1316; RV32I-NEXT: sll a1, a1, a2317; RV32I-NEXT: sll a4, a4, a2318; RV32I-NEXT: sll a2, a6, a2319; RV32I-NEXT: srli a5, a5, 1320; RV32I-NEXT: srli a6, a6, 1321; RV32I-NEXT: srl t0, t0, a3322; RV32I-NEXT: srl a5, a5, a3323; RV32I-NEXT: srl a3, a6, a3324; RV32I-NEXT: or a6, a7, t0325; RV32I-NEXT: or a2, a2, a5326; RV32I-NEXT: or a1, a1, a3327; RV32I-NEXT: sw a4, 0(a0)328; RV32I-NEXT: sw a6, 4(a0)329; RV32I-NEXT: sw a2, 8(a0)330; RV32I-NEXT: sw a1, 12(a0)331; RV32I-NEXT: addi sp, sp, 32332; RV32I-NEXT: ret333;334; RV64I-LABEL: shl128:335; RV64I: # %bb.0:336; RV64I-NEXT: addi a4, a2, -64337; RV64I-NEXT: sll a3, a0, a2338; RV64I-NEXT: bltz a4, .LBB8_2339; RV64I-NEXT: # %bb.1:340; RV64I-NEXT: mv a1, a3341; RV64I-NEXT: j .LBB8_3342; RV64I-NEXT: .LBB8_2:343; RV64I-NEXT: sll a1, a1, a2344; RV64I-NEXT: not a2, a2345; RV64I-NEXT: srli a0, a0, 1346; RV64I-NEXT: srl a0, a0, a2347; RV64I-NEXT: or a1, a1, a0348; RV64I-NEXT: .LBB8_3:349; RV64I-NEXT: srai a0, a4, 63350; RV64I-NEXT: and a0, a0, a3351; RV64I-NEXT: ret352 %1 = shl i128 %a, %b353 ret i128 %1354}355 356define i64 @fshr64_minsize(i64 %a, i64 %b) minsize nounwind {357; RV32I-LABEL: fshr64_minsize:358; RV32I: # %bb.0:359; RV32I-NEXT: andi a5, a2, 32360; RV32I-NEXT: mv a3, a0361; RV32I-NEXT: beqz a5, .LBB9_2362; RV32I-NEXT: # %bb.1:363; RV32I-NEXT: mv a3, a1364; RV32I-NEXT: .LBB9_2:365; RV32I-NEXT: srl a4, a3, a2366; RV32I-NEXT: beqz a5, .LBB9_4367; RV32I-NEXT: # %bb.3:368; RV32I-NEXT: mv a1, a0369; RV32I-NEXT: .LBB9_4:370; RV32I-NEXT: slli a0, a1, 1371; RV32I-NEXT: not a5, a2372; RV32I-NEXT: srl a1, a1, a2373; RV32I-NEXT: slli a3, a3, 1374; RV32I-NEXT: sll a0, a0, a5375; RV32I-NEXT: sll a2, a3, a5376; RV32I-NEXT: or a0, a0, a4377; RV32I-NEXT: or a1, a2, a1378; RV32I-NEXT: ret379;380; RV64I-LABEL: fshr64_minsize:381; RV64I: # %bb.0:382; RV64I-NEXT: srl a2, a0, a1383; RV64I-NEXT: neg a1, a1384; RV64I-NEXT: sll a0, a0, a1385; RV64I-NEXT: or a0, a2, a0386; RV64I-NEXT: ret387 %res = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %b)388 ret i64 %res389}390 391define i128 @fshr128_minsize(i128 %a, i128 %b) minsize nounwind {392; RV32I-LABEL: fshr128_minsize:393; RV32I: # %bb.0:394; RV32I-NEXT: lw a2, 0(a2)395; RV32I-NEXT: lw t1, 0(a1)396; RV32I-NEXT: lw a7, 4(a1)397; RV32I-NEXT: lw a4, 8(a1)398; RV32I-NEXT: lw a1, 12(a1)399; RV32I-NEXT: andi t2, a2, 64400; RV32I-NEXT: mv t0, a7401; RV32I-NEXT: mv a3, t1402; RV32I-NEXT: beqz t2, .LBB10_2403; RV32I-NEXT: # %bb.1:404; RV32I-NEXT: mv t0, a1405; RV32I-NEXT: mv a3, a4406; RV32I-NEXT: .LBB10_2:407; RV32I-NEXT: andi a6, a2, 32408; RV32I-NEXT: mv a5, a3409; RV32I-NEXT: bnez a6, .LBB10_13410; RV32I-NEXT: # %bb.3:411; RV32I-NEXT: bnez t2, .LBB10_14412; RV32I-NEXT: .LBB10_4:413; RV32I-NEXT: beqz a6, .LBB10_6414; RV32I-NEXT: .LBB10_5:415; RV32I-NEXT: mv t0, a4416; RV32I-NEXT: .LBB10_6:417; RV32I-NEXT: slli t3, t0, 1418; RV32I-NEXT: not t1, a2419; RV32I-NEXT: beqz t2, .LBB10_8420; RV32I-NEXT: # %bb.7:421; RV32I-NEXT: mv a1, a7422; RV32I-NEXT: .LBB10_8:423; RV32I-NEXT: srl a7, a5, a2424; RV32I-NEXT: sll t2, t3, t1425; RV32I-NEXT: srl t0, t0, a2426; RV32I-NEXT: beqz a6, .LBB10_10427; RV32I-NEXT: # %bb.9:428; RV32I-NEXT: mv a4, a1429; RV32I-NEXT: .LBB10_10:430; RV32I-NEXT: or a7, t2, a7431; RV32I-NEXT: slli t2, a4, 1432; RV32I-NEXT: sll t2, t2, t1433; RV32I-NEXT: or t0, t2, t0434; RV32I-NEXT: srl a4, a4, a2435; RV32I-NEXT: beqz a6, .LBB10_12436; RV32I-NEXT: # %bb.11:437; RV32I-NEXT: mv a1, a3438; RV32I-NEXT: .LBB10_12:439; RV32I-NEXT: slli a3, a1, 1440; RV32I-NEXT: srl a1, a1, a2441; RV32I-NEXT: slli a5, a5, 1442; RV32I-NEXT: sll a2, a3, t1443; RV32I-NEXT: sll a3, a5, t1444; RV32I-NEXT: or a2, a2, a4445; RV32I-NEXT: or a1, a3, a1446; RV32I-NEXT: sw a7, 0(a0)447; RV32I-NEXT: sw t0, 4(a0)448; RV32I-NEXT: sw a2, 8(a0)449; RV32I-NEXT: sw a1, 12(a0)450; RV32I-NEXT: ret451; RV32I-NEXT: .LBB10_13:452; RV32I-NEXT: mv a5, t0453; RV32I-NEXT: beqz t2, .LBB10_4454; RV32I-NEXT: .LBB10_14:455; RV32I-NEXT: mv a4, t1456; RV32I-NEXT: bnez a6, .LBB10_5457; RV32I-NEXT: j .LBB10_6458;459; RV64I-LABEL: fshr128_minsize:460; RV64I: # %bb.0:461; RV64I-NEXT: andi a5, a2, 64462; RV64I-NEXT: mv a3, a0463; RV64I-NEXT: beqz a5, .LBB10_2464; RV64I-NEXT: # %bb.1:465; RV64I-NEXT: mv a3, a1466; RV64I-NEXT: .LBB10_2:467; RV64I-NEXT: srl a4, a3, a2468; RV64I-NEXT: beqz a5, .LBB10_4469; RV64I-NEXT: # %bb.3:470; RV64I-NEXT: mv a1, a0471; RV64I-NEXT: .LBB10_4:472; RV64I-NEXT: slli a0, a1, 1473; RV64I-NEXT: not a5, a2474; RV64I-NEXT: srl a1, a1, a2475; RV64I-NEXT: slli a3, a3, 1476; RV64I-NEXT: sll a0, a0, a5477; RV64I-NEXT: sll a2, a3, a5478; RV64I-NEXT: or a0, a0, a4479; RV64I-NEXT: or a1, a2, a1480; RV64I-NEXT: ret481 %res = tail call i128 @llvm.fshr.i128(i128 %a, i128 %a, i128 %b)482 ret i128 %res483}484 485define i64 @lshr64_shamt32(i64 %a, i32 signext %b) nounwind {486; RV32I-LABEL: lshr64_shamt32:487; RV32I: # %bb.0:488; RV32I-NEXT: addi a4, a2, -32489; RV32I-NEXT: srl a3, a1, a2490; RV32I-NEXT: bltz a4, .LBB11_2491; RV32I-NEXT: # %bb.1:492; RV32I-NEXT: mv a0, a3493; RV32I-NEXT: j .LBB11_3494; RV32I-NEXT: .LBB11_2:495; RV32I-NEXT: srl a0, a0, a2496; RV32I-NEXT: not a2, a2497; RV32I-NEXT: slli a1, a1, 1498; RV32I-NEXT: sll a1, a1, a2499; RV32I-NEXT: or a0, a0, a1500; RV32I-NEXT: .LBB11_3:501; RV32I-NEXT: srai a1, a4, 31502; RV32I-NEXT: and a1, a1, a3503; RV32I-NEXT: ret504;505; RV64I-LABEL: lshr64_shamt32:506; RV64I: # %bb.0:507; RV64I-NEXT: srl a0, a0, a1508; RV64I-NEXT: ret509 %zext = zext nneg i32 %b to i64510 %1 = lshr i64 %a, %zext511 ret i64 %1512}513 514define i64 @ashr64_shamt32(i64 %a, i32 signext %b) nounwind {515; RV32I-LABEL: ashr64_shamt32:516; RV32I: # %bb.0:517; RV32I-NEXT: mv a3, a1518; RV32I-NEXT: addi a4, a2, -32519; RV32I-NEXT: sra a1, a1, a2520; RV32I-NEXT: bltz a4, .LBB12_2521; RV32I-NEXT: # %bb.1:522; RV32I-NEXT: srai a3, a3, 31523; RV32I-NEXT: mv a0, a1524; RV32I-NEXT: mv a1, a3525; RV32I-NEXT: ret526; RV32I-NEXT: .LBB12_2:527; RV32I-NEXT: srl a0, a0, a2528; RV32I-NEXT: not a2, a2529; RV32I-NEXT: slli a3, a3, 1530; RV32I-NEXT: sll a2, a3, a2531; RV32I-NEXT: or a0, a0, a2532; RV32I-NEXT: ret533;534; RV64I-LABEL: ashr64_shamt32:535; RV64I: # %bb.0:536; RV64I-NEXT: sra a0, a0, a1537; RV64I-NEXT: ret538 %zext = zext nneg i32 %b to i64539 %1 = ashr i64 %a, %zext540 ret i64 %1541}542 543define i64 @shl64_shamt32(i64 %a, i32 signext %b) nounwind {544; RV32I-LABEL: shl64_shamt32:545; RV32I: # %bb.0:546; RV32I-NEXT: addi a4, a2, -32547; RV32I-NEXT: sll a3, a0, a2548; RV32I-NEXT: bltz a4, .LBB13_2549; RV32I-NEXT: # %bb.1:550; RV32I-NEXT: mv a1, a3551; RV32I-NEXT: j .LBB13_3552; RV32I-NEXT: .LBB13_2:553; RV32I-NEXT: sll a1, a1, a2554; RV32I-NEXT: not a2, a2555; RV32I-NEXT: srli a0, a0, 1556; RV32I-NEXT: srl a0, a0, a2557; RV32I-NEXT: or a1, a1, a0558; RV32I-NEXT: .LBB13_3:559; RV32I-NEXT: srai a0, a4, 31560; RV32I-NEXT: and a0, a0, a3561; RV32I-NEXT: ret562;563; RV64I-LABEL: shl64_shamt32:564; RV64I: # %bb.0:565; RV64I-NEXT: sll a0, a0, a1566; RV64I-NEXT: ret567 %zext = zext nneg i32 %b to i64568 %1 = shl i64 %a, %zext569 ret i64 %1570}571 572define i128 @lshr128_shamt32(i128 %a, i32 signext %b) nounwind {573; RV32I-LABEL: lshr128_shamt32:574; RV32I: # %bb.0:575; RV32I-NEXT: addi sp, sp, -32576; RV32I-NEXT: lw a3, 0(a1)577; RV32I-NEXT: lw a4, 4(a1)578; RV32I-NEXT: lw a5, 8(a1)579; RV32I-NEXT: lw a1, 12(a1)580; RV32I-NEXT: sw zero, 16(sp)581; RV32I-NEXT: sw zero, 20(sp)582; RV32I-NEXT: sw zero, 24(sp)583; RV32I-NEXT: sw zero, 28(sp)584; RV32I-NEXT: srli a6, a2, 3585; RV32I-NEXT: mv a7, sp586; RV32I-NEXT: andi t0, a2, 31587; RV32I-NEXT: andi a6, a6, 12588; RV32I-NEXT: xori t0, t0, 31589; RV32I-NEXT: add a6, a7, a6590; RV32I-NEXT: sw a3, 0(sp)591; RV32I-NEXT: sw a4, 4(sp)592; RV32I-NEXT: sw a5, 8(sp)593; RV32I-NEXT: sw a1, 12(sp)594; RV32I-NEXT: lw a1, 0(a6)595; RV32I-NEXT: lw a3, 4(a6)596; RV32I-NEXT: lw a4, 8(a6)597; RV32I-NEXT: lw a5, 12(a6)598; RV32I-NEXT: srl a1, a1, a2599; RV32I-NEXT: slli a6, a3, 1600; RV32I-NEXT: srl a3, a3, a2601; RV32I-NEXT: slli a7, a4, 1602; RV32I-NEXT: srl a4, a4, a2603; RV32I-NEXT: srl a2, a5, a2604; RV32I-NEXT: slli a5, a5, 1605; RV32I-NEXT: sll a6, a6, t0606; RV32I-NEXT: sll a7, a7, t0607; RV32I-NEXT: sll a5, a5, t0608; RV32I-NEXT: or a1, a1, a6609; RV32I-NEXT: or a3, a3, a7610; RV32I-NEXT: or a4, a4, a5611; RV32I-NEXT: sw a1, 0(a0)612; RV32I-NEXT: sw a3, 4(a0)613; RV32I-NEXT: sw a4, 8(a0)614; RV32I-NEXT: sw a2, 12(a0)615; RV32I-NEXT: addi sp, sp, 32616; RV32I-NEXT: ret617;618; RV64I-LABEL: lshr128_shamt32:619; RV64I: # %bb.0:620; RV64I-NEXT: addi a4, a2, -64621; RV64I-NEXT: srl a3, a1, a2622; RV64I-NEXT: bltz a4, .LBB14_2623; RV64I-NEXT: # %bb.1:624; RV64I-NEXT: mv a0, a3625; RV64I-NEXT: j .LBB14_3626; RV64I-NEXT: .LBB14_2:627; RV64I-NEXT: srl a0, a0, a2628; RV64I-NEXT: not a2, a2629; RV64I-NEXT: slli a1, a1, 1630; RV64I-NEXT: sll a1, a1, a2631; RV64I-NEXT: or a0, a0, a1632; RV64I-NEXT: .LBB14_3:633; RV64I-NEXT: srai a1, a4, 63634; RV64I-NEXT: and a1, a1, a3635; RV64I-NEXT: ret636 %zext = zext nneg i32 %b to i128637 %1 = lshr i128 %a, %zext638 ret i128 %1639}640 641define i128 @ashr128_shamt32(i128 %a, i32 signext %b) nounwind {642; RV32I-LABEL: ashr128_shamt32:643; RV32I: # %bb.0:644; RV32I-NEXT: addi sp, sp, -32645; RV32I-NEXT: lw a3, 0(a1)646; RV32I-NEXT: lw a4, 4(a1)647; RV32I-NEXT: lw a5, 8(a1)648; RV32I-NEXT: lw a1, 12(a1)649; RV32I-NEXT: srli a6, a2, 3650; RV32I-NEXT: mv a7, sp651; RV32I-NEXT: andi t0, a2, 31652; RV32I-NEXT: andi a6, a6, 12653; RV32I-NEXT: xori t0, t0, 31654; RV32I-NEXT: add a6, a7, a6655; RV32I-NEXT: sw a3, 0(sp)656; RV32I-NEXT: sw a4, 4(sp)657; RV32I-NEXT: sw a5, 8(sp)658; RV32I-NEXT: sw a1, 12(sp)659; RV32I-NEXT: srai a1, a1, 31660; RV32I-NEXT: sw a1, 16(sp)661; RV32I-NEXT: sw a1, 20(sp)662; RV32I-NEXT: sw a1, 24(sp)663; RV32I-NEXT: sw a1, 28(sp)664; RV32I-NEXT: lw a1, 0(a6)665; RV32I-NEXT: lw a3, 4(a6)666; RV32I-NEXT: lw a4, 8(a6)667; RV32I-NEXT: lw a5, 12(a6)668; RV32I-NEXT: srl a1, a1, a2669; RV32I-NEXT: slli a6, a3, 1670; RV32I-NEXT: srl a3, a3, a2671; RV32I-NEXT: slli a7, a4, 1672; RV32I-NEXT: srl a4, a4, a2673; RV32I-NEXT: sra a2, a5, a2674; RV32I-NEXT: slli a5, a5, 1675; RV32I-NEXT: sll a6, a6, t0676; RV32I-NEXT: sll a7, a7, t0677; RV32I-NEXT: sll a5, a5, t0678; RV32I-NEXT: or a1, a1, a6679; RV32I-NEXT: or a3, a3, a7680; RV32I-NEXT: or a4, a4, a5681; RV32I-NEXT: sw a1, 0(a0)682; RV32I-NEXT: sw a3, 4(a0)683; RV32I-NEXT: sw a4, 8(a0)684; RV32I-NEXT: sw a2, 12(a0)685; RV32I-NEXT: addi sp, sp, 32686; RV32I-NEXT: ret687;688; RV64I-LABEL: ashr128_shamt32:689; RV64I: # %bb.0:690; RV64I-NEXT: mv a3, a1691; RV64I-NEXT: addi a4, a2, -64692; RV64I-NEXT: sra a1, a1, a2693; RV64I-NEXT: bltz a4, .LBB15_2694; RV64I-NEXT: # %bb.1:695; RV64I-NEXT: srai a3, a3, 63696; RV64I-NEXT: mv a0, a1697; RV64I-NEXT: mv a1, a3698; RV64I-NEXT: ret699; RV64I-NEXT: .LBB15_2:700; RV64I-NEXT: srl a0, a0, a2701; RV64I-NEXT: not a2, a2702; RV64I-NEXT: slli a3, a3, 1703; RV64I-NEXT: sll a2, a3, a2704; RV64I-NEXT: or a0, a0, a2705; RV64I-NEXT: ret706 %zext = zext nneg i32 %b to i128707 %1 = ashr i128 %a, %zext708 ret i128 %1709}710 711define i128 @shl128_shamt32(i128 %a, i32 signext %b) nounwind {712; RV32I-LABEL: shl128_shamt32:713; RV32I: # %bb.0:714; RV32I-NEXT: addi sp, sp, -32715; RV32I-NEXT: lw a3, 0(a1)716; RV32I-NEXT: lw a4, 4(a1)717; RV32I-NEXT: lw a5, 8(a1)718; RV32I-NEXT: lw a1, 12(a1)719; RV32I-NEXT: sw zero, 0(sp)720; RV32I-NEXT: sw zero, 4(sp)721; RV32I-NEXT: sw zero, 8(sp)722; RV32I-NEXT: sw zero, 12(sp)723; RV32I-NEXT: srli a6, a2, 3724; RV32I-NEXT: addi a7, sp, 16725; RV32I-NEXT: andi t0, a2, 31726; RV32I-NEXT: andi a6, a6, 12727; RV32I-NEXT: sub a6, a7, a6728; RV32I-NEXT: sw a3, 16(sp)729; RV32I-NEXT: sw a4, 20(sp)730; RV32I-NEXT: sw a5, 24(sp)731; RV32I-NEXT: sw a1, 28(sp)732; RV32I-NEXT: lw a1, 0(a6)733; RV32I-NEXT: lw a3, 4(a6)734; RV32I-NEXT: lw a4, 8(a6)735; RV32I-NEXT: lw a5, 12(a6)736; RV32I-NEXT: xori a6, t0, 31737; RV32I-NEXT: sll a7, a3, a2738; RV32I-NEXT: srli t0, a1, 1739; RV32I-NEXT: sll a5, a5, a2740; RV32I-NEXT: sll a1, a1, a2741; RV32I-NEXT: sll a2, a4, a2742; RV32I-NEXT: srli a3, a3, 1743; RV32I-NEXT: srli a4, a4, 1744; RV32I-NEXT: srl t0, t0, a6745; RV32I-NEXT: srl a3, a3, a6746; RV32I-NEXT: srl a4, a4, a6747; RV32I-NEXT: or a6, a7, t0748; RV32I-NEXT: or a2, a2, a3749; RV32I-NEXT: or a4, a5, a4750; RV32I-NEXT: sw a1, 0(a0)751; RV32I-NEXT: sw a6, 4(a0)752; RV32I-NEXT: sw a2, 8(a0)753; RV32I-NEXT: sw a4, 12(a0)754; RV32I-NEXT: addi sp, sp, 32755; RV32I-NEXT: ret756;757; RV64I-LABEL: shl128_shamt32:758; RV64I: # %bb.0:759; RV64I-NEXT: addi a4, a2, -64760; RV64I-NEXT: sll a3, a0, a2761; RV64I-NEXT: bltz a4, .LBB16_2762; RV64I-NEXT: # %bb.1:763; RV64I-NEXT: mv a1, a3764; RV64I-NEXT: j .LBB16_3765; RV64I-NEXT: .LBB16_2:766; RV64I-NEXT: sll a1, a1, a2767; RV64I-NEXT: not a2, a2768; RV64I-NEXT: srli a0, a0, 1769; RV64I-NEXT: srl a0, a0, a2770; RV64I-NEXT: or a1, a1, a0771; RV64I-NEXT: .LBB16_3:772; RV64I-NEXT: srai a0, a4, 63773; RV64I-NEXT: and a0, a0, a3774; RV64I-NEXT: ret775 %zext = zext nneg i32 %b to i128776 %1 = shl i128 %a, %zext777 ret i128 %1778}779 780; Do some arithmetic on the i32 shift amount before the zext nneg. This781; arithmetic will be promoted using a W instruction RV64. Make sure we can use782; this to avoid an unncessary zext of the shift amount.783define i128 @shl128_shamt32_arith(i128 %a, i32 signext %b) nounwind {784; RV32I-LABEL: shl128_shamt32_arith:785; RV32I: # %bb.0:786; RV32I-NEXT: addi sp, sp, -32787; RV32I-NEXT: lw a3, 0(a1)788; RV32I-NEXT: lw a4, 4(a1)789; RV32I-NEXT: lw a5, 8(a1)790; RV32I-NEXT: lw a1, 12(a1)791; RV32I-NEXT: addi a2, a2, 1792; RV32I-NEXT: sw zero, 0(sp)793; RV32I-NEXT: sw zero, 4(sp)794; RV32I-NEXT: sw zero, 8(sp)795; RV32I-NEXT: sw zero, 12(sp)796; RV32I-NEXT: addi a6, sp, 16797; RV32I-NEXT: srli a7, a2, 3798; RV32I-NEXT: andi t0, a2, 31799; RV32I-NEXT: andi a7, a7, 12800; RV32I-NEXT: sub a6, a6, a7801; RV32I-NEXT: sw a3, 16(sp)802; RV32I-NEXT: sw a4, 20(sp)803; RV32I-NEXT: sw a5, 24(sp)804; RV32I-NEXT: sw a1, 28(sp)805; RV32I-NEXT: lw a1, 0(a6)806; RV32I-NEXT: lw a3, 4(a6)807; RV32I-NEXT: lw a4, 8(a6)808; RV32I-NEXT: lw a5, 12(a6)809; RV32I-NEXT: xori a6, t0, 31810; RV32I-NEXT: sll a7, a3, a2811; RV32I-NEXT: srli t0, a1, 1812; RV32I-NEXT: sll a5, a5, a2813; RV32I-NEXT: sll a1, a1, a2814; RV32I-NEXT: sll a2, a4, a2815; RV32I-NEXT: srli a3, a3, 1816; RV32I-NEXT: srli a4, a4, 1817; RV32I-NEXT: srl t0, t0, a6818; RV32I-NEXT: srl a3, a3, a6819; RV32I-NEXT: srl a4, a4, a6820; RV32I-NEXT: or a6, a7, t0821; RV32I-NEXT: or a2, a2, a3822; RV32I-NEXT: or a4, a5, a4823; RV32I-NEXT: sw a1, 0(a0)824; RV32I-NEXT: sw a6, 4(a0)825; RV32I-NEXT: sw a2, 8(a0)826; RV32I-NEXT: sw a4, 12(a0)827; RV32I-NEXT: addi sp, sp, 32828; RV32I-NEXT: ret829;830; RV64I-LABEL: shl128_shamt32_arith:831; RV64I: # %bb.0:832; RV64I-NEXT: addiw a4, a2, 1833; RV64I-NEXT: addi a3, a4, -64834; RV64I-NEXT: sll a2, a0, a4835; RV64I-NEXT: bltz a3, .LBB17_2836; RV64I-NEXT: # %bb.1:837; RV64I-NEXT: mv a1, a2838; RV64I-NEXT: j .LBB17_3839; RV64I-NEXT: .LBB17_2:840; RV64I-NEXT: sll a1, a1, a4841; RV64I-NEXT: srli a0, a0, 1842; RV64I-NEXT: not a4, a4843; RV64I-NEXT: srl a0, a0, a4844; RV64I-NEXT: or a1, a1, a0845; RV64I-NEXT: .LBB17_3:846; RV64I-NEXT: srai a0, a3, 63847; RV64I-NEXT: and a0, a0, a2848; RV64I-NEXT: ret849 %c = add i32 %b, 1850 %zext = zext nneg i32 %c to i128851 %1 = shl i128 %a, %zext852 ret i128 %1853}854