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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV32I4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefix=RV64I6 7define void @sext_shl_trunc_same_size(i16 %x, i32 %y, ptr %res) {8; RV32I-LABEL: sext_shl_trunc_same_size:9; RV32I: # %bb.0:10; RV32I-NEXT: sll a0, a0, a111; RV32I-NEXT: sh a0, 0(a2)12; RV32I-NEXT: ret13;14; RV64I-LABEL: sext_shl_trunc_same_size:15; RV64I: # %bb.0:16; RV64I-NEXT: sllw a0, a0, a117; RV64I-NEXT: sh a0, 0(a2)18; RV64I-NEXT: ret19 %conv = sext i16 %x to i3220 %shl = shl i32 %conv, %y21 %t = trunc i32 %shl to i1622 store i16 %t, ptr %res23 ret void24}25 26define void @zext_shl_trunc_same_size(i16 %x, i32 %y, ptr %res) {27; RV32I-LABEL: zext_shl_trunc_same_size:28; RV32I: # %bb.0:29; RV32I-NEXT: sll a0, a0, a130; RV32I-NEXT: sh a0, 0(a2)31; RV32I-NEXT: ret32;33; RV64I-LABEL: zext_shl_trunc_same_size:34; RV64I: # %bb.0:35; RV64I-NEXT: sllw a0, a0, a136; RV64I-NEXT: sh a0, 0(a2)37; RV64I-NEXT: ret38 %conv = zext i16 %x to i3239 %shl = shl i32 %conv, %y40 %t = trunc i32 %shl to i1641 store i16 %t, ptr %res42 ret void43}44 45define void @sext_shl_trunc_smaller(i16 %x, i32 %y, ptr %res) {46; RV32I-LABEL: sext_shl_trunc_smaller:47; RV32I: # %bb.0:48; RV32I-NEXT: sll a0, a0, a149; RV32I-NEXT: sb a0, 0(a2)50; RV32I-NEXT: ret51;52; RV64I-LABEL: sext_shl_trunc_smaller:53; RV64I: # %bb.0:54; RV64I-NEXT: sllw a0, a0, a155; RV64I-NEXT: sb a0, 0(a2)56; RV64I-NEXT: ret57 %conv = sext i16 %x to i3258 %shl = shl i32 %conv, %y59 %t = trunc i32 %shl to i860 store i8 %t, ptr %res61 ret void62}63 64define void @zext_shl_trunc_smaller(i16 %x, i32 %y, ptr %res) {65; RV32I-LABEL: zext_shl_trunc_smaller:66; RV32I: # %bb.0:67; RV32I-NEXT: sll a0, a0, a168; RV32I-NEXT: sb a0, 0(a2)69; RV32I-NEXT: ret70;71; RV64I-LABEL: zext_shl_trunc_smaller:72; RV64I: # %bb.0:73; RV64I-NEXT: sllw a0, a0, a174; RV64I-NEXT: sb a0, 0(a2)75; RV64I-NEXT: ret76 %conv = zext i16 %x to i3277 %shl = shl i32 %conv, %y78 %t = trunc i32 %shl to i879 store i8 %t, ptr %res80 ret void81}82 83; negative test - demanding 1 high-bit too many to change the extend84 85define signext i17 @sext_shl_trunc_larger(i16 %x, i32 %y) {86; RV32I-LABEL: sext_shl_trunc_larger:87; RV32I: # %bb.0:88; RV32I-NEXT: slli a0, a0, 1689; RV32I-NEXT: srai a0, a0, 1690; RV32I-NEXT: sll a0, a0, a191; RV32I-NEXT: slli a0, a0, 1592; RV32I-NEXT: srai a0, a0, 1593; RV32I-NEXT: ret94;95; RV64I-LABEL: sext_shl_trunc_larger:96; RV64I: # %bb.0:97; RV64I-NEXT: slli a0, a0, 4898; RV64I-NEXT: srai a0, a0, 4899; RV64I-NEXT: sllw a0, a0, a1100; RV64I-NEXT: slli a0, a0, 47101; RV64I-NEXT: srai a0, a0, 47102; RV64I-NEXT: ret103 %conv = sext i16 %x to i32104 %shl = shl i32 %conv, %y105 %t = trunc i32 %shl to i17106 ret i17 %t107}108 109; negative test - demanding 1 high-bit too many to change the extend110 111define zeroext i17 @zext_shl_trunc_larger(i16 %x, i32 %y) {112; RV32I-LABEL: zext_shl_trunc_larger:113; RV32I: # %bb.0:114; RV32I-NEXT: slli a0, a0, 16115; RV32I-NEXT: srli a0, a0, 16116; RV32I-NEXT: sll a0, a0, a1117; RV32I-NEXT: slli a0, a0, 15118; RV32I-NEXT: srli a0, a0, 15119; RV32I-NEXT: ret120;121; RV64I-LABEL: zext_shl_trunc_larger:122; RV64I: # %bb.0:123; RV64I-NEXT: slli a0, a0, 48124; RV64I-NEXT: srli a0, a0, 48125; RV64I-NEXT: sllw a0, a0, a1126; RV64I-NEXT: slli a0, a0, 47127; RV64I-NEXT: srli a0, a0, 47128; RV64I-NEXT: ret129 %conv = zext i16 %x to i32130 %shl = shl i32 %conv, %y131 %t = trunc i32 %shl to i17132 ret i17 %t133}134 135define i32 @sext_shl_mask(i16 %x, i32 %y) {136; RV32I-LABEL: sext_shl_mask:137; RV32I: # %bb.0:138; RV32I-NEXT: sll a0, a0, a1139; RV32I-NEXT: slli a0, a0, 16140; RV32I-NEXT: srli a0, a0, 16141; RV32I-NEXT: ret142;143; RV64I-LABEL: sext_shl_mask:144; RV64I: # %bb.0:145; RV64I-NEXT: sllw a0, a0, a1146; RV64I-NEXT: slli a0, a0, 48147; RV64I-NEXT: srli a0, a0, 48148; RV64I-NEXT: ret149 %conv = sext i16 %x to i32150 %shl = shl i32 %conv, %y151 %t = and i32 %shl, 65535152 ret i32 %t153}154 155define i32 @zext_shl_mask(i16 %x, i32 %y) {156; RV32I-LABEL: zext_shl_mask:157; RV32I: # %bb.0:158; RV32I-NEXT: sll a0, a0, a1159; RV32I-NEXT: slli a0, a0, 16160; RV32I-NEXT: srli a0, a0, 16161; RV32I-NEXT: ret162;163; RV64I-LABEL: zext_shl_mask:164; RV64I: # %bb.0:165; RV64I-NEXT: sllw a0, a0, a1166; RV64I-NEXT: slli a0, a0, 48167; RV64I-NEXT: srli a0, a0, 48168; RV64I-NEXT: ret169 %conv = zext i16 %x to i32170 %shl = shl i32 %conv, %y171 %t = and i32 %shl, 65535172 ret i32 %t173}174 175; negative test - demanding a bit that could change with sext176 177define i32 @sext_shl_mask_higher(i16 %x, i32 %y) {178; RV32I-LABEL: sext_shl_mask_higher:179; RV32I: # %bb.0:180; RV32I-NEXT: slli a0, a0, 16181; RV32I-NEXT: srai a0, a0, 16182; RV32I-NEXT: sll a0, a0, a1183; RV32I-NEXT: lui a1, 16184; RV32I-NEXT: and a0, a0, a1185; RV32I-NEXT: ret186;187; RV64I-LABEL: sext_shl_mask_higher:188; RV64I: # %bb.0:189; RV64I-NEXT: slli a0, a0, 48190; RV64I-NEXT: srai a0, a0, 48191; RV64I-NEXT: sllw a0, a0, a1192; RV64I-NEXT: lui a1, 16193; RV64I-NEXT: and a0, a0, a1194; RV64I-NEXT: ret195 %conv = sext i16 %x to i32196 %shl = shl i32 %conv, %y197 %t = and i32 %shl, 65536198 ret i32 %t199}200 201; negative test - demanding a bit that could change with zext202 203define i32 @zext_shl_mask_higher(i16 %x, i32 %y) {204; RV32I-LABEL: zext_shl_mask_higher:205; RV32I: # %bb.0:206; RV32I-NEXT: slli a0, a0, 16207; RV32I-NEXT: srli a0, a0, 16208; RV32I-NEXT: sll a0, a0, a1209; RV32I-NEXT: lui a1, 16210; RV32I-NEXT: and a0, a0, a1211; RV32I-NEXT: ret212;213; RV64I-LABEL: zext_shl_mask_higher:214; RV64I: # %bb.0:215; RV64I-NEXT: slli a0, a0, 48216; RV64I-NEXT: srli a0, a0, 48217; RV64I-NEXT: sllw a0, a0, a1218; RV64I-NEXT: lui a1, 16219; RV64I-NEXT: and a0, a0, a1220; RV64I-NEXT: ret221 %conv = zext i16 %x to i32222 %shl = shl i32 %conv, %y223 %t = and i32 %shl, 65536224 ret i32 %t225}226 227; May need some, but not all of the bits set by the 'or'.228 229define i32 @set_shl_mask(i32 %x, i32 %y) {230; RV32I-LABEL: set_shl_mask:231; RV32I: # %bb.0:232; RV32I-NEXT: lui a2, 16233; RV32I-NEXT: addi a3, a2, 1234; RV32I-NEXT: or a0, a0, a3235; RV32I-NEXT: sll a0, a0, a1236; RV32I-NEXT: and a0, a0, a2237; RV32I-NEXT: ret238;239; RV64I-LABEL: set_shl_mask:240; RV64I: # %bb.0:241; RV64I-NEXT: lui a2, 16242; RV64I-NEXT: addi a3, a2, 1243; RV64I-NEXT: or a0, a0, a3244; RV64I-NEXT: sllw a0, a0, a1245; RV64I-NEXT: and a0, a0, a2246; RV64I-NEXT: ret247 %z = or i32 %x, 196609248 %s = shl i32 %z, %y249 %r = and i32 %s, 65536250 ret i32 %r251}252