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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2 3; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \4; RUN: | FileCheck -check-prefix=RV32I %s5; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \6; RUN: | FileCheck -check-prefix=RV64I %s7 8;; Test that (add (shl x, c0), c1) can be transformed to9;; (add (shl (add x, c1>>c0), c0), c1-(c1>>c0<<c0)) or10;; (shl (add x, c1>>c0), c0) if profitable.11 12define i32 @shl5_add1184_a(i32 %x) {13; RV32I-LABEL: shl5_add1184_a:14; RV32I: # %bb.0:15; RV32I-NEXT: slli a0, a0, 516; RV32I-NEXT: addi a0, a0, 118417; RV32I-NEXT: ret18;19; RV64I-LABEL: shl5_add1184_a:20; RV64I: # %bb.0:21; RV64I-NEXT: slli a0, a0, 522; RV64I-NEXT: addiw a0, a0, 118423; RV64I-NEXT: ret24 %tmp0 = shl i32 %x, 525 %tmp1 = add i32 %tmp0, 118426 ret i32 %tmp127}28 29define signext i32 @shl5_add1184_b(i32 signext %x) {30; RV32I-LABEL: shl5_add1184_b:31; RV32I: # %bb.0:32; RV32I-NEXT: slli a0, a0, 533; RV32I-NEXT: addi a0, a0, 118434; RV32I-NEXT: ret35;36; RV64I-LABEL: shl5_add1184_b:37; RV64I: # %bb.0:38; RV64I-NEXT: slli a0, a0, 539; RV64I-NEXT: addiw a0, a0, 118440; RV64I-NEXT: ret41 %tmp0 = shl i32 %x, 542 %tmp1 = add i32 %tmp0, 118443 ret i32 %tmp144}45 46define i64 @shl5_add1184_c(i64 %x) {47; RV32I-LABEL: shl5_add1184_c:48; RV32I: # %bb.0:49; RV32I-NEXT: srli a2, a0, 2750; RV32I-NEXT: slli a1, a1, 551; RV32I-NEXT: slli a3, a0, 552; RV32I-NEXT: or a1, a1, a253; RV32I-NEXT: addi a0, a3, 118454; RV32I-NEXT: sltu a2, a0, a355; RV32I-NEXT: add a1, a1, a256; RV32I-NEXT: ret57;58; RV64I-LABEL: shl5_add1184_c:59; RV64I: # %bb.0:60; RV64I-NEXT: slli a0, a0, 561; RV64I-NEXT: addi a0, a0, 118462; RV64I-NEXT: ret63 %tmp0 = shl i64 %x, 564 %tmp1 = add i64 %tmp0, 118465 ret i64 %tmp166}67 68define i32 @shl5_add101024_a(i32 %x) {69; RV32I-LABEL: shl5_add101024_a:70; RV32I: # %bb.0:71; RV32I-NEXT: slli a0, a0, 572; RV32I-NEXT: lui a1, 2573; RV32I-NEXT: addi a1, a1, -137674; RV32I-NEXT: add a0, a0, a175; RV32I-NEXT: ret76;77; RV64I-LABEL: shl5_add101024_a:78; RV64I: # %bb.0:79; RV64I-NEXT: slli a0, a0, 580; RV64I-NEXT: lui a1, 2581; RV64I-NEXT: addi a1, a1, -137682; RV64I-NEXT: addw a0, a0, a183; RV64I-NEXT: ret84 %tmp0 = shl i32 %x, 585 %tmp1 = add i32 %tmp0, 10102486 ret i32 %tmp187}88 89define signext i32 @shl5_add101024_b(i32 signext %x) {90; RV32I-LABEL: shl5_add101024_b:91; RV32I: # %bb.0:92; RV32I-NEXT: slli a0, a0, 593; RV32I-NEXT: lui a1, 2594; RV32I-NEXT: addi a1, a1, -137695; RV32I-NEXT: add a0, a0, a196; RV32I-NEXT: ret97;98; RV64I-LABEL: shl5_add101024_b:99; RV64I: # %bb.0:100; RV64I-NEXT: slli a0, a0, 5101; RV64I-NEXT: lui a1, 25102; RV64I-NEXT: addi a1, a1, -1376103; RV64I-NEXT: addw a0, a0, a1104; RV64I-NEXT: ret105 %tmp0 = shl i32 %x, 5106 %tmp1 = add i32 %tmp0, 101024107 ret i32 %tmp1108}109 110define i64 @shl5_add101024_c(i64 %x) {111; RV32I-LABEL: shl5_add101024_c:112; RV32I: # %bb.0:113; RV32I-NEXT: srli a2, a0, 27114; RV32I-NEXT: slli a1, a1, 5115; RV32I-NEXT: slli a3, a0, 5116; RV32I-NEXT: or a1, a1, a2117; RV32I-NEXT: lui a0, 25118; RV32I-NEXT: addi a0, a0, -1376119; RV32I-NEXT: add a0, a3, a0120; RV32I-NEXT: sltu a2, a0, a3121; RV32I-NEXT: add a1, a1, a2122; RV32I-NEXT: ret123;124; RV64I-LABEL: shl5_add101024_c:125; RV64I: # %bb.0:126; RV64I-NEXT: slli a0, a0, 5127; RV64I-NEXT: lui a1, 25128; RV64I-NEXT: addi a1, a1, -1376129; RV64I-NEXT: add a0, a0, a1130; RV64I-NEXT: ret131 %tmp0 = shl i64 %x, 5132 %tmp1 = add i64 %tmp0, 101024133 ret i64 %tmp1134}135 136define i32 @shl5_add47968_a(i32 %x) {137; RV32I-LABEL: shl5_add47968_a:138; RV32I: # %bb.0:139; RV32I-NEXT: slli a0, a0, 5140; RV32I-NEXT: lui a1, 12141; RV32I-NEXT: addi a1, a1, -1184142; RV32I-NEXT: add a0, a0, a1143; RV32I-NEXT: ret144;145; RV64I-LABEL: shl5_add47968_a:146; RV64I: # %bb.0:147; RV64I-NEXT: slli a0, a0, 5148; RV64I-NEXT: lui a1, 12149; RV64I-NEXT: addi a1, a1, -1184150; RV64I-NEXT: addw a0, a0, a1151; RV64I-NEXT: ret152 %tmp0 = shl i32 %x, 5153 %tmp1 = add i32 %tmp0, 47968154 ret i32 %tmp1155}156 157define signext i32 @shl5_add47968_b(i32 signext %x) {158; RV32I-LABEL: shl5_add47968_b:159; RV32I: # %bb.0:160; RV32I-NEXT: slli a0, a0, 5161; RV32I-NEXT: lui a1, 12162; RV32I-NEXT: addi a1, a1, -1184163; RV32I-NEXT: add a0, a0, a1164; RV32I-NEXT: ret165;166; RV64I-LABEL: shl5_add47968_b:167; RV64I: # %bb.0:168; RV64I-NEXT: slli a0, a0, 5169; RV64I-NEXT: lui a1, 12170; RV64I-NEXT: addi a1, a1, -1184171; RV64I-NEXT: addw a0, a0, a1172; RV64I-NEXT: ret173 %tmp0 = shl i32 %x, 5174 %tmp1 = add i32 %tmp0, 47968175 ret i32 %tmp1176}177 178define i64 @shl5_add47968_c(i64 %x) {179; RV32I-LABEL: shl5_add47968_c:180; RV32I: # %bb.0:181; RV32I-NEXT: srli a2, a0, 27182; RV32I-NEXT: slli a1, a1, 5183; RV32I-NEXT: slli a3, a0, 5184; RV32I-NEXT: or a1, a1, a2185; RV32I-NEXT: lui a0, 12186; RV32I-NEXT: addi a0, a0, -1184187; RV32I-NEXT: add a0, a3, a0188; RV32I-NEXT: sltu a2, a0, a3189; RV32I-NEXT: add a1, a1, a2190; RV32I-NEXT: ret191;192; RV64I-LABEL: shl5_add47968_c:193; RV64I: # %bb.0:194; RV64I-NEXT: slli a0, a0, 5195; RV64I-NEXT: lui a1, 12196; RV64I-NEXT: addi a1, a1, -1184197; RV64I-NEXT: add a0, a0, a1198; RV64I-NEXT: ret199 %tmp0 = shl i64 %x, 5200 %tmp1 = add i64 %tmp0, 47968201 ret i64 %tmp1202}203 204define i32 @shl5_add47969_a(i32 %x) {205; RV32I-LABEL: shl5_add47969_a:206; RV32I: # %bb.0:207; RV32I-NEXT: slli a0, a0, 5208; RV32I-NEXT: lui a1, 12209; RV32I-NEXT: addi a1, a1, -1183210; RV32I-NEXT: add a0, a0, a1211; RV32I-NEXT: ret212;213; RV64I-LABEL: shl5_add47969_a:214; RV64I: # %bb.0:215; RV64I-NEXT: slli a0, a0, 5216; RV64I-NEXT: lui a1, 12217; RV64I-NEXT: addi a1, a1, -1183218; RV64I-NEXT: addw a0, a0, a1219; RV64I-NEXT: ret220 %tmp0 = shl i32 %x, 5221 %tmp1 = add i32 %tmp0, 47969222 ret i32 %tmp1223}224 225define signext i32 @shl5_add47969_b(i32 signext %x) {226; RV32I-LABEL: shl5_add47969_b:227; RV32I: # %bb.0:228; RV32I-NEXT: slli a0, a0, 5229; RV32I-NEXT: lui a1, 12230; RV32I-NEXT: addi a1, a1, -1183231; RV32I-NEXT: add a0, a0, a1232; RV32I-NEXT: ret233;234; RV64I-LABEL: shl5_add47969_b:235; RV64I: # %bb.0:236; RV64I-NEXT: slli a0, a0, 5237; RV64I-NEXT: lui a1, 12238; RV64I-NEXT: addi a1, a1, -1183239; RV64I-NEXT: addw a0, a0, a1240; RV64I-NEXT: ret241 %tmp0 = shl i32 %x, 5242 %tmp1 = add i32 %tmp0, 47969243 ret i32 %tmp1244}245 246define i64 @shl5_add47969_c(i64 %x) {247; RV32I-LABEL: shl5_add47969_c:248; RV32I: # %bb.0:249; RV32I-NEXT: srli a2, a0, 27250; RV32I-NEXT: slli a1, a1, 5251; RV32I-NEXT: slli a3, a0, 5252; RV32I-NEXT: or a1, a1, a2253; RV32I-NEXT: lui a0, 12254; RV32I-NEXT: addi a0, a0, -1183255; RV32I-NEXT: add a0, a3, a0256; RV32I-NEXT: sltu a2, a0, a3257; RV32I-NEXT: add a1, a1, a2258; RV32I-NEXT: ret259;260; RV64I-LABEL: shl5_add47969_c:261; RV64I: # %bb.0:262; RV64I-NEXT: slli a0, a0, 5263; RV64I-NEXT: lui a1, 12264; RV64I-NEXT: addi a1, a1, -1183265; RV64I-NEXT: add a0, a0, a1266; RV64I-NEXT: ret267 %tmp0 = shl i64 %x, 5268 %tmp1 = add i64 %tmp0, 47969269 ret i64 %tmp1270}271 272define i32 @shl5_sub47968_a(i32 %x) {273; RV32I-LABEL: shl5_sub47968_a:274; RV32I: # %bb.0:275; RV32I-NEXT: slli a0, a0, 5276; RV32I-NEXT: lui a1, 1048564277; RV32I-NEXT: addi a1, a1, 1184278; RV32I-NEXT: add a0, a0, a1279; RV32I-NEXT: ret280;281; RV64I-LABEL: shl5_sub47968_a:282; RV64I: # %bb.0:283; RV64I-NEXT: slli a0, a0, 5284; RV64I-NEXT: lui a1, 1048564285; RV64I-NEXT: addi a1, a1, 1184286; RV64I-NEXT: addw a0, a0, a1287; RV64I-NEXT: ret288 %tmp0 = shl i32 %x, 5289 %tmp1 = add i32 %tmp0, -47968290 ret i32 %tmp1291}292 293define signext i32 @shl5_sub47968_b(i32 signext %x) {294; RV32I-LABEL: shl5_sub47968_b:295; RV32I: # %bb.0:296; RV32I-NEXT: slli a0, a0, 5297; RV32I-NEXT: lui a1, 1048564298; RV32I-NEXT: addi a1, a1, 1184299; RV32I-NEXT: add a0, a0, a1300; RV32I-NEXT: ret301;302; RV64I-LABEL: shl5_sub47968_b:303; RV64I: # %bb.0:304; RV64I-NEXT: slli a0, a0, 5305; RV64I-NEXT: lui a1, 1048564306; RV64I-NEXT: addi a1, a1, 1184307; RV64I-NEXT: addw a0, a0, a1308; RV64I-NEXT: ret309 %tmp0 = shl i32 %x, 5310 %tmp1 = add i32 %tmp0, -47968311 ret i32 %tmp1312}313 314define i64 @shl5_sub47968_c(i64 %x) {315; RV32I-LABEL: shl5_sub47968_c:316; RV32I: # %bb.0:317; RV32I-NEXT: srli a2, a0, 27318; RV32I-NEXT: slli a1, a1, 5319; RV32I-NEXT: slli a3, a0, 5320; RV32I-NEXT: or a1, a1, a2321; RV32I-NEXT: lui a0, 1048564322; RV32I-NEXT: addi a0, a0, 1184323; RV32I-NEXT: add a0, a3, a0324; RV32I-NEXT: sltu a2, a0, a3325; RV32I-NEXT: add a1, a1, a2326; RV32I-NEXT: addi a1, a1, -1327; RV32I-NEXT: ret328;329; RV64I-LABEL: shl5_sub47968_c:330; RV64I: # %bb.0:331; RV64I-NEXT: slli a0, a0, 5332; RV64I-NEXT: lui a1, 1048564333; RV64I-NEXT: addi a1, a1, 1184334; RV64I-NEXT: add a0, a0, a1335; RV64I-NEXT: ret336 %tmp0 = shl i64 %x, 5337 %tmp1 = add i64 %tmp0, -47968338 ret i64 %tmp1339}340 341define i32 @shl5_sub47969_a(i32 %x) {342; RV32I-LABEL: shl5_sub47969_a:343; RV32I: # %bb.0:344; RV32I-NEXT: slli a0, a0, 5345; RV32I-NEXT: lui a1, 1048564346; RV32I-NEXT: addi a1, a1, 1183347; RV32I-NEXT: add a0, a0, a1348; RV32I-NEXT: ret349;350; RV64I-LABEL: shl5_sub47969_a:351; RV64I: # %bb.0:352; RV64I-NEXT: slli a0, a0, 5353; RV64I-NEXT: lui a1, 1048564354; RV64I-NEXT: addi a1, a1, 1183355; RV64I-NEXT: addw a0, a0, a1356; RV64I-NEXT: ret357 %tmp0 = shl i32 %x, 5358 %tmp1 = add i32 %tmp0, -47969359 ret i32 %tmp1360}361 362define signext i32 @shl5_sub47969_b(i32 signext %x) {363; RV32I-LABEL: shl5_sub47969_b:364; RV32I: # %bb.0:365; RV32I-NEXT: slli a0, a0, 5366; RV32I-NEXT: lui a1, 1048564367; RV32I-NEXT: addi a1, a1, 1183368; RV32I-NEXT: add a0, a0, a1369; RV32I-NEXT: ret370;371; RV64I-LABEL: shl5_sub47969_b:372; RV64I: # %bb.0:373; RV64I-NEXT: slli a0, a0, 5374; RV64I-NEXT: lui a1, 1048564375; RV64I-NEXT: addi a1, a1, 1183376; RV64I-NEXT: addw a0, a0, a1377; RV64I-NEXT: ret378 %tmp0 = shl i32 %x, 5379 %tmp1 = add i32 %tmp0, -47969380 ret i32 %tmp1381}382 383define i64 @shl5_sub47969_c(i64 %x) {384; RV32I-LABEL: shl5_sub47969_c:385; RV32I: # %bb.0:386; RV32I-NEXT: srli a2, a0, 27387; RV32I-NEXT: slli a1, a1, 5388; RV32I-NEXT: slli a3, a0, 5389; RV32I-NEXT: or a1, a1, a2390; RV32I-NEXT: lui a0, 1048564391; RV32I-NEXT: addi a0, a0, 1183392; RV32I-NEXT: add a0, a3, a0393; RV32I-NEXT: sltu a2, a0, a3394; RV32I-NEXT: add a1, a1, a2395; RV32I-NEXT: addi a1, a1, -1396; RV32I-NEXT: ret397;398; RV64I-LABEL: shl5_sub47969_c:399; RV64I: # %bb.0:400; RV64I-NEXT: slli a0, a0, 5401; RV64I-NEXT: lui a1, 1048564402; RV64I-NEXT: addi a1, a1, 1183403; RV64I-NEXT: add a0, a0, a1404; RV64I-NEXT: ret405 %tmp0 = shl i64 %x, 5406 %tmp1 = add i64 %tmp0, -47969407 ret i64 %tmp1408}409