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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 62; RUN: llc < %s -mtriple=riscv32 -mattr=+zbb | FileCheck %s --check-prefixes=RV32I-ZBB3; RUN: llc < %s -mtriple=riscv64 -mattr=+zbb | FileCheck %s --check-prefixes=RV64I-ZBB4; RUN: llc < %s -mtriple=riscv32 -mattr=+zbb,+short-forward-branch-ialu | \5; RUN: FileCheck %s --check-prefixes=RV32I-SFB-ZBB6; RUN: llc < %s -mtriple=riscv64 -mattr=+zbb,+short-forward-branch-ialu | \7; RUN: FileCheck %s --check-prefixes=RV64I-SFB-ZBB8; RUN: llc < %s -mtriple=riscv32 -mattr=+zbb,+short-forward-branch-iminmax | \9; RUN: FileCheck %s --check-prefixes=RV32I-SFBIMinMax-ZBB10; RUN: llc < %s -mtriple=riscv64 -mattr=+zbb,+short-forward-branch-iminmax | \11; RUN: FileCheck %s --check-prefixes=RV64I-SFBIMinMax-ZBB12 13define i32 @select_example_smax(i32 %a, i32 %b, i1 zeroext %x, i32 %y) {14; RV32I-ZBB-LABEL: select_example_smax:15; RV32I-ZBB: # %bb.0: # %entry16; RV32I-ZBB-NEXT: beqz a2, .LBB0_217; RV32I-ZBB-NEXT: # %bb.1:18; RV32I-ZBB-NEXT: max a1, a0, a319; RV32I-ZBB-NEXT: .LBB0_2: # %entry20; RV32I-ZBB-NEXT: mv a0, a121; RV32I-ZBB-NEXT: ret22;23; RV64I-ZBB-LABEL: select_example_smax:24; RV64I-ZBB: # %bb.0: # %entry25; RV64I-ZBB-NEXT: beqz a2, .LBB0_226; RV64I-ZBB-NEXT: # %bb.1:27; RV64I-ZBB-NEXT: sext.w a3, a328; RV64I-ZBB-NEXT: sext.w a0, a029; RV64I-ZBB-NEXT: max a1, a0, a330; RV64I-ZBB-NEXT: .LBB0_2: # %entry31; RV64I-ZBB-NEXT: mv a0, a132; RV64I-ZBB-NEXT: ret33;34; RV32I-SFB-ZBB-LABEL: select_example_smax:35; RV32I-SFB-ZBB: # %bb.0: # %entry36; RV32I-SFB-ZBB-NEXT: max a0, a0, a337; RV32I-SFB-ZBB-NEXT: bnez a2, .LBB0_238; RV32I-SFB-ZBB-NEXT: # %bb.1: # %entry39; RV32I-SFB-ZBB-NEXT: mv a0, a140; RV32I-SFB-ZBB-NEXT: .LBB0_2: # %entry41; RV32I-SFB-ZBB-NEXT: ret42;43; RV64I-SFB-ZBB-LABEL: select_example_smax:44; RV64I-SFB-ZBB: # %bb.0: # %entry45; RV64I-SFB-ZBB-NEXT: sext.w a3, a346; RV64I-SFB-ZBB-NEXT: sext.w a0, a047; RV64I-SFB-ZBB-NEXT: max a0, a0, a348; RV64I-SFB-ZBB-NEXT: bnez a2, .LBB0_249; RV64I-SFB-ZBB-NEXT: # %bb.1: # %entry50; RV64I-SFB-ZBB-NEXT: mv a0, a151; RV64I-SFB-ZBB-NEXT: .LBB0_2: # %entry52; RV64I-SFB-ZBB-NEXT: ret53;54; RV32I-SFBIMinMax-ZBB-LABEL: select_example_smax:55; RV32I-SFBIMinMax-ZBB: # %bb.0: # %entry56; RV32I-SFBIMinMax-ZBB-NEXT: beqz a2, .LBB0_257; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry58; RV32I-SFBIMinMax-ZBB-NEXT: max a1, a0, a359; RV32I-SFBIMinMax-ZBB-NEXT: .LBB0_2: # %entry60; RV32I-SFBIMinMax-ZBB-NEXT: mv a0, a161; RV32I-SFBIMinMax-ZBB-NEXT: ret62;63; RV64I-SFBIMinMax-ZBB-LABEL: select_example_smax:64; RV64I-SFBIMinMax-ZBB: # %bb.0: # %entry65; RV64I-SFBIMinMax-ZBB-NEXT: sext.w a3, a366; RV64I-SFBIMinMax-ZBB-NEXT: sext.w a0, a067; RV64I-SFBIMinMax-ZBB-NEXT: beqz a2, .LBB0_268; RV64I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry69; RV64I-SFBIMinMax-ZBB-NEXT: max a1, a0, a370; RV64I-SFBIMinMax-ZBB-NEXT: .LBB0_2: # %entry71; RV64I-SFBIMinMax-ZBB-NEXT: mv a0, a172; RV64I-SFBIMinMax-ZBB-NEXT: ret73entry:74 %res = call i32 @llvm.smax.i32(i32 %a, i32 %y)75 %sel = select i1 %x, i32 %res, i32 %b76 ret i32 %sel77}78 79define i32 @select_example_smin(i32 %a, i32 %b, i1 zeroext %x, i32 %y) {80; RV32I-ZBB-LABEL: select_example_smin:81; RV32I-ZBB: # %bb.0: # %entry82; RV32I-ZBB-NEXT: beqz a2, .LBB1_283; RV32I-ZBB-NEXT: # %bb.1:84; RV32I-ZBB-NEXT: min a1, a0, a385; RV32I-ZBB-NEXT: .LBB1_2: # %entry86; RV32I-ZBB-NEXT: mv a0, a187; RV32I-ZBB-NEXT: ret88;89; RV64I-ZBB-LABEL: select_example_smin:90; RV64I-ZBB: # %bb.0: # %entry91; RV64I-ZBB-NEXT: beqz a2, .LBB1_292; RV64I-ZBB-NEXT: # %bb.1:93; RV64I-ZBB-NEXT: sext.w a3, a394; RV64I-ZBB-NEXT: sext.w a0, a095; RV64I-ZBB-NEXT: min a1, a0, a396; RV64I-ZBB-NEXT: .LBB1_2: # %entry97; RV64I-ZBB-NEXT: mv a0, a198; RV64I-ZBB-NEXT: ret99;100; RV32I-SFB-ZBB-LABEL: select_example_smin:101; RV32I-SFB-ZBB: # %bb.0: # %entry102; RV32I-SFB-ZBB-NEXT: min a0, a0, a3103; RV32I-SFB-ZBB-NEXT: bnez a2, .LBB1_2104; RV32I-SFB-ZBB-NEXT: # %bb.1: # %entry105; RV32I-SFB-ZBB-NEXT: mv a0, a1106; RV32I-SFB-ZBB-NEXT: .LBB1_2: # %entry107; RV32I-SFB-ZBB-NEXT: ret108;109; RV64I-SFB-ZBB-LABEL: select_example_smin:110; RV64I-SFB-ZBB: # %bb.0: # %entry111; RV64I-SFB-ZBB-NEXT: sext.w a3, a3112; RV64I-SFB-ZBB-NEXT: sext.w a0, a0113; RV64I-SFB-ZBB-NEXT: min a0, a0, a3114; RV64I-SFB-ZBB-NEXT: bnez a2, .LBB1_2115; RV64I-SFB-ZBB-NEXT: # %bb.1: # %entry116; RV64I-SFB-ZBB-NEXT: mv a0, a1117; RV64I-SFB-ZBB-NEXT: .LBB1_2: # %entry118; RV64I-SFB-ZBB-NEXT: ret119;120; RV32I-SFBIMinMax-ZBB-LABEL: select_example_smin:121; RV32I-SFBIMinMax-ZBB: # %bb.0: # %entry122; RV32I-SFBIMinMax-ZBB-NEXT: beqz a2, .LBB1_2123; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry124; RV32I-SFBIMinMax-ZBB-NEXT: min a1, a0, a3125; RV32I-SFBIMinMax-ZBB-NEXT: .LBB1_2: # %entry126; RV32I-SFBIMinMax-ZBB-NEXT: mv a0, a1127; RV32I-SFBIMinMax-ZBB-NEXT: ret128;129; RV64I-SFBIMinMax-ZBB-LABEL: select_example_smin:130; RV64I-SFBIMinMax-ZBB: # %bb.0: # %entry131; RV64I-SFBIMinMax-ZBB-NEXT: sext.w a3, a3132; RV64I-SFBIMinMax-ZBB-NEXT: sext.w a0, a0133; RV64I-SFBIMinMax-ZBB-NEXT: beqz a2, .LBB1_2134; RV64I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry135; RV64I-SFBIMinMax-ZBB-NEXT: min a1, a0, a3136; RV64I-SFBIMinMax-ZBB-NEXT: .LBB1_2: # %entry137; RV64I-SFBIMinMax-ZBB-NEXT: mv a0, a1138; RV64I-SFBIMinMax-ZBB-NEXT: ret139entry:140 %res = call i32 @llvm.smin.i32(i32 %a, i32 %y)141 %sel = select i1 %x, i32 %res, i32 %b142 ret i32 %sel143}144 145define i32 @select_example_umax(i32 %a, i32 %b, i1 zeroext %x, i32 %y) {146; RV32I-ZBB-LABEL: select_example_umax:147; RV32I-ZBB: # %bb.0: # %entry148; RV32I-ZBB-NEXT: beqz a2, .LBB2_2149; RV32I-ZBB-NEXT: # %bb.1:150; RV32I-ZBB-NEXT: maxu a1, a0, a3151; RV32I-ZBB-NEXT: .LBB2_2: # %entry152; RV32I-ZBB-NEXT: mv a0, a1153; RV32I-ZBB-NEXT: ret154;155; RV64I-ZBB-LABEL: select_example_umax:156; RV64I-ZBB: # %bb.0: # %entry157; RV64I-ZBB-NEXT: beqz a2, .LBB2_2158; RV64I-ZBB-NEXT: # %bb.1:159; RV64I-ZBB-NEXT: sext.w a3, a3160; RV64I-ZBB-NEXT: sext.w a0, a0161; RV64I-ZBB-NEXT: maxu a1, a0, a3162; RV64I-ZBB-NEXT: .LBB2_2: # %entry163; RV64I-ZBB-NEXT: mv a0, a1164; RV64I-ZBB-NEXT: ret165;166; RV32I-SFB-ZBB-LABEL: select_example_umax:167; RV32I-SFB-ZBB: # %bb.0: # %entry168; RV32I-SFB-ZBB-NEXT: maxu a0, a0, a3169; RV32I-SFB-ZBB-NEXT: bnez a2, .LBB2_2170; RV32I-SFB-ZBB-NEXT: # %bb.1: # %entry171; RV32I-SFB-ZBB-NEXT: mv a0, a1172; RV32I-SFB-ZBB-NEXT: .LBB2_2: # %entry173; RV32I-SFB-ZBB-NEXT: ret174;175; RV64I-SFB-ZBB-LABEL: select_example_umax:176; RV64I-SFB-ZBB: # %bb.0: # %entry177; RV64I-SFB-ZBB-NEXT: sext.w a3, a3178; RV64I-SFB-ZBB-NEXT: sext.w a0, a0179; RV64I-SFB-ZBB-NEXT: maxu a0, a0, a3180; RV64I-SFB-ZBB-NEXT: bnez a2, .LBB2_2181; RV64I-SFB-ZBB-NEXT: # %bb.1: # %entry182; RV64I-SFB-ZBB-NEXT: mv a0, a1183; RV64I-SFB-ZBB-NEXT: .LBB2_2: # %entry184; RV64I-SFB-ZBB-NEXT: ret185;186; RV32I-SFBIMinMax-ZBB-LABEL: select_example_umax:187; RV32I-SFBIMinMax-ZBB: # %bb.0: # %entry188; RV32I-SFBIMinMax-ZBB-NEXT: beqz a2, .LBB2_2189; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry190; RV32I-SFBIMinMax-ZBB-NEXT: maxu a1, a0, a3191; RV32I-SFBIMinMax-ZBB-NEXT: .LBB2_2: # %entry192; RV32I-SFBIMinMax-ZBB-NEXT: mv a0, a1193; RV32I-SFBIMinMax-ZBB-NEXT: ret194;195; RV64I-SFBIMinMax-ZBB-LABEL: select_example_umax:196; RV64I-SFBIMinMax-ZBB: # %bb.0: # %entry197; RV64I-SFBIMinMax-ZBB-NEXT: sext.w a3, a3198; RV64I-SFBIMinMax-ZBB-NEXT: sext.w a0, a0199; RV64I-SFBIMinMax-ZBB-NEXT: beqz a2, .LBB2_2200; RV64I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry201; RV64I-SFBIMinMax-ZBB-NEXT: maxu a1, a0, a3202; RV64I-SFBIMinMax-ZBB-NEXT: .LBB2_2: # %entry203; RV64I-SFBIMinMax-ZBB-NEXT: mv a0, a1204; RV64I-SFBIMinMax-ZBB-NEXT: ret205entry:206 %res = call i32 @llvm.umax.i32(i32 %a, i32 %y)207 %sel = select i1 %x, i32 %res, i32 %b208 ret i32 %sel209}210 211define i32 @select_example_umin(i32 %a, i32 %b, i1 zeroext %x, i32 %y) {212; RV32I-ZBB-LABEL: select_example_umin:213; RV32I-ZBB: # %bb.0: # %entry214; RV32I-ZBB-NEXT: beqz a2, .LBB3_2215; RV32I-ZBB-NEXT: # %bb.1:216; RV32I-ZBB-NEXT: minu a1, a0, a3217; RV32I-ZBB-NEXT: .LBB3_2: # %entry218; RV32I-ZBB-NEXT: mv a0, a1219; RV32I-ZBB-NEXT: ret220;221; RV64I-ZBB-LABEL: select_example_umin:222; RV64I-ZBB: # %bb.0: # %entry223; RV64I-ZBB-NEXT: beqz a2, .LBB3_2224; RV64I-ZBB-NEXT: # %bb.1:225; RV64I-ZBB-NEXT: sext.w a3, a3226; RV64I-ZBB-NEXT: sext.w a0, a0227; RV64I-ZBB-NEXT: minu a1, a0, a3228; RV64I-ZBB-NEXT: .LBB3_2: # %entry229; RV64I-ZBB-NEXT: mv a0, a1230; RV64I-ZBB-NEXT: ret231;232; RV32I-SFB-ZBB-LABEL: select_example_umin:233; RV32I-SFB-ZBB: # %bb.0: # %entry234; RV32I-SFB-ZBB-NEXT: minu a0, a0, a3235; RV32I-SFB-ZBB-NEXT: bnez a2, .LBB3_2236; RV32I-SFB-ZBB-NEXT: # %bb.1: # %entry237; RV32I-SFB-ZBB-NEXT: mv a0, a1238; RV32I-SFB-ZBB-NEXT: .LBB3_2: # %entry239; RV32I-SFB-ZBB-NEXT: ret240;241; RV64I-SFB-ZBB-LABEL: select_example_umin:242; RV64I-SFB-ZBB: # %bb.0: # %entry243; RV64I-SFB-ZBB-NEXT: sext.w a3, a3244; RV64I-SFB-ZBB-NEXT: sext.w a0, a0245; RV64I-SFB-ZBB-NEXT: minu a0, a0, a3246; RV64I-SFB-ZBB-NEXT: bnez a2, .LBB3_2247; RV64I-SFB-ZBB-NEXT: # %bb.1: # %entry248; RV64I-SFB-ZBB-NEXT: mv a0, a1249; RV64I-SFB-ZBB-NEXT: .LBB3_2: # %entry250; RV64I-SFB-ZBB-NEXT: ret251;252; RV32I-SFBIMinMax-ZBB-LABEL: select_example_umin:253; RV32I-SFBIMinMax-ZBB: # %bb.0: # %entry254; RV32I-SFBIMinMax-ZBB-NEXT: beqz a2, .LBB3_2255; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry256; RV32I-SFBIMinMax-ZBB-NEXT: minu a1, a0, a3257; RV32I-SFBIMinMax-ZBB-NEXT: .LBB3_2: # %entry258; RV32I-SFBIMinMax-ZBB-NEXT: mv a0, a1259; RV32I-SFBIMinMax-ZBB-NEXT: ret260;261; RV64I-SFBIMinMax-ZBB-LABEL: select_example_umin:262; RV64I-SFBIMinMax-ZBB: # %bb.0: # %entry263; RV64I-SFBIMinMax-ZBB-NEXT: sext.w a3, a3264; RV64I-SFBIMinMax-ZBB-NEXT: sext.w a0, a0265; RV64I-SFBIMinMax-ZBB-NEXT: beqz a2, .LBB3_2266; RV64I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry267; RV64I-SFBIMinMax-ZBB-NEXT: minu a1, a0, a3268; RV64I-SFBIMinMax-ZBB-NEXT: .LBB3_2: # %entry269; RV64I-SFBIMinMax-ZBB-NEXT: mv a0, a1270; RV64I-SFBIMinMax-ZBB-NEXT: ret271entry:272 %res = call i32 @llvm.umin.i32(i32 %a, i32 %y)273 %sel = select i1 %x, i32 %res, i32 %b274 ret i32 %sel275}276 277define i64 @select_example_smax_1(i64 %a, i64 %b, i1 zeroext %x, i64 %y) {278; RV32I-ZBB-LABEL: select_example_smax_1:279; RV32I-ZBB: # %bb.0: # %entry280; RV32I-ZBB-NEXT: beq a1, a6, .LBB4_2281; RV32I-ZBB-NEXT: # %bb.1: # %entry282; RV32I-ZBB-NEXT: slt a7, a6, a1283; RV32I-ZBB-NEXT: beqz a7, .LBB4_3284; RV32I-ZBB-NEXT: j .LBB4_4285; RV32I-ZBB-NEXT: .LBB4_2:286; RV32I-ZBB-NEXT: sltu a7, a5, a0287; RV32I-ZBB-NEXT: bnez a7, .LBB4_4288; RV32I-ZBB-NEXT: .LBB4_3: # %entry289; RV32I-ZBB-NEXT: mv a1, a6290; RV32I-ZBB-NEXT: mv a0, a5291; RV32I-ZBB-NEXT: .LBB4_4: # %entry292; RV32I-ZBB-NEXT: beqz a4, .LBB4_6293; RV32I-ZBB-NEXT: # %bb.5: # %entry294; RV32I-ZBB-NEXT: ret295; RV32I-ZBB-NEXT: .LBB4_6: # %entry296; RV32I-ZBB-NEXT: mv a0, a2297; RV32I-ZBB-NEXT: mv a1, a3298; RV32I-ZBB-NEXT: ret299;300; RV64I-ZBB-LABEL: select_example_smax_1:301; RV64I-ZBB: # %bb.0: # %entry302; RV64I-ZBB-NEXT: beqz a2, .LBB4_2303; RV64I-ZBB-NEXT: # %bb.1:304; RV64I-ZBB-NEXT: max a1, a0, a3305; RV64I-ZBB-NEXT: .LBB4_2: # %entry306; RV64I-ZBB-NEXT: mv a0, a1307; RV64I-ZBB-NEXT: ret308;309; RV32I-SFB-ZBB-LABEL: select_example_smax_1:310; RV32I-SFB-ZBB: # %bb.0: # %entry311; RV32I-SFB-ZBB-NEXT: sltu a7, a5, a0312; RV32I-SFB-ZBB-NEXT: slt t0, a6, a1313; RV32I-SFB-ZBB-NEXT: bne a1, a6, .LBB4_2314; RV32I-SFB-ZBB-NEXT: # %bb.1: # %entry315; RV32I-SFB-ZBB-NEXT: mv t0, a7316; RV32I-SFB-ZBB-NEXT: .LBB4_2: # %entry317; RV32I-SFB-ZBB-NEXT: bnez t0, .LBB4_4318; RV32I-SFB-ZBB-NEXT: # %bb.3: # %entry319; RV32I-SFB-ZBB-NEXT: mv a1, a6320; RV32I-SFB-ZBB-NEXT: .LBB4_4: # %entry321; RV32I-SFB-ZBB-NEXT: bnez t0, .LBB4_6322; RV32I-SFB-ZBB-NEXT: # %bb.5: # %entry323; RV32I-SFB-ZBB-NEXT: mv a0, a5324; RV32I-SFB-ZBB-NEXT: .LBB4_6: # %entry325; RV32I-SFB-ZBB-NEXT: bnez a4, .LBB4_8326; RV32I-SFB-ZBB-NEXT: # %bb.7: # %entry327; RV32I-SFB-ZBB-NEXT: mv a0, a2328; RV32I-SFB-ZBB-NEXT: .LBB4_8: # %entry329; RV32I-SFB-ZBB-NEXT: bnez a4, .LBB4_10330; RV32I-SFB-ZBB-NEXT: # %bb.9: # %entry331; RV32I-SFB-ZBB-NEXT: mv a1, a3332; RV32I-SFB-ZBB-NEXT: .LBB4_10: # %entry333; RV32I-SFB-ZBB-NEXT: ret334;335; RV64I-SFB-ZBB-LABEL: select_example_smax_1:336; RV64I-SFB-ZBB: # %bb.0: # %entry337; RV64I-SFB-ZBB-NEXT: max a0, a0, a3338; RV64I-SFB-ZBB-NEXT: bnez a2, .LBB4_2339; RV64I-SFB-ZBB-NEXT: # %bb.1: # %entry340; RV64I-SFB-ZBB-NEXT: mv a0, a1341; RV64I-SFB-ZBB-NEXT: .LBB4_2: # %entry342; RV64I-SFB-ZBB-NEXT: ret343;344; RV32I-SFBIMinMax-ZBB-LABEL: select_example_smax_1:345; RV32I-SFBIMinMax-ZBB: # %bb.0: # %entry346; RV32I-SFBIMinMax-ZBB-NEXT: sltu a7, a5, a0347; RV32I-SFBIMinMax-ZBB-NEXT: slt t0, a6, a1348; RV32I-SFBIMinMax-ZBB-NEXT: bne a1, a6, .LBB4_2349; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry350; RV32I-SFBIMinMax-ZBB-NEXT: mv t0, a7351; RV32I-SFBIMinMax-ZBB-NEXT: .LBB4_2: # %entry352; RV32I-SFBIMinMax-ZBB-NEXT: bnez t0, .LBB4_4353; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.3: # %entry354; RV32I-SFBIMinMax-ZBB-NEXT: mv a1, a6355; RV32I-SFBIMinMax-ZBB-NEXT: .LBB4_4: # %entry356; RV32I-SFBIMinMax-ZBB-NEXT: bnez t0, .LBB4_6357; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.5: # %entry358; RV32I-SFBIMinMax-ZBB-NEXT: mv a0, a5359; RV32I-SFBIMinMax-ZBB-NEXT: .LBB4_6: # %entry360; RV32I-SFBIMinMax-ZBB-NEXT: bnez a4, .LBB4_8361; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.7: # %entry362; RV32I-SFBIMinMax-ZBB-NEXT: mv a0, a2363; RV32I-SFBIMinMax-ZBB-NEXT: .LBB4_8: # %entry364; RV32I-SFBIMinMax-ZBB-NEXT: bnez a4, .LBB4_10365; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.9: # %entry366; RV32I-SFBIMinMax-ZBB-NEXT: mv a1, a3367; RV32I-SFBIMinMax-ZBB-NEXT: .LBB4_10: # %entry368; RV32I-SFBIMinMax-ZBB-NEXT: ret369;370; RV64I-SFBIMinMax-ZBB-LABEL: select_example_smax_1:371; RV64I-SFBIMinMax-ZBB: # %bb.0: # %entry372; RV64I-SFBIMinMax-ZBB-NEXT: beqz a2, .LBB4_2373; RV64I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry374; RV64I-SFBIMinMax-ZBB-NEXT: max a1, a0, a3375; RV64I-SFBIMinMax-ZBB-NEXT: .LBB4_2: # %entry376; RV64I-SFBIMinMax-ZBB-NEXT: mv a0, a1377; RV64I-SFBIMinMax-ZBB-NEXT: ret378entry:379 %res = call i64 @llvm.smax.i64(i64 %a, i64 %y)380 %sel = select i1 %x, i64 %res, i64 %b381 ret i64 %sel382}383 384define i64 @select_example_smin_1(i64 %a, i64 %b, i1 zeroext %x, i64 %y) {385; RV32I-ZBB-LABEL: select_example_smin_1:386; RV32I-ZBB: # %bb.0: # %entry387; RV32I-ZBB-NEXT: beq a1, a6, .LBB5_2388; RV32I-ZBB-NEXT: # %bb.1: # %entry389; RV32I-ZBB-NEXT: slt a7, a1, a6390; RV32I-ZBB-NEXT: beqz a7, .LBB5_3391; RV32I-ZBB-NEXT: j .LBB5_4392; RV32I-ZBB-NEXT: .LBB5_2:393; RV32I-ZBB-NEXT: sltu a7, a0, a5394; RV32I-ZBB-NEXT: bnez a7, .LBB5_4395; RV32I-ZBB-NEXT: .LBB5_3: # %entry396; RV32I-ZBB-NEXT: mv a1, a6397; RV32I-ZBB-NEXT: mv a0, a5398; RV32I-ZBB-NEXT: .LBB5_4: # %entry399; RV32I-ZBB-NEXT: beqz a4, .LBB5_6400; RV32I-ZBB-NEXT: # %bb.5: # %entry401; RV32I-ZBB-NEXT: ret402; RV32I-ZBB-NEXT: .LBB5_6: # %entry403; RV32I-ZBB-NEXT: mv a0, a2404; RV32I-ZBB-NEXT: mv a1, a3405; RV32I-ZBB-NEXT: ret406;407; RV64I-ZBB-LABEL: select_example_smin_1:408; RV64I-ZBB: # %bb.0: # %entry409; RV64I-ZBB-NEXT: beqz a2, .LBB5_2410; RV64I-ZBB-NEXT: # %bb.1:411; RV64I-ZBB-NEXT: min a1, a0, a3412; RV64I-ZBB-NEXT: .LBB5_2: # %entry413; RV64I-ZBB-NEXT: mv a0, a1414; RV64I-ZBB-NEXT: ret415;416; RV32I-SFB-ZBB-LABEL: select_example_smin_1:417; RV32I-SFB-ZBB: # %bb.0: # %entry418; RV32I-SFB-ZBB-NEXT: sltu a7, a0, a5419; RV32I-SFB-ZBB-NEXT: slt t0, a1, a6420; RV32I-SFB-ZBB-NEXT: bne a1, a6, .LBB5_2421; RV32I-SFB-ZBB-NEXT: # %bb.1: # %entry422; RV32I-SFB-ZBB-NEXT: mv t0, a7423; RV32I-SFB-ZBB-NEXT: .LBB5_2: # %entry424; RV32I-SFB-ZBB-NEXT: bnez t0, .LBB5_4425; RV32I-SFB-ZBB-NEXT: # %bb.3: # %entry426; RV32I-SFB-ZBB-NEXT: mv a1, a6427; RV32I-SFB-ZBB-NEXT: .LBB5_4: # %entry428; RV32I-SFB-ZBB-NEXT: bnez t0, .LBB5_6429; RV32I-SFB-ZBB-NEXT: # %bb.5: # %entry430; RV32I-SFB-ZBB-NEXT: mv a0, a5431; RV32I-SFB-ZBB-NEXT: .LBB5_6: # %entry432; RV32I-SFB-ZBB-NEXT: bnez a4, .LBB5_8433; RV32I-SFB-ZBB-NEXT: # %bb.7: # %entry434; RV32I-SFB-ZBB-NEXT: mv a0, a2435; RV32I-SFB-ZBB-NEXT: .LBB5_8: # %entry436; RV32I-SFB-ZBB-NEXT: bnez a4, .LBB5_10437; RV32I-SFB-ZBB-NEXT: # %bb.9: # %entry438; RV32I-SFB-ZBB-NEXT: mv a1, a3439; RV32I-SFB-ZBB-NEXT: .LBB5_10: # %entry440; RV32I-SFB-ZBB-NEXT: ret441;442; RV64I-SFB-ZBB-LABEL: select_example_smin_1:443; RV64I-SFB-ZBB: # %bb.0: # %entry444; RV64I-SFB-ZBB-NEXT: min a0, a0, a3445; RV64I-SFB-ZBB-NEXT: bnez a2, .LBB5_2446; RV64I-SFB-ZBB-NEXT: # %bb.1: # %entry447; RV64I-SFB-ZBB-NEXT: mv a0, a1448; RV64I-SFB-ZBB-NEXT: .LBB5_2: # %entry449; RV64I-SFB-ZBB-NEXT: ret450;451; RV32I-SFBIMinMax-ZBB-LABEL: select_example_smin_1:452; RV32I-SFBIMinMax-ZBB: # %bb.0: # %entry453; RV32I-SFBIMinMax-ZBB-NEXT: sltu a7, a0, a5454; RV32I-SFBIMinMax-ZBB-NEXT: slt t0, a1, a6455; RV32I-SFBIMinMax-ZBB-NEXT: bne a1, a6, .LBB5_2456; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry457; RV32I-SFBIMinMax-ZBB-NEXT: mv t0, a7458; RV32I-SFBIMinMax-ZBB-NEXT: .LBB5_2: # %entry459; RV32I-SFBIMinMax-ZBB-NEXT: bnez t0, .LBB5_4460; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.3: # %entry461; RV32I-SFBIMinMax-ZBB-NEXT: mv a1, a6462; RV32I-SFBIMinMax-ZBB-NEXT: .LBB5_4: # %entry463; RV32I-SFBIMinMax-ZBB-NEXT: bnez t0, .LBB5_6464; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.5: # %entry465; RV32I-SFBIMinMax-ZBB-NEXT: mv a0, a5466; RV32I-SFBIMinMax-ZBB-NEXT: .LBB5_6: # %entry467; RV32I-SFBIMinMax-ZBB-NEXT: bnez a4, .LBB5_8468; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.7: # %entry469; RV32I-SFBIMinMax-ZBB-NEXT: mv a0, a2470; RV32I-SFBIMinMax-ZBB-NEXT: .LBB5_8: # %entry471; RV32I-SFBIMinMax-ZBB-NEXT: bnez a4, .LBB5_10472; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.9: # %entry473; RV32I-SFBIMinMax-ZBB-NEXT: mv a1, a3474; RV32I-SFBIMinMax-ZBB-NEXT: .LBB5_10: # %entry475; RV32I-SFBIMinMax-ZBB-NEXT: ret476;477; RV64I-SFBIMinMax-ZBB-LABEL: select_example_smin_1:478; RV64I-SFBIMinMax-ZBB: # %bb.0: # %entry479; RV64I-SFBIMinMax-ZBB-NEXT: beqz a2, .LBB5_2480; RV64I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry481; RV64I-SFBIMinMax-ZBB-NEXT: min a1, a0, a3482; RV64I-SFBIMinMax-ZBB-NEXT: .LBB5_2: # %entry483; RV64I-SFBIMinMax-ZBB-NEXT: mv a0, a1484; RV64I-SFBIMinMax-ZBB-NEXT: ret485entry:486 %res = call i64 @llvm.smin.i64(i64 %a, i64 %y)487 %sel = select i1 %x, i64 %res, i64 %b488 ret i64 %sel489}490 491define i64 @select_example_umax_1(i64 %a, i64 %b, i1 zeroext %x, i64 %y) {492; RV32I-ZBB-LABEL: select_example_umax_1:493; RV32I-ZBB: # %bb.0: # %entry494; RV32I-ZBB-NEXT: beq a1, a6, .LBB6_2495; RV32I-ZBB-NEXT: # %bb.1: # %entry496; RV32I-ZBB-NEXT: sltu a7, a6, a1497; RV32I-ZBB-NEXT: beqz a7, .LBB6_3498; RV32I-ZBB-NEXT: j .LBB6_4499; RV32I-ZBB-NEXT: .LBB6_2:500; RV32I-ZBB-NEXT: sltu a7, a5, a0501; RV32I-ZBB-NEXT: bnez a7, .LBB6_4502; RV32I-ZBB-NEXT: .LBB6_3: # %entry503; RV32I-ZBB-NEXT: mv a1, a6504; RV32I-ZBB-NEXT: mv a0, a5505; RV32I-ZBB-NEXT: .LBB6_4: # %entry506; RV32I-ZBB-NEXT: beqz a4, .LBB6_6507; RV32I-ZBB-NEXT: # %bb.5: # %entry508; RV32I-ZBB-NEXT: ret509; RV32I-ZBB-NEXT: .LBB6_6: # %entry510; RV32I-ZBB-NEXT: mv a0, a2511; RV32I-ZBB-NEXT: mv a1, a3512; RV32I-ZBB-NEXT: ret513;514; RV64I-ZBB-LABEL: select_example_umax_1:515; RV64I-ZBB: # %bb.0: # %entry516; RV64I-ZBB-NEXT: beqz a2, .LBB6_2517; RV64I-ZBB-NEXT: # %bb.1:518; RV64I-ZBB-NEXT: maxu a1, a0, a3519; RV64I-ZBB-NEXT: .LBB6_2: # %entry520; RV64I-ZBB-NEXT: mv a0, a1521; RV64I-ZBB-NEXT: ret522;523; RV32I-SFB-ZBB-LABEL: select_example_umax_1:524; RV32I-SFB-ZBB: # %bb.0: # %entry525; RV32I-SFB-ZBB-NEXT: sltu a7, a5, a0526; RV32I-SFB-ZBB-NEXT: sltu t0, a6, a1527; RV32I-SFB-ZBB-NEXT: bne a1, a6, .LBB6_2528; RV32I-SFB-ZBB-NEXT: # %bb.1: # %entry529; RV32I-SFB-ZBB-NEXT: mv t0, a7530; RV32I-SFB-ZBB-NEXT: .LBB6_2: # %entry531; RV32I-SFB-ZBB-NEXT: bnez t0, .LBB6_4532; RV32I-SFB-ZBB-NEXT: # %bb.3: # %entry533; RV32I-SFB-ZBB-NEXT: mv a1, a6534; RV32I-SFB-ZBB-NEXT: .LBB6_4: # %entry535; RV32I-SFB-ZBB-NEXT: bnez t0, .LBB6_6536; RV32I-SFB-ZBB-NEXT: # %bb.5: # %entry537; RV32I-SFB-ZBB-NEXT: mv a0, a5538; RV32I-SFB-ZBB-NEXT: .LBB6_6: # %entry539; RV32I-SFB-ZBB-NEXT: bnez a4, .LBB6_8540; RV32I-SFB-ZBB-NEXT: # %bb.7: # %entry541; RV32I-SFB-ZBB-NEXT: mv a0, a2542; RV32I-SFB-ZBB-NEXT: .LBB6_8: # %entry543; RV32I-SFB-ZBB-NEXT: bnez a4, .LBB6_10544; RV32I-SFB-ZBB-NEXT: # %bb.9: # %entry545; RV32I-SFB-ZBB-NEXT: mv a1, a3546; RV32I-SFB-ZBB-NEXT: .LBB6_10: # %entry547; RV32I-SFB-ZBB-NEXT: ret548;549; RV64I-SFB-ZBB-LABEL: select_example_umax_1:550; RV64I-SFB-ZBB: # %bb.0: # %entry551; RV64I-SFB-ZBB-NEXT: maxu a0, a0, a3552; RV64I-SFB-ZBB-NEXT: bnez a2, .LBB6_2553; RV64I-SFB-ZBB-NEXT: # %bb.1: # %entry554; RV64I-SFB-ZBB-NEXT: mv a0, a1555; RV64I-SFB-ZBB-NEXT: .LBB6_2: # %entry556; RV64I-SFB-ZBB-NEXT: ret557;558; RV32I-SFBIMinMax-ZBB-LABEL: select_example_umax_1:559; RV32I-SFBIMinMax-ZBB: # %bb.0: # %entry560; RV32I-SFBIMinMax-ZBB-NEXT: sltu a7, a5, a0561; RV32I-SFBIMinMax-ZBB-NEXT: sltu t0, a6, a1562; RV32I-SFBIMinMax-ZBB-NEXT: bne a1, a6, .LBB6_2563; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry564; RV32I-SFBIMinMax-ZBB-NEXT: mv t0, a7565; RV32I-SFBIMinMax-ZBB-NEXT: .LBB6_2: # %entry566; RV32I-SFBIMinMax-ZBB-NEXT: bnez t0, .LBB6_4567; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.3: # %entry568; RV32I-SFBIMinMax-ZBB-NEXT: mv a1, a6569; RV32I-SFBIMinMax-ZBB-NEXT: .LBB6_4: # %entry570; RV32I-SFBIMinMax-ZBB-NEXT: bnez t0, .LBB6_6571; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.5: # %entry572; RV32I-SFBIMinMax-ZBB-NEXT: mv a0, a5573; RV32I-SFBIMinMax-ZBB-NEXT: .LBB6_6: # %entry574; RV32I-SFBIMinMax-ZBB-NEXT: bnez a4, .LBB6_8575; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.7: # %entry576; RV32I-SFBIMinMax-ZBB-NEXT: mv a0, a2577; RV32I-SFBIMinMax-ZBB-NEXT: .LBB6_8: # %entry578; RV32I-SFBIMinMax-ZBB-NEXT: bnez a4, .LBB6_10579; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.9: # %entry580; RV32I-SFBIMinMax-ZBB-NEXT: mv a1, a3581; RV32I-SFBIMinMax-ZBB-NEXT: .LBB6_10: # %entry582; RV32I-SFBIMinMax-ZBB-NEXT: ret583;584; RV64I-SFBIMinMax-ZBB-LABEL: select_example_umax_1:585; RV64I-SFBIMinMax-ZBB: # %bb.0: # %entry586; RV64I-SFBIMinMax-ZBB-NEXT: beqz a2, .LBB6_2587; RV64I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry588; RV64I-SFBIMinMax-ZBB-NEXT: maxu a1, a0, a3589; RV64I-SFBIMinMax-ZBB-NEXT: .LBB6_2: # %entry590; RV64I-SFBIMinMax-ZBB-NEXT: mv a0, a1591; RV64I-SFBIMinMax-ZBB-NEXT: ret592entry:593 %res = call i64 @llvm.umax.i64(i64 %a, i64 %y)594 %sel = select i1 %x, i64 %res, i64 %b595 ret i64 %sel596}597 598define i64 @select_example_umin_1(i64 %a, i64 %b, i1 zeroext %x, i64 %y) {599; RV32I-ZBB-LABEL: select_example_umin_1:600; RV32I-ZBB: # %bb.0: # %entry601; RV32I-ZBB-NEXT: beq a1, a6, .LBB7_2602; RV32I-ZBB-NEXT: # %bb.1: # %entry603; RV32I-ZBB-NEXT: sltu a7, a1, a6604; RV32I-ZBB-NEXT: beqz a7, .LBB7_3605; RV32I-ZBB-NEXT: j .LBB7_4606; RV32I-ZBB-NEXT: .LBB7_2:607; RV32I-ZBB-NEXT: sltu a7, a0, a5608; RV32I-ZBB-NEXT: bnez a7, .LBB7_4609; RV32I-ZBB-NEXT: .LBB7_3: # %entry610; RV32I-ZBB-NEXT: mv a1, a6611; RV32I-ZBB-NEXT: mv a0, a5612; RV32I-ZBB-NEXT: .LBB7_4: # %entry613; RV32I-ZBB-NEXT: beqz a4, .LBB7_6614; RV32I-ZBB-NEXT: # %bb.5: # %entry615; RV32I-ZBB-NEXT: ret616; RV32I-ZBB-NEXT: .LBB7_6: # %entry617; RV32I-ZBB-NEXT: mv a0, a2618; RV32I-ZBB-NEXT: mv a1, a3619; RV32I-ZBB-NEXT: ret620;621; RV64I-ZBB-LABEL: select_example_umin_1:622; RV64I-ZBB: # %bb.0: # %entry623; RV64I-ZBB-NEXT: beqz a2, .LBB7_2624; RV64I-ZBB-NEXT: # %bb.1:625; RV64I-ZBB-NEXT: minu a1, a0, a3626; RV64I-ZBB-NEXT: .LBB7_2: # %entry627; RV64I-ZBB-NEXT: mv a0, a1628; RV64I-ZBB-NEXT: ret629;630; RV32I-SFB-ZBB-LABEL: select_example_umin_1:631; RV32I-SFB-ZBB: # %bb.0: # %entry632; RV32I-SFB-ZBB-NEXT: sltu a7, a0, a5633; RV32I-SFB-ZBB-NEXT: sltu t0, a1, a6634; RV32I-SFB-ZBB-NEXT: bne a1, a6, .LBB7_2635; RV32I-SFB-ZBB-NEXT: # %bb.1: # %entry636; RV32I-SFB-ZBB-NEXT: mv t0, a7637; RV32I-SFB-ZBB-NEXT: .LBB7_2: # %entry638; RV32I-SFB-ZBB-NEXT: bnez t0, .LBB7_4639; RV32I-SFB-ZBB-NEXT: # %bb.3: # %entry640; RV32I-SFB-ZBB-NEXT: mv a1, a6641; RV32I-SFB-ZBB-NEXT: .LBB7_4: # %entry642; RV32I-SFB-ZBB-NEXT: bnez t0, .LBB7_6643; RV32I-SFB-ZBB-NEXT: # %bb.5: # %entry644; RV32I-SFB-ZBB-NEXT: mv a0, a5645; RV32I-SFB-ZBB-NEXT: .LBB7_6: # %entry646; RV32I-SFB-ZBB-NEXT: bnez a4, .LBB7_8647; RV32I-SFB-ZBB-NEXT: # %bb.7: # %entry648; RV32I-SFB-ZBB-NEXT: mv a0, a2649; RV32I-SFB-ZBB-NEXT: .LBB7_8: # %entry650; RV32I-SFB-ZBB-NEXT: bnez a4, .LBB7_10651; RV32I-SFB-ZBB-NEXT: # %bb.9: # %entry652; RV32I-SFB-ZBB-NEXT: mv a1, a3653; RV32I-SFB-ZBB-NEXT: .LBB7_10: # %entry654; RV32I-SFB-ZBB-NEXT: ret655;656; RV64I-SFB-ZBB-LABEL: select_example_umin_1:657; RV64I-SFB-ZBB: # %bb.0: # %entry658; RV64I-SFB-ZBB-NEXT: minu a0, a0, a3659; RV64I-SFB-ZBB-NEXT: bnez a2, .LBB7_2660; RV64I-SFB-ZBB-NEXT: # %bb.1: # %entry661; RV64I-SFB-ZBB-NEXT: mv a0, a1662; RV64I-SFB-ZBB-NEXT: .LBB7_2: # %entry663; RV64I-SFB-ZBB-NEXT: ret664;665; RV32I-SFBIMinMax-ZBB-LABEL: select_example_umin_1:666; RV32I-SFBIMinMax-ZBB: # %bb.0: # %entry667; RV32I-SFBIMinMax-ZBB-NEXT: sltu a7, a0, a5668; RV32I-SFBIMinMax-ZBB-NEXT: sltu t0, a1, a6669; RV32I-SFBIMinMax-ZBB-NEXT: bne a1, a6, .LBB7_2670; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry671; RV32I-SFBIMinMax-ZBB-NEXT: mv t0, a7672; RV32I-SFBIMinMax-ZBB-NEXT: .LBB7_2: # %entry673; RV32I-SFBIMinMax-ZBB-NEXT: bnez t0, .LBB7_4674; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.3: # %entry675; RV32I-SFBIMinMax-ZBB-NEXT: mv a1, a6676; RV32I-SFBIMinMax-ZBB-NEXT: .LBB7_4: # %entry677; RV32I-SFBIMinMax-ZBB-NEXT: bnez t0, .LBB7_6678; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.5: # %entry679; RV32I-SFBIMinMax-ZBB-NEXT: mv a0, a5680; RV32I-SFBIMinMax-ZBB-NEXT: .LBB7_6: # %entry681; RV32I-SFBIMinMax-ZBB-NEXT: bnez a4, .LBB7_8682; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.7: # %entry683; RV32I-SFBIMinMax-ZBB-NEXT: mv a0, a2684; RV32I-SFBIMinMax-ZBB-NEXT: .LBB7_8: # %entry685; RV32I-SFBIMinMax-ZBB-NEXT: bnez a4, .LBB7_10686; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.9: # %entry687; RV32I-SFBIMinMax-ZBB-NEXT: mv a1, a3688; RV32I-SFBIMinMax-ZBB-NEXT: .LBB7_10: # %entry689; RV32I-SFBIMinMax-ZBB-NEXT: ret690;691; RV64I-SFBIMinMax-ZBB-LABEL: select_example_umin_1:692; RV64I-SFBIMinMax-ZBB: # %bb.0: # %entry693; RV64I-SFBIMinMax-ZBB-NEXT: beqz a2, .LBB7_2694; RV64I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry695; RV64I-SFBIMinMax-ZBB-NEXT: minu a1, a0, a3696; RV64I-SFBIMinMax-ZBB-NEXT: .LBB7_2: # %entry697; RV64I-SFBIMinMax-ZBB-NEXT: mv a0, a1698; RV64I-SFBIMinMax-ZBB-NEXT: ret699entry:700 %res = call i64 @llvm.umin.i64(i64 %a, i64 %y)701 %sel = select i1 %x, i64 %res, i64 %b702 ret i64 %sel703}704