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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 62; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefixes=RV32I-M3; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefixes=RV64I-M4; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+short-forward-branch-ialu | \5; RUN: FileCheck %s --check-prefixes=RV32I-SFB-M6; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+short-forward-branch-ialu | \7; RUN: FileCheck %s --check-prefixes=RV64I-SFB-M8; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+short-forward-branch-imul | \9; RUN: FileCheck %s --check-prefixes=RV32I-SFBIMul-M10; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+short-forward-branch-imul | \11; RUN: FileCheck %s --check-prefixes=RV64I-SFBIMul-M12 13define i32 @select_example_mul_i32(i32 %a, i32 %b, i1 zeroext %x, i32 %y) {14; RV32I-M-LABEL: select_example_mul_i32:15; RV32I-M: # %bb.0: # %entry16; RV32I-M-NEXT: beqz a2, .LBB0_217; RV32I-M-NEXT: # %bb.1:18; RV32I-M-NEXT: mul a1, a0, a319; RV32I-M-NEXT: .LBB0_2: # %entry20; RV32I-M-NEXT: mv a0, a121; RV32I-M-NEXT: ret22;23; RV64I-M-LABEL: select_example_mul_i32:24; RV64I-M: # %bb.0: # %entry25; RV64I-M-NEXT: beqz a2, .LBB0_226; RV64I-M-NEXT: # %bb.1:27; RV64I-M-NEXT: mulw a1, a0, a328; RV64I-M-NEXT: .LBB0_2: # %entry29; RV64I-M-NEXT: mv a0, a130; RV64I-M-NEXT: ret31;32; RV32I-SFB-M-LABEL: select_example_mul_i32:33; RV32I-SFB-M: # %bb.0: # %entry34; RV32I-SFB-M-NEXT: mul a0, a0, a335; RV32I-SFB-M-NEXT: bnez a2, .LBB0_236; RV32I-SFB-M-NEXT: # %bb.1: # %entry37; RV32I-SFB-M-NEXT: mv a0, a138; RV32I-SFB-M-NEXT: .LBB0_2: # %entry39; RV32I-SFB-M-NEXT: ret40;41; RV64I-SFB-M-LABEL: select_example_mul_i32:42; RV64I-SFB-M: # %bb.0: # %entry43; RV64I-SFB-M-NEXT: mulw a0, a0, a344; RV64I-SFB-M-NEXT: bnez a2, .LBB0_245; RV64I-SFB-M-NEXT: # %bb.1: # %entry46; RV64I-SFB-M-NEXT: mv a0, a147; RV64I-SFB-M-NEXT: .LBB0_2: # %entry48; RV64I-SFB-M-NEXT: ret49;50; RV32I-SFBIMul-M-LABEL: select_example_mul_i32:51; RV32I-SFBIMul-M: # %bb.0: # %entry52; RV32I-SFBIMul-M-NEXT: beqz a2, .LBB0_253; RV32I-SFBIMul-M-NEXT: # %bb.1: # %entry54; RV32I-SFBIMul-M-NEXT: mul a1, a0, a355; RV32I-SFBIMul-M-NEXT: .LBB0_2: # %entry56; RV32I-SFBIMul-M-NEXT: mv a0, a157; RV32I-SFBIMul-M-NEXT: ret58;59; RV64I-SFBIMul-M-LABEL: select_example_mul_i32:60; RV64I-SFBIMul-M: # %bb.0: # %entry61; RV64I-SFBIMul-M-NEXT: mulw a0, a0, a362; RV64I-SFBIMul-M-NEXT: bnez a2, .LBB0_263; RV64I-SFBIMul-M-NEXT: # %bb.1: # %entry64; RV64I-SFBIMul-M-NEXT: mv a0, a165; RV64I-SFBIMul-M-NEXT: .LBB0_2: # %entry66; RV64I-SFBIMul-M-NEXT: ret67entry:68 %res = mul i32 %a, %y69 %sel = select i1 %x, i32 %res, i32 %b70 ret i32 %sel71}72 73define i64 @select_example_mul_i64(i64 %a, i64 %b, i1 zeroext %x, i64 %y) {74; RV32I-M-LABEL: select_example_mul_i64:75; RV32I-M: # %bb.0: # %entry76; RV32I-M-NEXT: beqz a4, .LBB1_277; RV32I-M-NEXT: # %bb.1:78; RV32I-M-NEXT: mul a2, a0, a679; RV32I-M-NEXT: mulhu a3, a0, a580; RV32I-M-NEXT: mul a1, a1, a581; RV32I-M-NEXT: add a2, a3, a282; RV32I-M-NEXT: add a3, a2, a183; RV32I-M-NEXT: mul a2, a0, a584; RV32I-M-NEXT: .LBB1_2: # %entry85; RV32I-M-NEXT: mv a0, a286; RV32I-M-NEXT: mv a1, a387; RV32I-M-NEXT: ret88;89; RV64I-M-LABEL: select_example_mul_i64:90; RV64I-M: # %bb.0: # %entry91; RV64I-M-NEXT: beqz a2, .LBB1_292; RV64I-M-NEXT: # %bb.1:93; RV64I-M-NEXT: mul a1, a0, a394; RV64I-M-NEXT: .LBB1_2: # %entry95; RV64I-M-NEXT: mv a0, a196; RV64I-M-NEXT: ret97;98; RV32I-SFB-M-LABEL: select_example_mul_i64:99; RV32I-SFB-M: # %bb.0: # %entry100; RV32I-SFB-M-NEXT: mul a6, a0, a6101; RV32I-SFB-M-NEXT: mulhu a7, a0, a5102; RV32I-SFB-M-NEXT: mul a1, a1, a5103; RV32I-SFB-M-NEXT: mul a0, a0, a5104; RV32I-SFB-M-NEXT: add a6, a7, a6105; RV32I-SFB-M-NEXT: beqz a4, .LBB1_2106; RV32I-SFB-M-NEXT: # %bb.1: # %entry107; RV32I-SFB-M-NEXT: add a3, a6, a1108; RV32I-SFB-M-NEXT: .LBB1_2: # %entry109; RV32I-SFB-M-NEXT: bnez a4, .LBB1_4110; RV32I-SFB-M-NEXT: # %bb.3: # %entry111; RV32I-SFB-M-NEXT: mv a0, a2112; RV32I-SFB-M-NEXT: .LBB1_4: # %entry113; RV32I-SFB-M-NEXT: mv a1, a3114; RV32I-SFB-M-NEXT: ret115;116; RV64I-SFB-M-LABEL: select_example_mul_i64:117; RV64I-SFB-M: # %bb.0: # %entry118; RV64I-SFB-M-NEXT: mul a0, a0, a3119; RV64I-SFB-M-NEXT: bnez a2, .LBB1_2120; RV64I-SFB-M-NEXT: # %bb.1: # %entry121; RV64I-SFB-M-NEXT: mv a0, a1122; RV64I-SFB-M-NEXT: .LBB1_2: # %entry123; RV64I-SFB-M-NEXT: ret124;125; RV32I-SFBIMul-M-LABEL: select_example_mul_i64:126; RV32I-SFBIMul-M: # %bb.0: # %entry127; RV32I-SFBIMul-M-NEXT: mul a6, a0, a6128; RV32I-SFBIMul-M-NEXT: mulhu a7, a0, a5129; RV32I-SFBIMul-M-NEXT: mul a1, a1, a5130; RV32I-SFBIMul-M-NEXT: add a6, a7, a6131; RV32I-SFBIMul-M-NEXT: beqz a4, .LBB1_2132; RV32I-SFBIMul-M-NEXT: # %bb.1: # %entry133; RV32I-SFBIMul-M-NEXT: add a3, a6, a1134; RV32I-SFBIMul-M-NEXT: .LBB1_2: # %entry135; RV32I-SFBIMul-M-NEXT: beqz a4, .LBB1_4136; RV32I-SFBIMul-M-NEXT: # %bb.3: # %entry137; RV32I-SFBIMul-M-NEXT: mul a2, a0, a5138; RV32I-SFBIMul-M-NEXT: .LBB1_4: # %entry139; RV32I-SFBIMul-M-NEXT: mv a0, a2140; RV32I-SFBIMul-M-NEXT: mv a1, a3141; RV32I-SFBIMul-M-NEXT: ret142;143; RV64I-SFBIMul-M-LABEL: select_example_mul_i64:144; RV64I-SFBIMul-M: # %bb.0: # %entry145; RV64I-SFBIMul-M-NEXT: beqz a2, .LBB1_2146; RV64I-SFBIMul-M-NEXT: # %bb.1: # %entry147; RV64I-SFBIMul-M-NEXT: mul a1, a0, a3148; RV64I-SFBIMul-M-NEXT: .LBB1_2: # %entry149; RV64I-SFBIMul-M-NEXT: mv a0, a1150; RV64I-SFBIMul-M-NEXT: ret151entry:152 %res = mul i64 %a, %y153 %sel = select i1 %x, i64 %res, i64 %b154 ret i64 %sel155}156 157