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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32 %s3; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck -check-prefixes=RV64 %s4 5define i64 @test_clear_mask_i64_i32(i64 %x) nounwind {6; RV32-LABEL: test_clear_mask_i64_i32:7; RV32: # %bb.0: # %entry8; RV32-NEXT: bltz a0, .LBB0_29; RV32-NEXT: # %bb.1: # %t10; RV32-NEXT: li a1, 011; RV32-NEXT: li a0, 4212; RV32-NEXT: .LBB0_2: # %f13; RV32-NEXT: ret14;15; RV64-LABEL: test_clear_mask_i64_i32:16; RV64: # %bb.0: # %entry17; RV64-NEXT: slli a1, a0, 3218; RV64-NEXT: bltz a1, .LBB0_219; RV64-NEXT: # %bb.1: # %t20; RV64-NEXT: li a0, 4221; RV64-NEXT: .LBB0_2: # %f22; RV64-NEXT: ret23entry:24 %a = and i64 %x, 214748364825 %r = icmp eq i64 %a, 026 br i1 %r, label %t, label %f27t:28 br label %f29f:30 %ret = phi i64 [ %x, %entry], [ 42, %t]31 ret i64 %ret32}33 34define i64 @test_set_mask_i64_i32(i64 %x) nounwind {35; RV32-LABEL: test_set_mask_i64_i32:36; RV32: # %bb.0: # %entry37; RV32-NEXT: bgez a0, .LBB1_238; RV32-NEXT: # %bb.1: # %t39; RV32-NEXT: li a1, 040; RV32-NEXT: li a0, 4241; RV32-NEXT: .LBB1_2: # %f42; RV32-NEXT: ret43;44; RV64-LABEL: test_set_mask_i64_i32:45; RV64: # %bb.0: # %entry46; RV64-NEXT: slli a1, a0, 3247; RV64-NEXT: bgez a1, .LBB1_248; RV64-NEXT: # %bb.1: # %t49; RV64-NEXT: li a0, 4250; RV64-NEXT: .LBB1_2: # %f51; RV64-NEXT: ret52entry:53 %a = and i64 %x, 214748364854 %r = icmp ne i64 %a, 055 br i1 %r, label %t, label %f56t:57 br label %f58f:59 %ret = phi i64 [ %x, %entry], [ 42, %t]60 ret i64 %ret61}62 63define i64 @test_clear_mask_i64_i16(i64 %x) nounwind {64; RV32-LABEL: test_clear_mask_i64_i16:65; RV32: # %bb.0: # %entry66; RV32-NEXT: slli a2, a0, 1667; RV32-NEXT: bltz a2, .LBB2_268; RV32-NEXT: # %bb.1: # %t69; RV32-NEXT: li a1, 070; RV32-NEXT: li a0, 4271; RV32-NEXT: .LBB2_2: # %f72; RV32-NEXT: ret73;74; RV64-LABEL: test_clear_mask_i64_i16:75; RV64: # %bb.0: # %entry76; RV64-NEXT: slli a1, a0, 4877; RV64-NEXT: bltz a1, .LBB2_278; RV64-NEXT: # %bb.1: # %t79; RV64-NEXT: li a0, 4280; RV64-NEXT: .LBB2_2: # %f81; RV64-NEXT: ret82entry:83 %a = and i64 %x, 3276884 %r = icmp eq i64 %a, 085 br i1 %r, label %t, label %f86t:87 br label %f88f:89 %ret = phi i64 [ %x, %entry], [ 42, %t]90 ret i64 %ret91}92 93define i64 @test_set_mask_i64_i16(i64 %x) nounwind {94; RV32-LABEL: test_set_mask_i64_i16:95; RV32: # %bb.0: # %entry96; RV32-NEXT: slli a2, a0, 1697; RV32-NEXT: bgez a2, .LBB3_298; RV32-NEXT: # %bb.1: # %t99; RV32-NEXT: li a1, 0100; RV32-NEXT: li a0, 42101; RV32-NEXT: .LBB3_2: # %f102; RV32-NEXT: ret103;104; RV64-LABEL: test_set_mask_i64_i16:105; RV64: # %bb.0: # %entry106; RV64-NEXT: slli a1, a0, 48107; RV64-NEXT: bgez a1, .LBB3_2108; RV64-NEXT: # %bb.1: # %t109; RV64-NEXT: li a0, 42110; RV64-NEXT: .LBB3_2: # %f111; RV64-NEXT: ret112entry:113 %a = and i64 %x, 32768114 %r = icmp ne i64 %a, 0115 br i1 %r, label %t, label %f116t:117 br label %f118f:119 %ret = phi i64 [ %x, %entry], [ 42, %t]120 ret i64 %ret121}122 123define i64 @test_clear_mask_i64_i8(i64 %x) nounwind {124; RV32-LABEL: test_clear_mask_i64_i8:125; RV32: # %bb.0: # %entry126; RV32-NEXT: andi a2, a0, 128127; RV32-NEXT: bnez a2, .LBB4_2128; RV32-NEXT: # %bb.1: # %t129; RV32-NEXT: li a1, 0130; RV32-NEXT: li a0, 42131; RV32-NEXT: .LBB4_2: # %f132; RV32-NEXT: ret133;134; RV64-LABEL: test_clear_mask_i64_i8:135; RV64: # %bb.0: # %entry136; RV64-NEXT: andi a1, a0, 128137; RV64-NEXT: bnez a1, .LBB4_2138; RV64-NEXT: # %bb.1: # %t139; RV64-NEXT: li a0, 42140; RV64-NEXT: .LBB4_2: # %f141; RV64-NEXT: ret142entry:143 %a = and i64 %x, 128144 %r = icmp eq i64 %a, 0145 br i1 %r, label %t, label %f146t:147 br label %f148f:149 %ret = phi i64 [ %x, %entry], [ 42, %t]150 ret i64 %ret151}152 153define i64 @test_set_mask_i64_i8(i64 %x) nounwind {154; RV32-LABEL: test_set_mask_i64_i8:155; RV32: # %bb.0: # %entry156; RV32-NEXT: andi a2, a0, 128157; RV32-NEXT: beqz a2, .LBB5_2158; RV32-NEXT: # %bb.1: # %t159; RV32-NEXT: li a1, 0160; RV32-NEXT: li a0, 42161; RV32-NEXT: .LBB5_2: # %f162; RV32-NEXT: ret163;164; RV64-LABEL: test_set_mask_i64_i8:165; RV64: # %bb.0: # %entry166; RV64-NEXT: andi a1, a0, 128167; RV64-NEXT: beqz a1, .LBB5_2168; RV64-NEXT: # %bb.1: # %t169; RV64-NEXT: li a0, 42170; RV64-NEXT: .LBB5_2: # %f171; RV64-NEXT: ret172entry:173 %a = and i64 %x, 128174 %r = icmp ne i64 %a, 0175 br i1 %r, label %t, label %f176t:177 br label %f178f:179 %ret = phi i64 [ %x, %entry], [ 42, %t]180 ret i64 %ret181}182 183define i32 @test_clear_mask_i32_i16(i32 %x) nounwind {184; RV32-LABEL: test_clear_mask_i32_i16:185; RV32: # %bb.0: # %entry186; RV32-NEXT: slli a1, a0, 16187; RV32-NEXT: bltz a1, .LBB6_2188; RV32-NEXT: # %bb.1: # %t189; RV32-NEXT: li a0, 42190; RV32-NEXT: .LBB6_2: # %f191; RV32-NEXT: ret192;193; RV64-LABEL: test_clear_mask_i32_i16:194; RV64: # %bb.0: # %entry195; RV64-NEXT: slli a1, a0, 48196; RV64-NEXT: bltz a1, .LBB6_2197; RV64-NEXT: # %bb.1: # %t198; RV64-NEXT: li a0, 42199; RV64-NEXT: .LBB6_2: # %f200; RV64-NEXT: ret201entry:202 %a = and i32 %x, 32768203 %r = icmp eq i32 %a, 0204 br i1 %r, label %t, label %f205t:206 br label %f207f:208 %ret = phi i32 [ %x, %entry], [ 42, %t]209 ret i32 %ret210}211 212define i32 @test_set_mask_i32_i16(i32 %x) nounwind {213; RV32-LABEL: test_set_mask_i32_i16:214; RV32: # %bb.0: # %entry215; RV32-NEXT: slli a1, a0, 16216; RV32-NEXT: bgez a1, .LBB7_2217; RV32-NEXT: # %bb.1: # %t218; RV32-NEXT: li a0, 42219; RV32-NEXT: .LBB7_2: # %f220; RV32-NEXT: ret221;222; RV64-LABEL: test_set_mask_i32_i16:223; RV64: # %bb.0: # %entry224; RV64-NEXT: slli a1, a0, 48225; RV64-NEXT: bgez a1, .LBB7_2226; RV64-NEXT: # %bb.1: # %t227; RV64-NEXT: li a0, 42228; RV64-NEXT: .LBB7_2: # %f229; RV64-NEXT: ret230entry:231 %a = and i32 %x, 32768232 %r = icmp ne i32 %a, 0233 br i1 %r, label %t, label %f234t:235 br label %f236f:237 %ret = phi i32 [ %x, %entry], [ 42, %t]238 ret i32 %ret239}240 241define i32 @test_clear_mask_i32_i8(i32 %x) nounwind {242; RV32-LABEL: test_clear_mask_i32_i8:243; RV32: # %bb.0: # %entry244; RV32-NEXT: andi a1, a0, 128245; RV32-NEXT: bnez a1, .LBB8_2246; RV32-NEXT: # %bb.1: # %t247; RV32-NEXT: li a0, 42248; RV32-NEXT: .LBB8_2: # %f249; RV32-NEXT: ret250;251; RV64-LABEL: test_clear_mask_i32_i8:252; RV64: # %bb.0: # %entry253; RV64-NEXT: andi a1, a0, 128254; RV64-NEXT: bnez a1, .LBB8_2255; RV64-NEXT: # %bb.1: # %t256; RV64-NEXT: li a0, 42257; RV64-NEXT: .LBB8_2: # %f258; RV64-NEXT: ret259entry:260 %a = and i32 %x, 128261 %r = icmp eq i32 %a, 0262 br i1 %r, label %t, label %f263t:264 br label %f265f:266 %ret = phi i32 [ %x, %entry], [ 42, %t]267 ret i32 %ret268}269 270define i32 @test_set_mask_i32_i8(i32 %x) nounwind {271; RV32-LABEL: test_set_mask_i32_i8:272; RV32: # %bb.0: # %entry273; RV32-NEXT: andi a1, a0, 128274; RV32-NEXT: beqz a1, .LBB9_2275; RV32-NEXT: # %bb.1: # %t276; RV32-NEXT: li a0, 42277; RV32-NEXT: .LBB9_2: # %f278; RV32-NEXT: ret279;280; RV64-LABEL: test_set_mask_i32_i8:281; RV64: # %bb.0: # %entry282; RV64-NEXT: andi a1, a0, 128283; RV64-NEXT: beqz a1, .LBB9_2284; RV64-NEXT: # %bb.1: # %t285; RV64-NEXT: li a0, 42286; RV64-NEXT: .LBB9_2: # %f287; RV64-NEXT: ret288entry:289 %a = and i32 %x, 128290 %r = icmp ne i32 %a, 0291 br i1 %r, label %t, label %f292t:293 br label %f294f:295 %ret = phi i32 [ %x, %entry], [ 42, %t]296 ret i32 %ret297}298 299define i16 @test_clear_mask_i16_i8(i16 %x) nounwind {300; RV32-LABEL: test_clear_mask_i16_i8:301; RV32: # %bb.0: # %entry302; RV32-NEXT: andi a1, a0, 128303; RV32-NEXT: bnez a1, .LBB10_2304; RV32-NEXT: # %bb.1: # %t305; RV32-NEXT: li a0, 42306; RV32-NEXT: ret307; RV32-NEXT: .LBB10_2:308; RV32-NEXT: slli a0, a0, 16309; RV32-NEXT: srli a0, a0, 16310; RV32-NEXT: ret311;312; RV64-LABEL: test_clear_mask_i16_i8:313; RV64: # %bb.0: # %entry314; RV64-NEXT: andi a1, a0, 128315; RV64-NEXT: bnez a1, .LBB10_2316; RV64-NEXT: # %bb.1: # %t317; RV64-NEXT: li a0, 42318; RV64-NEXT: ret319; RV64-NEXT: .LBB10_2:320; RV64-NEXT: slli a0, a0, 48321; RV64-NEXT: srli a0, a0, 48322; RV64-NEXT: ret323entry:324 %a = and i16 %x, 128325 %r = icmp eq i16 %a, 0326 br i1 %r, label %t, label %f327t:328 br label %f329f:330 %ret = phi i16 [ %x, %entry], [ 42, %t]331 ret i16 %ret332}333 334define i16 @test_set_mask_i16_i8(i16 %x) nounwind {335; RV32-LABEL: test_set_mask_i16_i8:336; RV32: # %bb.0: # %entry337; RV32-NEXT: andi a1, a0, 128338; RV32-NEXT: beqz a1, .LBB11_2339; RV32-NEXT: # %bb.1: # %t340; RV32-NEXT: li a0, 42341; RV32-NEXT: ret342; RV32-NEXT: .LBB11_2:343; RV32-NEXT: slli a0, a0, 16344; RV32-NEXT: srli a0, a0, 16345; RV32-NEXT: ret346;347; RV64-LABEL: test_set_mask_i16_i8:348; RV64: # %bb.0: # %entry349; RV64-NEXT: andi a1, a0, 128350; RV64-NEXT: beqz a1, .LBB11_2351; RV64-NEXT: # %bb.1: # %t352; RV64-NEXT: li a0, 42353; RV64-NEXT: ret354; RV64-NEXT: .LBB11_2:355; RV64-NEXT: slli a0, a0, 48356; RV64-NEXT: srli a0, a0, 48357; RV64-NEXT: ret358entry:359 %a = and i16 %x, 128360 %r = icmp ne i16 %a, 0361 br i1 %r, label %t, label %f362t:363 br label %f364f:365 %ret = phi i16 [ %x, %entry], [ 42, %t]366 ret i16 %ret367}368 369define i16 @test_set_mask_i16_i7(i16 %x) nounwind {370; RV32-LABEL: test_set_mask_i16_i7:371; RV32: # %bb.0: # %entry372; RV32-NEXT: andi a1, a0, 64373; RV32-NEXT: beqz a1, .LBB12_2374; RV32-NEXT: # %bb.1: # %t375; RV32-NEXT: li a0, 42376; RV32-NEXT: ret377; RV32-NEXT: .LBB12_2:378; RV32-NEXT: slli a0, a0, 16379; RV32-NEXT: srli a0, a0, 16380; RV32-NEXT: ret381;382; RV64-LABEL: test_set_mask_i16_i7:383; RV64: # %bb.0: # %entry384; RV64-NEXT: andi a1, a0, 64385; RV64-NEXT: beqz a1, .LBB12_2386; RV64-NEXT: # %bb.1: # %t387; RV64-NEXT: li a0, 42388; RV64-NEXT: ret389; RV64-NEXT: .LBB12_2:390; RV64-NEXT: slli a0, a0, 48391; RV64-NEXT: srli a0, a0, 48392; RV64-NEXT: ret393entry:394 %a = and i16 %x, 64395 %r = icmp ne i16 %a, 0396 br i1 %r, label %t, label %f397t:398 br label %f399f:400 %ret = phi i16 [ %x, %entry], [ 42, %t]401 ret i16 %ret402}403