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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh -target-abi=lp64 \3; RUN: -verify-machineinstrs < %s \4; RUN: | FileCheck %s5 6define void @spill_half(ptr) nounwind {7; CHECK-LABEL: spill_half:8; CHECK: # %bb.0:9; CHECK-NEXT: addi sp, sp, -1610; CHECK-NEXT: flh fa5, 0(a0)11; CHECK-NEXT: fsh fa5, 14(sp) # 2-byte Folded Spill12; CHECK-NEXT: #APP13; CHECK-NEXT: #NO_APP14; CHECK-NEXT: flh fa5, 14(sp) # 2-byte Folded Reload15; CHECK-NEXT: fsh fa5, 0(a0)16; CHECK-NEXT: addi sp, sp, 1617; CHECK-NEXT: ret18 %2 = load volatile half, ptr %019 call void asm sideeffect "", "~{f0_d},~{f1_d},~{f2_d},~{f3_d},~{f4_d},~{f5_d},~{f6_d},~{f7_d},~{f8_d},~{f9_d},~{f10_d},~{f11_d},~{f12_d},~{f13_d},~{f14_d},~{f15_d},~{f16_d},~{f17_d},~{f18_d},~{f19_d},~{f20_d},~{f21_d},~{f22_d},~{f23_d},~{f24_d},~{f25_d},~{f26_d},~{f27_d},~{f28_d},~{f29_d},~{f30_d},~{f31_d}"()20 store volatile half %2, ptr %021 ret void22}23 24define void @spill_float(ptr) nounwind {25; CHECK-LABEL: spill_float:26; CHECK: # %bb.0:27; CHECK-NEXT: addi sp, sp, -1628; CHECK-NEXT: flw fa5, 0(a0)29; CHECK-NEXT: fsw fa5, 12(sp) # 4-byte Folded Spill30; CHECK-NEXT: #APP31; CHECK-NEXT: #NO_APP32; CHECK-NEXT: flw fa5, 12(sp) # 4-byte Folded Reload33; CHECK-NEXT: fsw fa5, 0(a0)34; CHECK-NEXT: addi sp, sp, 1635; CHECK-NEXT: ret36 %2 = load volatile float, ptr %037 call void asm sideeffect "", "~{f0_d},~{f1_d},~{f2_d},~{f3_d},~{f4_d},~{f5_d},~{f6_d},~{f7_d},~{f8_d},~{f9_d},~{f10_d},~{f11_d},~{f12_d},~{f13_d},~{f14_d},~{f15_d},~{f16_d},~{f17_d},~{f18_d},~{f19_d},~{f20_d},~{f21_d},~{f22_d},~{f23_d},~{f24_d},~{f25_d},~{f26_d},~{f27_d},~{f28_d},~{f29_d},~{f30_d},~{f31_d}"()38 store volatile float %2, ptr %039 ret void40}41 42define void @spill_double(ptr) nounwind {43; CHECK-LABEL: spill_double:44; CHECK: # %bb.0:45; CHECK-NEXT: addi sp, sp, -1646; CHECK-NEXT: fld fa5, 0(a0)47; CHECK-NEXT: fsd fa5, 8(sp) # 8-byte Folded Spill48; CHECK-NEXT: #APP49; CHECK-NEXT: #NO_APP50; CHECK-NEXT: fld fa5, 8(sp) # 8-byte Folded Reload51; CHECK-NEXT: fsd fa5, 0(a0)52; CHECK-NEXT: addi sp, sp, 1653; CHECK-NEXT: ret54 %2 = load volatile double, ptr %055 call void asm sideeffect "", "~{f0_d},~{f1_d},~{f2_d},~{f3_d},~{f4_d},~{f5_d},~{f6_d},~{f7_d},~{f8_d},~{f9_d},~{f10_d},~{f11_d},~{f12_d},~{f13_d},~{f14_d},~{f15_d},~{f16_d},~{f17_d},~{f18_d},~{f19_d},~{f20_d},~{f21_d},~{f22_d},~{f23_d},~{f24_d},~{f25_d},~{f26_d},~{f27_d},~{f28_d},~{f29_d},~{f30_d},~{f31_d}"()56 store volatile double %2, ptr %057 ret void58}59