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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefixes=RV32-RV64,RV324; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefixes=RV32D-RV64D,RV32D6; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \7; RUN: | FileCheck %s -check-prefixes=RV32-RV64,RV648; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \9; RUN: | FileCheck %s -check-prefixes=RV32D-RV64D,RV64D10 11define void @int32_float_pair(i32 %tmp1, float %tmp2, ptr %ref.tmp) {12; RV32-RV64-LABEL: int32_float_pair:13; RV32-RV64: # %bb.0:14; RV32-RV64-NEXT: sw a0, 0(a2)15; RV32-RV64-NEXT: sw a1, 4(a2)16; RV32-RV64-NEXT: ret17;18; RV32D-RV64D-LABEL: int32_float_pair:19; RV32D-RV64D: # %bb.0:20; RV32D-RV64D-NEXT: sw a0, 0(a1)21; RV32D-RV64D-NEXT: fsw fa0, 4(a1)22; RV32D-RV64D-NEXT: ret23 %t0 = bitcast float %tmp2 to i3224 %t1 = zext i32 %t0 to i6425 %t2 = shl nuw i64 %t1, 3226 %t3 = zext i32 %tmp1 to i6427 %t4 = or i64 %t2, %t328 store i64 %t4, ptr %ref.tmp, align 829 ret void30}31 32define void @float_int32_pair(float %tmp1, i32 %tmp2, ptr %ref.tmp) {33; RV32-RV64-LABEL: float_int32_pair:34; RV32-RV64: # %bb.0:35; RV32-RV64-NEXT: sw a0, 0(a2)36; RV32-RV64-NEXT: sw a1, 4(a2)37; RV32-RV64-NEXT: ret38;39; RV32D-RV64D-LABEL: float_int32_pair:40; RV32D-RV64D: # %bb.0:41; RV32D-RV64D-NEXT: fsw fa0, 0(a1)42; RV32D-RV64D-NEXT: sw a0, 4(a1)43; RV32D-RV64D-NEXT: ret44 %t0 = bitcast float %tmp1 to i3245 %t1 = zext i32 %tmp2 to i6446 %t2 = shl nuw i64 %t1, 3247 %t3 = zext i32 %t0 to i6448 %t4 = or i64 %t2, %t349 store i64 %t4, ptr %ref.tmp, align 850 ret void51}52 53define void @int16_float_pair(i16 signext %tmp1, float %tmp2, ptr %ref.tmp) {54; RV32-LABEL: int16_float_pair:55; RV32: # %bb.0:56; RV32-NEXT: slli a0, a0, 1657; RV32-NEXT: srli a0, a0, 1658; RV32-NEXT: sw a0, 0(a2)59; RV32-NEXT: sw a1, 4(a2)60; RV32-NEXT: ret61;62; RV32D-LABEL: int16_float_pair:63; RV32D: # %bb.0:64; RV32D-NEXT: slli a0, a0, 1665; RV32D-NEXT: srli a0, a0, 1666; RV32D-NEXT: sw a0, 0(a1)67; RV32D-NEXT: fsw fa0, 4(a1)68; RV32D-NEXT: ret69;70; RV64-LABEL: int16_float_pair:71; RV64: # %bb.0:72; RV64-NEXT: slli a0, a0, 4873; RV64-NEXT: srli a0, a0, 4874; RV64-NEXT: sw a0, 0(a2)75; RV64-NEXT: sw a1, 4(a2)76; RV64-NEXT: ret77;78; RV64D-LABEL: int16_float_pair:79; RV64D: # %bb.0:80; RV64D-NEXT: slli a0, a0, 4881; RV64D-NEXT: srli a0, a0, 4882; RV64D-NEXT: sw a0, 0(a1)83; RV64D-NEXT: fsw fa0, 4(a1)84; RV64D-NEXT: ret85 %t0 = bitcast float %tmp2 to i3286 %t1 = zext i32 %t0 to i6487 %t2 = shl nuw i64 %t1, 3288 %t3 = zext i16 %tmp1 to i6489 %t4 = or i64 %t2, %t390 store i64 %t4, ptr %ref.tmp, align 891 ret void92}93 94define void @int8_float_pair(i8 signext %tmp1, float %tmp2, ptr %ref.tmp) {95; RV32-RV64-LABEL: int8_float_pair:96; RV32-RV64: # %bb.0:97; RV32-RV64-NEXT: zext.b a0, a098; RV32-RV64-NEXT: sw a0, 0(a2)99; RV32-RV64-NEXT: sw a1, 4(a2)100; RV32-RV64-NEXT: ret101;102; RV32D-RV64D-LABEL: int8_float_pair:103; RV32D-RV64D: # %bb.0:104; RV32D-RV64D-NEXT: zext.b a0, a0105; RV32D-RV64D-NEXT: sw a0, 0(a1)106; RV32D-RV64D-NEXT: fsw fa0, 4(a1)107; RV32D-RV64D-NEXT: ret108 %t0 = bitcast float %tmp2 to i32109 %t1 = zext i32 %t0 to i64110 %t2 = shl nuw i64 %t1, 32111 %t3 = zext i8 %tmp1 to i64112 %t4 = or i64 %t2, %t3113 store i64 %t4, ptr %ref.tmp, align 8114 ret void115}116 117define void @int32_int32_pair(i32 %tmp1, i32 %tmp2, ptr %ref.tmp) {118; RV32-LABEL: int32_int32_pair:119; RV32: # %bb.0:120; RV32-NEXT: sw a0, 0(a2)121; RV32-NEXT: sw a1, 4(a2)122; RV32-NEXT: ret123;124; RV32D-LABEL: int32_int32_pair:125; RV32D: # %bb.0:126; RV32D-NEXT: sw a0, 0(a2)127; RV32D-NEXT: sw a1, 4(a2)128; RV32D-NEXT: ret129;130; RV64-LABEL: int32_int32_pair:131; RV64: # %bb.0:132; RV64-NEXT: slli a1, a1, 32133; RV64-NEXT: slli a0, a0, 32134; RV64-NEXT: srli a0, a0, 32135; RV64-NEXT: or a0, a1, a0136; RV64-NEXT: sd a0, 0(a2)137; RV64-NEXT: ret138;139; RV64D-LABEL: int32_int32_pair:140; RV64D: # %bb.0:141; RV64D-NEXT: slli a1, a1, 32142; RV64D-NEXT: slli a0, a0, 32143; RV64D-NEXT: srli a0, a0, 32144; RV64D-NEXT: or a0, a1, a0145; RV64D-NEXT: sd a0, 0(a2)146; RV64D-NEXT: ret147 %t1 = zext i32 %tmp2 to i64148 %t2 = shl nuw i64 %t1, 32149 %t3 = zext i32 %tmp1 to i64150 %t4 = or i64 %t2, %t3151 store i64 %t4, ptr %ref.tmp, align 8152 ret void153}154 155define void @mbb_int32_float_pair(i32 %tmp1, float %tmp2, ptr %ref.tmp) {156; RV32-RV64-LABEL: mbb_int32_float_pair:157; RV32-RV64: # %bb.0: # %entry158; RV32-RV64-NEXT: sw a0, 0(a2)159; RV32-RV64-NEXT: sw a1, 4(a2)160; RV32-RV64-NEXT: ret161;162; RV32D-RV64D-LABEL: mbb_int32_float_pair:163; RV32D-RV64D: # %bb.0: # %entry164; RV32D-RV64D-NEXT: sw a0, 0(a1)165; RV32D-RV64D-NEXT: fsw fa0, 4(a1)166; RV32D-RV64D-NEXT: ret167entry:168 %t0 = bitcast float %tmp2 to i32169 br label %next170next:171 %t1 = zext i32 %t0 to i64172 %t2 = shl nuw i64 %t1, 32173 %t3 = zext i32 %tmp1 to i64174 %t4 = or i64 %t2, %t3175 store i64 %t4, ptr %ref.tmp, align 8176 ret void177}178 179define void @mbb_int32_float_multi_stores(i32 %tmp1, float %tmp2, ptr %ref.tmp, ptr %ref.tmp1, i1 %cmp) {180; RV32-RV64-LABEL: mbb_int32_float_multi_stores:181; RV32-RV64: # %bb.0: # %entry182; RV32-RV64-NEXT: andi a4, a4, 1183; RV32-RV64-NEXT: sw a0, 0(a2)184; RV32-RV64-NEXT: sw a1, 4(a2)185; RV32-RV64-NEXT: beqz a4, .LBB6_2186; RV32-RV64-NEXT: # %bb.1: # %bb2187; RV32-RV64-NEXT: sw a0, 0(a3)188; RV32-RV64-NEXT: sw a1, 4(a3)189; RV32-RV64-NEXT: .LBB6_2: # %exitbb190; RV32-RV64-NEXT: ret191;192; RV32D-RV64D-LABEL: mbb_int32_float_multi_stores:193; RV32D-RV64D: # %bb.0: # %entry194; RV32D-RV64D-NEXT: andi a3, a3, 1195; RV32D-RV64D-NEXT: sw a0, 0(a1)196; RV32D-RV64D-NEXT: fsw fa0, 4(a1)197; RV32D-RV64D-NEXT: beqz a3, .LBB6_2198; RV32D-RV64D-NEXT: # %bb.1: # %bb2199; RV32D-RV64D-NEXT: sw a0, 0(a2)200; RV32D-RV64D-NEXT: fsw fa0, 4(a2)201; RV32D-RV64D-NEXT: .LBB6_2: # %exitbb202; RV32D-RV64D-NEXT: ret203entry:204 %t0 = bitcast float %tmp2 to i32205 br label %bb1206bb1:207 %t1 = zext i32 %t0 to i64208 %t2 = shl nuw i64 %t1, 32209 %t3 = zext i32 %tmp1 to i64210 %t4 = or i64 %t2, %t3211 store i64 %t4, ptr %ref.tmp, align 8212 br i1 %cmp, label %bb2, label %exitbb213bb2:214 store i64 %t4, ptr %ref.tmp1, align 8215 br label %exitbb216exitbb:217 ret void218}219