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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen2/i64/g' %s | llc -mtriple=riscv32 -mattr=+m | \3; RUN: FileCheck %s --check-prefix=RV324; RUN: sed 's/iXLen2/i128/g' %s | llc -mtriple=riscv64 -mattr=+m | \5; RUN: FileCheck %s --check-prefix=RV646 7define iXLen2 @test_udiv_3(iXLen2 %x) nounwind {8; RV32-LABEL: test_udiv_3:9; RV32: # %bb.0:10; RV32-NEXT: add a2, a0, a111; RV32-NEXT: lui a3, 69905112; RV32-NEXT: sltu a4, a2, a013; RV32-NEXT: addi a5, a3, -136514; RV32-NEXT: addi a3, a3, -136615; RV32-NEXT: add a2, a2, a416; RV32-NEXT: mulhu a4, a2, a517; RV32-NEXT: srli a6, a4, 118; RV32-NEXT: andi a4, a4, -219; RV32-NEXT: add a4, a4, a620; RV32-NEXT: sub a2, a2, a421; RV32-NEXT: sub a4, a0, a222; RV32-NEXT: sltu a0, a0, a223; RV32-NEXT: mul a2, a4, a324; RV32-NEXT: mulhu a3, a4, a525; RV32-NEXT: sub a1, a1, a026; RV32-NEXT: add a2, a3, a227; RV32-NEXT: mul a1, a1, a528; RV32-NEXT: add a1, a2, a129; RV32-NEXT: mul a0, a4, a530; RV32-NEXT: ret31;32; RV64-LABEL: test_udiv_3:33; RV64: # %bb.0:34; RV64-NEXT: add a2, a0, a135; RV64-NEXT: lui a3, 69905136; RV64-NEXT: lui a4, %hi(.LCPI0_0)37; RV64-NEXT: sltu a5, a2, a038; RV64-NEXT: addi a3, a3, -136539; RV64-NEXT: ld a4, %lo(.LCPI0_0)(a4)40; RV64-NEXT: add a2, a2, a541; RV64-NEXT: slli a5, a3, 3242; RV64-NEXT: add a3, a3, a543; RV64-NEXT: mulhu a5, a2, a344; RV64-NEXT: srli a6, a5, 145; RV64-NEXT: andi a5, a5, -246; RV64-NEXT: add a5, a5, a647; RV64-NEXT: sub a2, a2, a548; RV64-NEXT: sub a5, a0, a249; RV64-NEXT: sltu a0, a0, a250; RV64-NEXT: mul a2, a5, a451; RV64-NEXT: mulhu a4, a5, a352; RV64-NEXT: sub a1, a1, a053; RV64-NEXT: add a2, a4, a254; RV64-NEXT: mul a1, a1, a355; RV64-NEXT: add a1, a2, a156; RV64-NEXT: mul a0, a5, a357; RV64-NEXT: ret58 %a = udiv iXLen2 %x, 359 ret iXLen2 %a60}61 62define iXLen2 @test_udiv_5(iXLen2 %x) nounwind {63; RV32-LABEL: test_udiv_5:64; RV32: # %bb.0:65; RV32-NEXT: add a2, a0, a166; RV32-NEXT: lui a3, 83886167; RV32-NEXT: sltu a4, a2, a068; RV32-NEXT: addi a5, a3, -81969; RV32-NEXT: addi a3, a3, -82070; RV32-NEXT: add a2, a2, a471; RV32-NEXT: mulhu a4, a2, a572; RV32-NEXT: srli a6, a4, 273; RV32-NEXT: andi a4, a4, -474; RV32-NEXT: add a4, a4, a675; RV32-NEXT: sub a2, a2, a476; RV32-NEXT: sub a4, a0, a277; RV32-NEXT: sltu a0, a0, a278; RV32-NEXT: mul a2, a4, a379; RV32-NEXT: mulhu a3, a4, a580; RV32-NEXT: sub a1, a1, a081; RV32-NEXT: add a2, a3, a282; RV32-NEXT: mul a1, a1, a583; RV32-NEXT: add a1, a2, a184; RV32-NEXT: mul a0, a4, a585; RV32-NEXT: ret86;87; RV64-LABEL: test_udiv_5:88; RV64: # %bb.0:89; RV64-NEXT: add a2, a0, a190; RV64-NEXT: lui a3, 83886191; RV64-NEXT: lui a4, %hi(.LCPI1_0)92; RV64-NEXT: sltu a5, a2, a093; RV64-NEXT: addi a3, a3, -81994; RV64-NEXT: ld a4, %lo(.LCPI1_0)(a4)95; RV64-NEXT: add a2, a2, a596; RV64-NEXT: slli a5, a3, 3297; RV64-NEXT: add a3, a3, a598; RV64-NEXT: mulhu a5, a2, a399; RV64-NEXT: srli a6, a5, 2100; RV64-NEXT: andi a5, a5, -4101; RV64-NEXT: add a5, a5, a6102; RV64-NEXT: sub a2, a2, a5103; RV64-NEXT: sub a5, a0, a2104; RV64-NEXT: sltu a0, a0, a2105; RV64-NEXT: mul a2, a5, a4106; RV64-NEXT: mulhu a4, a5, a3107; RV64-NEXT: sub a1, a1, a0108; RV64-NEXT: add a2, a4, a2109; RV64-NEXT: mul a1, a1, a3110; RV64-NEXT: add a1, a2, a1111; RV64-NEXT: mul a0, a5, a3112; RV64-NEXT: ret113 %a = udiv iXLen2 %x, 5114 ret iXLen2 %a115}116 117define iXLen2 @test_udiv_7(iXLen2 %x) nounwind {118; RV32-LABEL: test_udiv_7:119; RV32: # %bb.0:120; RV32-NEXT: addi sp, sp, -16121; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill122; RV32-NEXT: li a2, 7123; RV32-NEXT: li a3, 0124; RV32-NEXT: call __udivdi3125; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload126; RV32-NEXT: addi sp, sp, 16127; RV32-NEXT: ret128;129; RV64-LABEL: test_udiv_7:130; RV64: # %bb.0:131; RV64-NEXT: addi sp, sp, -16132; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill133; RV64-NEXT: li a2, 7134; RV64-NEXT: li a3, 0135; RV64-NEXT: call __udivti3136; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload137; RV64-NEXT: addi sp, sp, 16138; RV64-NEXT: ret139 %a = udiv iXLen2 %x, 7140 ret iXLen2 %a141}142 143define iXLen2 @test_udiv_9(iXLen2 %x) nounwind {144; RV32-LABEL: test_udiv_9:145; RV32: # %bb.0:146; RV32-NEXT: addi sp, sp, -16147; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill148; RV32-NEXT: li a2, 9149; RV32-NEXT: li a3, 0150; RV32-NEXT: call __udivdi3151; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload152; RV32-NEXT: addi sp, sp, 16153; RV32-NEXT: ret154;155; RV64-LABEL: test_udiv_9:156; RV64: # %bb.0:157; RV64-NEXT: addi sp, sp, -16158; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill159; RV64-NEXT: li a2, 9160; RV64-NEXT: li a3, 0161; RV64-NEXT: call __udivti3162; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload163; RV64-NEXT: addi sp, sp, 16164; RV64-NEXT: ret165 %a = udiv iXLen2 %x, 9166 ret iXLen2 %a167}168 169define iXLen2 @test_udiv_15(iXLen2 %x) nounwind {170; RV32-LABEL: test_udiv_15:171; RV32: # %bb.0:172; RV32-NEXT: add a2, a0, a1173; RV32-NEXT: lui a3, 559241174; RV32-NEXT: lui a4, 978671175; RV32-NEXT: sltu a5, a2, a0176; RV32-NEXT: addi a3, a3, -1911177; RV32-NEXT: addi a6, a4, -274178; RV32-NEXT: addi a4, a4, -273179; RV32-NEXT: add a2, a2, a5180; RV32-NEXT: mulhu a3, a2, a3181; RV32-NEXT: srli a3, a3, 3182; RV32-NEXT: slli a5, a3, 4183; RV32-NEXT: sub a3, a3, a5184; RV32-NEXT: add a2, a2, a3185; RV32-NEXT: sub a3, a0, a2186; RV32-NEXT: sltu a0, a0, a2187; RV32-NEXT: mul a2, a3, a6188; RV32-NEXT: mulhu a5, a3, a4189; RV32-NEXT: sub a1, a1, a0190; RV32-NEXT: add a2, a5, a2191; RV32-NEXT: mul a1, a1, a4192; RV32-NEXT: add a1, a2, a1193; RV32-NEXT: mul a0, a3, a4194; RV32-NEXT: ret195;196; RV64-LABEL: test_udiv_15:197; RV64: # %bb.0:198; RV64-NEXT: add a2, a0, a1199; RV64-NEXT: lui a3, 559241200; RV64-NEXT: lui a4, %hi(.LCPI4_0)201; RV64-NEXT: lui a5, 978671202; RV64-NEXT: sltu a6, a2, a0203; RV64-NEXT: addi a3, a3, -1911204; RV64-NEXT: ld a4, %lo(.LCPI4_0)(a4)205; RV64-NEXT: addi a5, a5, -273206; RV64-NEXT: add a2, a2, a6207; RV64-NEXT: slli a6, a3, 32208; RV64-NEXT: add a3, a3, a6209; RV64-NEXT: slli a6, a5, 32210; RV64-NEXT: add a5, a5, a6211; RV64-NEXT: mulhu a3, a2, a3212; RV64-NEXT: srli a3, a3, 3213; RV64-NEXT: slli a6, a3, 4214; RV64-NEXT: sub a3, a3, a6215; RV64-NEXT: add a2, a2, a3216; RV64-NEXT: sub a3, a0, a2217; RV64-NEXT: sltu a0, a0, a2218; RV64-NEXT: mul a2, a3, a4219; RV64-NEXT: mulhu a4, a3, a5220; RV64-NEXT: sub a1, a1, a0221; RV64-NEXT: add a2, a4, a2222; RV64-NEXT: mul a1, a1, a5223; RV64-NEXT: add a1, a2, a1224; RV64-NEXT: mul a0, a3, a5225; RV64-NEXT: ret226 %a = udiv iXLen2 %x, 15227 ret iXLen2 %a228}229 230define iXLen2 @test_udiv_17(iXLen2 %x) nounwind {231; RV32-LABEL: test_udiv_17:232; RV32: # %bb.0:233; RV32-NEXT: add a2, a0, a1234; RV32-NEXT: lui a3, 986895235; RV32-NEXT: sltu a4, a2, a0236; RV32-NEXT: addi a5, a3, 241237; RV32-NEXT: addi a3, a3, 240238; RV32-NEXT: add a2, a2, a4239; RV32-NEXT: mulhu a4, a2, a5240; RV32-NEXT: srli a6, a4, 4241; RV32-NEXT: andi a4, a4, -16242; RV32-NEXT: add a4, a4, a6243; RV32-NEXT: sub a2, a2, a4244; RV32-NEXT: sub a4, a0, a2245; RV32-NEXT: sltu a0, a0, a2246; RV32-NEXT: mul a2, a4, a3247; RV32-NEXT: mulhu a3, a4, a5248; RV32-NEXT: sub a1, a1, a0249; RV32-NEXT: add a2, a3, a2250; RV32-NEXT: mul a1, a1, a5251; RV32-NEXT: add a1, a2, a1252; RV32-NEXT: mul a0, a4, a5253; RV32-NEXT: ret254;255; RV64-LABEL: test_udiv_17:256; RV64: # %bb.0:257; RV64-NEXT: add a2, a0, a1258; RV64-NEXT: lui a3, 986895259; RV64-NEXT: lui a4, %hi(.LCPI5_0)260; RV64-NEXT: sltu a5, a2, a0261; RV64-NEXT: addi a3, a3, 241262; RV64-NEXT: ld a4, %lo(.LCPI5_0)(a4)263; RV64-NEXT: add a2, a2, a5264; RV64-NEXT: slli a5, a3, 32265; RV64-NEXT: add a3, a3, a5266; RV64-NEXT: mulhu a5, a2, a3267; RV64-NEXT: srli a6, a5, 4268; RV64-NEXT: andi a5, a5, -16269; RV64-NEXT: add a5, a5, a6270; RV64-NEXT: sub a2, a2, a5271; RV64-NEXT: sub a5, a0, a2272; RV64-NEXT: sltu a0, a0, a2273; RV64-NEXT: mul a2, a5, a4274; RV64-NEXT: mulhu a4, a5, a3275; RV64-NEXT: sub a1, a1, a0276; RV64-NEXT: add a2, a4, a2277; RV64-NEXT: mul a1, a1, a3278; RV64-NEXT: add a1, a2, a1279; RV64-NEXT: mul a0, a5, a3280; RV64-NEXT: ret281 %a = udiv iXLen2 %x, 17282 ret iXLen2 %a283}284 285define iXLen2 @test_udiv_255(iXLen2 %x) nounwind {286; RV32-LABEL: test_udiv_255:287; RV32: # %bb.0:288; RV32-NEXT: add a2, a0, a1289; RV32-NEXT: lui a3, 526344290; RV32-NEXT: lui a4, 1044464291; RV32-NEXT: sltu a5, a2, a0292; RV32-NEXT: addi a3, a3, 129293; RV32-NEXT: addi a6, a4, -258294; RV32-NEXT: addi a4, a4, -257295; RV32-NEXT: add a2, a2, a5296; RV32-NEXT: mulhu a3, a2, a3297; RV32-NEXT: srli a3, a3, 7298; RV32-NEXT: slli a5, a3, 8299; RV32-NEXT: sub a3, a3, a5300; RV32-NEXT: add a2, a2, a3301; RV32-NEXT: sub a3, a0, a2302; RV32-NEXT: sltu a0, a0, a2303; RV32-NEXT: mul a2, a3, a6304; RV32-NEXT: mulhu a5, a3, a4305; RV32-NEXT: sub a1, a1, a0306; RV32-NEXT: add a2, a5, a2307; RV32-NEXT: mul a1, a1, a4308; RV32-NEXT: add a1, a2, a1309; RV32-NEXT: mul a0, a3, a4310; RV32-NEXT: ret311;312; RV64-LABEL: test_udiv_255:313; RV64: # %bb.0:314; RV64-NEXT: add a2, a0, a1315; RV64-NEXT: lui a3, 526344316; RV64-NEXT: lui a4, %hi(.LCPI6_0)317; RV64-NEXT: lui a5, 1044464318; RV64-NEXT: sltu a6, a2, a0319; RV64-NEXT: addi a3, a3, 129320; RV64-NEXT: ld a4, %lo(.LCPI6_0)(a4)321; RV64-NEXT: addi a5, a5, -257322; RV64-NEXT: add a2, a2, a6323; RV64-NEXT: slli a6, a3, 32324; RV64-NEXT: add a3, a3, a6325; RV64-NEXT: slli a6, a5, 32326; RV64-NEXT: add a5, a5, a6327; RV64-NEXT: mulhu a3, a2, a3328; RV64-NEXT: srli a3, a3, 7329; RV64-NEXT: slli a6, a3, 8330; RV64-NEXT: sub a3, a3, a6331; RV64-NEXT: add a2, a2, a3332; RV64-NEXT: sub a3, a0, a2333; RV64-NEXT: sltu a0, a0, a2334; RV64-NEXT: mul a2, a3, a4335; RV64-NEXT: mulhu a4, a3, a5336; RV64-NEXT: sub a1, a1, a0337; RV64-NEXT: add a2, a4, a2338; RV64-NEXT: mul a1, a1, a5339; RV64-NEXT: add a1, a2, a1340; RV64-NEXT: mul a0, a3, a5341; RV64-NEXT: ret342 %a = udiv iXLen2 %x, 255343 ret iXLen2 %a344}345 346define iXLen2 @test_udiv_257(iXLen2 %x) nounwind {347; RV32-LABEL: test_udiv_257:348; RV32: # %bb.0:349; RV32-NEXT: add a2, a0, a1350; RV32-NEXT: lui a3, 1044496351; RV32-NEXT: sltu a4, a2, a0352; RV32-NEXT: addi a5, a3, -255353; RV32-NEXT: addi a3, a3, -256354; RV32-NEXT: add a2, a2, a4355; RV32-NEXT: mulhu a4, a2, a5356; RV32-NEXT: srli a6, a4, 8357; RV32-NEXT: andi a4, a4, -256358; RV32-NEXT: add a4, a4, a6359; RV32-NEXT: sub a2, a2, a4360; RV32-NEXT: sub a4, a0, a2361; RV32-NEXT: sltu a0, a0, a2362; RV32-NEXT: mul a2, a4, a3363; RV32-NEXT: mulhu a3, a4, a5364; RV32-NEXT: sub a1, a1, a0365; RV32-NEXT: add a2, a3, a2366; RV32-NEXT: mul a1, a1, a5367; RV32-NEXT: add a1, a2, a1368; RV32-NEXT: mul a0, a4, a5369; RV32-NEXT: ret370;371; RV64-LABEL: test_udiv_257:372; RV64: # %bb.0:373; RV64-NEXT: add a2, a0, a1374; RV64-NEXT: lui a3, 1044496375; RV64-NEXT: lui a4, %hi(.LCPI7_0)376; RV64-NEXT: sltu a5, a2, a0377; RV64-NEXT: addi a3, a3, -255378; RV64-NEXT: ld a4, %lo(.LCPI7_0)(a4)379; RV64-NEXT: add a2, a2, a5380; RV64-NEXT: slli a5, a3, 32381; RV64-NEXT: add a3, a3, a5382; RV64-NEXT: mulhu a5, a2, a3383; RV64-NEXT: srli a6, a5, 8384; RV64-NEXT: andi a5, a5, -256385; RV64-NEXT: add a5, a5, a6386; RV64-NEXT: sub a2, a2, a5387; RV64-NEXT: sub a5, a0, a2388; RV64-NEXT: sltu a0, a0, a2389; RV64-NEXT: mul a2, a5, a4390; RV64-NEXT: mulhu a4, a5, a3391; RV64-NEXT: sub a1, a1, a0392; RV64-NEXT: add a2, a4, a2393; RV64-NEXT: mul a1, a1, a3394; RV64-NEXT: add a1, a2, a1395; RV64-NEXT: mul a0, a5, a3396; RV64-NEXT: ret397 %a = udiv iXLen2 %x, 257398 ret iXLen2 %a399}400 401define iXLen2 @test_udiv_65535(iXLen2 %x) nounwind {402; RV32-LABEL: test_udiv_65535:403; RV32: # %bb.0:404; RV32-NEXT: add a2, a0, a1405; RV32-NEXT: lui a3, 524296406; RV32-NEXT: lui a4, 1048560407; RV32-NEXT: sltu a5, a2, a0408; RV32-NEXT: addi a3, a3, 1409; RV32-NEXT: add a2, a2, a5410; RV32-NEXT: mulhu a3, a2, a3411; RV32-NEXT: srli a3, a3, 15412; RV32-NEXT: slli a5, a3, 16413; RV32-NEXT: sub a3, a3, a5414; RV32-NEXT: addi a5, a4, -2415; RV32-NEXT: addi a4, a4, -1416; RV32-NEXT: add a2, a2, a3417; RV32-NEXT: sub a3, a0, a2418; RV32-NEXT: sltu a0, a0, a2419; RV32-NEXT: mul a2, a3, a5420; RV32-NEXT: mulhu a4, a3, a4421; RV32-NEXT: sub a1, a1, a0422; RV32-NEXT: slli a0, a3, 16423; RV32-NEXT: neg a3, a3424; RV32-NEXT: add a2, a4, a2425; RV32-NEXT: slli a4, a1, 16426; RV32-NEXT: add a1, a4, a1427; RV32-NEXT: sub a1, a2, a1428; RV32-NEXT: sub a0, a3, a0429; RV32-NEXT: ret430;431; RV64-LABEL: test_udiv_65535:432; RV64: # %bb.0:433; RV64-NEXT: add a2, a0, a1434; RV64-NEXT: lui a3, 524296435; RV64-NEXT: lui a4, 983039436; RV64-NEXT: lui a5, 1048560437; RV64-NEXT: sltu a6, a2, a0438; RV64-NEXT: addi a3, a3, 1439; RV64-NEXT: slli a4, a4, 4440; RV64-NEXT: addi a5, a5, -1441; RV64-NEXT: add a2, a2, a6442; RV64-NEXT: slli a6, a3, 32443; RV64-NEXT: addi a4, a4, -1444; RV64-NEXT: add a3, a3, a6445; RV64-NEXT: slli a6, a5, 32446; RV64-NEXT: slli a4, a4, 16447; RV64-NEXT: add a5, a5, a6448; RV64-NEXT: mulhu a3, a2, a3449; RV64-NEXT: addi a4, a4, -2450; RV64-NEXT: srli a3, a3, 15451; RV64-NEXT: slli a6, a3, 16452; RV64-NEXT: sub a3, a3, a6453; RV64-NEXT: add a2, a2, a3454; RV64-NEXT: sub a3, a0, a2455; RV64-NEXT: sltu a0, a0, a2456; RV64-NEXT: mul a2, a3, a4457; RV64-NEXT: mulhu a4, a3, a5458; RV64-NEXT: sub a1, a1, a0459; RV64-NEXT: add a2, a4, a2460; RV64-NEXT: mul a1, a1, a5461; RV64-NEXT: add a1, a2, a1462; RV64-NEXT: mul a0, a3, a5463; RV64-NEXT: ret464 %a = udiv iXLen2 %x, 65535465 ret iXLen2 %a466}467 468define iXLen2 @test_udiv_65537(iXLen2 %x) nounwind {469; RV32-LABEL: test_udiv_65537:470; RV32: # %bb.0:471; RV32-NEXT: add a2, a0, a1472; RV32-NEXT: lui a3, 1048560473; RV32-NEXT: sltu a4, a2, a0474; RV32-NEXT: addi a5, a3, 1475; RV32-NEXT: add a2, a2, a4476; RV32-NEXT: mulhu a4, a2, a5477; RV32-NEXT: and a3, a4, a3478; RV32-NEXT: srli a4, a4, 16479; RV32-NEXT: or a3, a3, a4480; RV32-NEXT: sub a2, a2, a3481; RV32-NEXT: sub a3, a0, a2482; RV32-NEXT: sltu a0, a0, a2483; RV32-NEXT: mulhu a2, a3, a5484; RV32-NEXT: slli a4, a3, 16485; RV32-NEXT: sub a1, a1, a0486; RV32-NEXT: sub a2, a2, a4487; RV32-NEXT: slli a0, a1, 16488; RV32-NEXT: sub a1, a1, a0489; RV32-NEXT: add a1, a2, a1490; RV32-NEXT: sub a0, a3, a4491; RV32-NEXT: ret492;493; RV64-LABEL: test_udiv_65537:494; RV64: # %bb.0:495; RV64-NEXT: add a2, a0, a1496; RV64-NEXT: lui a3, 1048560497; RV64-NEXT: lui a4, 983041498; RV64-NEXT: sltu a5, a2, a0499; RV64-NEXT: addi a6, a3, 1500; RV64-NEXT: slli a4, a4, 4501; RV64-NEXT: add a2, a2, a5502; RV64-NEXT: slli a5, a6, 32503; RV64-NEXT: addi a4, a4, -1504; RV64-NEXT: add a5, a6, a5505; RV64-NEXT: slli a4, a4, 16506; RV64-NEXT: mulhu a6, a2, a5507; RV64-NEXT: and a3, a6, a3508; RV64-NEXT: srli a6, a6, 16509; RV64-NEXT: add a3, a3, a6510; RV64-NEXT: sub a2, a2, a3511; RV64-NEXT: sub a3, a0, a2512; RV64-NEXT: sltu a0, a0, a2513; RV64-NEXT: mul a2, a3, a4514; RV64-NEXT: mulhu a4, a3, a5515; RV64-NEXT: sub a1, a1, a0516; RV64-NEXT: add a2, a4, a2517; RV64-NEXT: mul a1, a1, a5518; RV64-NEXT: add a1, a2, a1519; RV64-NEXT: mul a0, a3, a5520; RV64-NEXT: ret521 %a = udiv iXLen2 %x, 65537522 ret iXLen2 %a523}524 525define iXLen2 @test_udiv_12(iXLen2 %x) nounwind {526; RV32-LABEL: test_udiv_12:527; RV32: # %bb.0:528; RV32-NEXT: slli a2, a1, 30529; RV32-NEXT: srli a0, a0, 2530; RV32-NEXT: srli a1, a1, 2531; RV32-NEXT: lui a3, 699051532; RV32-NEXT: or a0, a0, a2533; RV32-NEXT: addi a2, a3, -1365534; RV32-NEXT: addi a3, a3, -1366535; RV32-NEXT: add a4, a0, a1536; RV32-NEXT: sltu a5, a4, a0537; RV32-NEXT: add a4, a4, a5538; RV32-NEXT: mulhu a5, a4, a2539; RV32-NEXT: srli a6, a5, 1540; RV32-NEXT: andi a5, a5, -2541; RV32-NEXT: add a5, a5, a6542; RV32-NEXT: sub a4, a4, a5543; RV32-NEXT: sub a5, a0, a4544; RV32-NEXT: sltu a0, a0, a4545; RV32-NEXT: mul a3, a5, a3546; RV32-NEXT: mulhu a4, a5, a2547; RV32-NEXT: sub a1, a1, a0548; RV32-NEXT: add a3, a4, a3549; RV32-NEXT: mul a1, a1, a2550; RV32-NEXT: add a1, a3, a1551; RV32-NEXT: mul a0, a5, a2552; RV32-NEXT: ret553;554; RV64-LABEL: test_udiv_12:555; RV64: # %bb.0:556; RV64-NEXT: slli a2, a1, 62557; RV64-NEXT: srli a0, a0, 2558; RV64-NEXT: srli a1, a1, 2559; RV64-NEXT: lui a3, 699051560; RV64-NEXT: lui a4, %hi(.LCPI10_0)561; RV64-NEXT: or a0, a0, a2562; RV64-NEXT: addi a2, a3, -1365563; RV64-NEXT: ld a3, %lo(.LCPI10_0)(a4)564; RV64-NEXT: add a4, a0, a1565; RV64-NEXT: slli a5, a2, 32566; RV64-NEXT: sltu a6, a4, a0567; RV64-NEXT: add a2, a2, a5568; RV64-NEXT: add a4, a4, a6569; RV64-NEXT: mulhu a5, a4, a2570; RV64-NEXT: srli a6, a5, 1571; RV64-NEXT: andi a5, a5, -2572; RV64-NEXT: add a5, a5, a6573; RV64-NEXT: sub a4, a4, a5574; RV64-NEXT: sub a5, a0, a4575; RV64-NEXT: sltu a0, a0, a4576; RV64-NEXT: mul a3, a5, a3577; RV64-NEXT: mulhu a4, a5, a2578; RV64-NEXT: sub a1, a1, a0579; RV64-NEXT: add a3, a4, a3580; RV64-NEXT: mul a1, a1, a2581; RV64-NEXT: add a1, a3, a1582; RV64-NEXT: mul a0, a5, a2583; RV64-NEXT: ret584 %a = udiv iXLen2 %x, 12585 ret iXLen2 %a586}587