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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen2/i64/g' %s | llc -mtriple=riscv32 -mattr=+m | \3; RUN: FileCheck %s --check-prefix=RV324; RUN: sed 's/iXLen2/i128/g' %s | llc -mtriple=riscv64 -mattr=+m | \5; RUN: FileCheck %s --check-prefix=RV646 7define iXLen2 @test_urem_3(iXLen2 %x) nounwind {8; RV32-LABEL: test_urem_3:9; RV32: # %bb.0:10; RV32-NEXT: add a1, a0, a111; RV32-NEXT: lui a2, 69905112; RV32-NEXT: sltu a0, a1, a013; RV32-NEXT: addi a2, a2, -136514; RV32-NEXT: add a0, a1, a015; RV32-NEXT: mulhu a1, a0, a216; RV32-NEXT: srli a2, a1, 117; RV32-NEXT: andi a1, a1, -218; RV32-NEXT: add a1, a1, a219; RV32-NEXT: sub a0, a0, a120; RV32-NEXT: li a1, 021; RV32-NEXT: ret22;23; RV64-LABEL: test_urem_3:24; RV64: # %bb.0:25; RV64-NEXT: add a1, a0, a126; RV64-NEXT: lui a2, 69905127; RV64-NEXT: sltu a0, a1, a028; RV64-NEXT: addi a2, a2, -136529; RV64-NEXT: add a0, a1, a030; RV64-NEXT: slli a1, a2, 3231; RV64-NEXT: add a1, a2, a132; RV64-NEXT: mulhu a1, a0, a133; RV64-NEXT: srli a2, a1, 134; RV64-NEXT: andi a1, a1, -235; RV64-NEXT: add a1, a1, a236; RV64-NEXT: sub a0, a0, a137; RV64-NEXT: li a1, 038; RV64-NEXT: ret39 %a = urem iXLen2 %x, 340 ret iXLen2 %a41}42 43define iXLen2 @test_urem_5(iXLen2 %x) nounwind {44; RV32-LABEL: test_urem_5:45; RV32: # %bb.0:46; RV32-NEXT: add a1, a0, a147; RV32-NEXT: lui a2, 83886148; RV32-NEXT: sltu a0, a1, a049; RV32-NEXT: addi a2, a2, -81950; RV32-NEXT: add a0, a1, a051; RV32-NEXT: mulhu a1, a0, a252; RV32-NEXT: srli a2, a1, 253; RV32-NEXT: andi a1, a1, -454; RV32-NEXT: add a1, a1, a255; RV32-NEXT: sub a0, a0, a156; RV32-NEXT: li a1, 057; RV32-NEXT: ret58;59; RV64-LABEL: test_urem_5:60; RV64: # %bb.0:61; RV64-NEXT: add a1, a0, a162; RV64-NEXT: lui a2, 83886163; RV64-NEXT: sltu a0, a1, a064; RV64-NEXT: addi a2, a2, -81965; RV64-NEXT: add a0, a1, a066; RV64-NEXT: slli a1, a2, 3267; RV64-NEXT: add a1, a2, a168; RV64-NEXT: mulhu a1, a0, a169; RV64-NEXT: srli a2, a1, 270; RV64-NEXT: andi a1, a1, -471; RV64-NEXT: add a1, a1, a272; RV64-NEXT: sub a0, a0, a173; RV64-NEXT: li a1, 074; RV64-NEXT: ret75 %a = urem iXLen2 %x, 576 ret iXLen2 %a77}78 79define iXLen2 @test_urem_7(iXLen2 %x) nounwind {80; RV32-LABEL: test_urem_7:81; RV32: # %bb.0:82; RV32-NEXT: addi sp, sp, -1683; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill84; RV32-NEXT: li a2, 785; RV32-NEXT: li a3, 086; RV32-NEXT: call __umoddi387; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload88; RV32-NEXT: addi sp, sp, 1689; RV32-NEXT: ret90;91; RV64-LABEL: test_urem_7:92; RV64: # %bb.0:93; RV64-NEXT: addi sp, sp, -1694; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill95; RV64-NEXT: li a2, 796; RV64-NEXT: li a3, 097; RV64-NEXT: call __umodti398; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload99; RV64-NEXT: addi sp, sp, 16100; RV64-NEXT: ret101 %a = urem iXLen2 %x, 7102 ret iXLen2 %a103}104 105define iXLen2 @test_urem_9(iXLen2 %x) nounwind {106; RV32-LABEL: test_urem_9:107; RV32: # %bb.0:108; RV32-NEXT: addi sp, sp, -16109; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill110; RV32-NEXT: li a2, 9111; RV32-NEXT: li a3, 0112; RV32-NEXT: call __umoddi3113; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload114; RV32-NEXT: addi sp, sp, 16115; RV32-NEXT: ret116;117; RV64-LABEL: test_urem_9:118; RV64: # %bb.0:119; RV64-NEXT: addi sp, sp, -16120; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill121; RV64-NEXT: li a2, 9122; RV64-NEXT: li a3, 0123; RV64-NEXT: call __umodti3124; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload125; RV64-NEXT: addi sp, sp, 16126; RV64-NEXT: ret127 %a = urem iXLen2 %x, 9128 ret iXLen2 %a129}130 131define iXLen2 @test_urem_15(iXLen2 %x) nounwind {132; RV32-LABEL: test_urem_15:133; RV32: # %bb.0:134; RV32-NEXT: add a1, a0, a1135; RV32-NEXT: lui a2, 559241136; RV32-NEXT: sltu a0, a1, a0137; RV32-NEXT: add a0, a1, a0138; RV32-NEXT: addi a1, a2, -1911139; RV32-NEXT: mulhu a1, a0, a1140; RV32-NEXT: srli a1, a1, 3141; RV32-NEXT: slli a2, a1, 4142; RV32-NEXT: sub a1, a1, a2143; RV32-NEXT: add a0, a0, a1144; RV32-NEXT: li a1, 0145; RV32-NEXT: ret146;147; RV64-LABEL: test_urem_15:148; RV64: # %bb.0:149; RV64-NEXT: add a1, a0, a1150; RV64-NEXT: lui a2, 559241151; RV64-NEXT: sltu a0, a1, a0152; RV64-NEXT: addi a2, a2, -1911153; RV64-NEXT: add a0, a1, a0154; RV64-NEXT: slli a1, a2, 32155; RV64-NEXT: add a1, a2, a1156; RV64-NEXT: mulhu a1, a0, a1157; RV64-NEXT: srli a1, a1, 3158; RV64-NEXT: slli a2, a1, 4159; RV64-NEXT: sub a1, a1, a2160; RV64-NEXT: add a0, a0, a1161; RV64-NEXT: li a1, 0162; RV64-NEXT: ret163 %a = urem iXLen2 %x, 15164 ret iXLen2 %a165}166 167define iXLen2 @test_urem_17(iXLen2 %x) nounwind {168; RV32-LABEL: test_urem_17:169; RV32: # %bb.0:170; RV32-NEXT: add a1, a0, a1171; RV32-NEXT: lui a2, 986895172; RV32-NEXT: sltu a0, a1, a0173; RV32-NEXT: addi a2, a2, 241174; RV32-NEXT: add a0, a1, a0175; RV32-NEXT: mulhu a1, a0, a2176; RV32-NEXT: srli a2, a1, 4177; RV32-NEXT: andi a1, a1, -16178; RV32-NEXT: add a1, a1, a2179; RV32-NEXT: sub a0, a0, a1180; RV32-NEXT: li a1, 0181; RV32-NEXT: ret182;183; RV64-LABEL: test_urem_17:184; RV64: # %bb.0:185; RV64-NEXT: add a1, a0, a1186; RV64-NEXT: lui a2, 986895187; RV64-NEXT: sltu a0, a1, a0188; RV64-NEXT: addi a2, a2, 241189; RV64-NEXT: add a0, a1, a0190; RV64-NEXT: slli a1, a2, 32191; RV64-NEXT: add a1, a2, a1192; RV64-NEXT: mulhu a1, a0, a1193; RV64-NEXT: srli a2, a1, 4194; RV64-NEXT: andi a1, a1, -16195; RV64-NEXT: add a1, a1, a2196; RV64-NEXT: sub a0, a0, a1197; RV64-NEXT: li a1, 0198; RV64-NEXT: ret199 %a = urem iXLen2 %x, 17200 ret iXLen2 %a201}202 203define iXLen2 @test_urem_255(iXLen2 %x) nounwind {204; RV32-LABEL: test_urem_255:205; RV32: # %bb.0:206; RV32-NEXT: add a1, a0, a1207; RV32-NEXT: lui a2, 526344208; RV32-NEXT: sltu a0, a1, a0209; RV32-NEXT: add a0, a1, a0210; RV32-NEXT: addi a1, a2, 129211; RV32-NEXT: mulhu a1, a0, a1212; RV32-NEXT: srli a1, a1, 7213; RV32-NEXT: slli a2, a1, 8214; RV32-NEXT: sub a1, a1, a2215; RV32-NEXT: add a0, a0, a1216; RV32-NEXT: li a1, 0217; RV32-NEXT: ret218;219; RV64-LABEL: test_urem_255:220; RV64: # %bb.0:221; RV64-NEXT: add a1, a0, a1222; RV64-NEXT: lui a2, 526344223; RV64-NEXT: sltu a0, a1, a0224; RV64-NEXT: addi a2, a2, 129225; RV64-NEXT: add a0, a1, a0226; RV64-NEXT: slli a1, a2, 32227; RV64-NEXT: add a1, a2, a1228; RV64-NEXT: mulhu a1, a0, a1229; RV64-NEXT: srli a1, a1, 7230; RV64-NEXT: slli a2, a1, 8231; RV64-NEXT: sub a1, a1, a2232; RV64-NEXT: add a0, a0, a1233; RV64-NEXT: li a1, 0234; RV64-NEXT: ret235 %a = urem iXLen2 %x, 255236 ret iXLen2 %a237}238 239define iXLen2 @test_urem_257(iXLen2 %x) nounwind {240; RV32-LABEL: test_urem_257:241; RV32: # %bb.0:242; RV32-NEXT: add a1, a0, a1243; RV32-NEXT: lui a2, 1044496244; RV32-NEXT: sltu a0, a1, a0245; RV32-NEXT: addi a2, a2, -255246; RV32-NEXT: add a0, a1, a0247; RV32-NEXT: mulhu a1, a0, a2248; RV32-NEXT: srli a2, a1, 8249; RV32-NEXT: andi a1, a1, -256250; RV32-NEXT: add a1, a1, a2251; RV32-NEXT: sub a0, a0, a1252; RV32-NEXT: li a1, 0253; RV32-NEXT: ret254;255; RV64-LABEL: test_urem_257:256; RV64: # %bb.0:257; RV64-NEXT: add a1, a0, a1258; RV64-NEXT: lui a2, 1044496259; RV64-NEXT: sltu a0, a1, a0260; RV64-NEXT: addi a2, a2, -255261; RV64-NEXT: add a0, a1, a0262; RV64-NEXT: slli a1, a2, 32263; RV64-NEXT: add a1, a2, a1264; RV64-NEXT: mulhu a1, a0, a1265; RV64-NEXT: srli a2, a1, 8266; RV64-NEXT: andi a1, a1, -256267; RV64-NEXT: add a1, a1, a2268; RV64-NEXT: sub a0, a0, a1269; RV64-NEXT: li a1, 0270; RV64-NEXT: ret271 %a = urem iXLen2 %x, 257272 ret iXLen2 %a273}274 275define iXLen2 @test_urem_65535(iXLen2 %x) nounwind {276; RV32-LABEL: test_urem_65535:277; RV32: # %bb.0:278; RV32-NEXT: add a1, a0, a1279; RV32-NEXT: lui a2, 524296280; RV32-NEXT: sltu a0, a1, a0281; RV32-NEXT: add a0, a1, a0282; RV32-NEXT: addi a2, a2, 1283; RV32-NEXT: mulhu a1, a0, a2284; RV32-NEXT: srli a1, a1, 15285; RV32-NEXT: slli a2, a1, 16286; RV32-NEXT: sub a1, a1, a2287; RV32-NEXT: add a0, a0, a1288; RV32-NEXT: li a1, 0289; RV32-NEXT: ret290;291; RV64-LABEL: test_urem_65535:292; RV64: # %bb.0:293; RV64-NEXT: add a1, a0, a1294; RV64-NEXT: lui a2, 524296295; RV64-NEXT: sltu a0, a1, a0296; RV64-NEXT: addi a2, a2, 1297; RV64-NEXT: add a0, a1, a0298; RV64-NEXT: slli a1, a2, 32299; RV64-NEXT: add a1, a2, a1300; RV64-NEXT: mulhu a1, a0, a1301; RV64-NEXT: srli a1, a1, 15302; RV64-NEXT: slli a2, a1, 16303; RV64-NEXT: sub a1, a1, a2304; RV64-NEXT: add a0, a0, a1305; RV64-NEXT: li a1, 0306; RV64-NEXT: ret307 %a = urem iXLen2 %x, 65535308 ret iXLen2 %a309}310 311define iXLen2 @test_urem_65537(iXLen2 %x) nounwind {312; RV32-LABEL: test_urem_65537:313; RV32: # %bb.0:314; RV32-NEXT: add a1, a0, a1315; RV32-NEXT: lui a2, 1048560316; RV32-NEXT: sltu a0, a1, a0317; RV32-NEXT: add a0, a1, a0318; RV32-NEXT: addi a1, a2, 1319; RV32-NEXT: mulhu a1, a0, a1320; RV32-NEXT: and a2, a1, a2321; RV32-NEXT: srli a1, a1, 16322; RV32-NEXT: or a1, a2, a1323; RV32-NEXT: sub a0, a0, a1324; RV32-NEXT: li a1, 0325; RV32-NEXT: ret326;327; RV64-LABEL: test_urem_65537:328; RV64: # %bb.0:329; RV64-NEXT: add a1, a0, a1330; RV64-NEXT: lui a2, 1048560331; RV64-NEXT: sltu a0, a1, a0332; RV64-NEXT: addi a3, a2, 1333; RV64-NEXT: add a0, a1, a0334; RV64-NEXT: slli a1, a3, 32335; RV64-NEXT: add a1, a3, a1336; RV64-NEXT: mulhu a1, a0, a1337; RV64-NEXT: and a2, a1, a2338; RV64-NEXT: srli a1, a1, 16339; RV64-NEXT: add a1, a2, a1340; RV64-NEXT: sub a0, a0, a1341; RV64-NEXT: li a1, 0342; RV64-NEXT: ret343 %a = urem iXLen2 %x, 65537344 ret iXLen2 %a345}346 347define iXLen2 @test_urem_12(iXLen2 %x) nounwind {348; RV32-LABEL: test_urem_12:349; RV32: # %bb.0:350; RV32-NEXT: slli a2, a1, 30351; RV32-NEXT: srli a3, a0, 2352; RV32-NEXT: srli a1, a1, 2353; RV32-NEXT: or a2, a3, a2354; RV32-NEXT: lui a3, 699051355; RV32-NEXT: addi a3, a3, -1365356; RV32-NEXT: add a1, a2, a1357; RV32-NEXT: sltu a2, a1, a2358; RV32-NEXT: add a1, a1, a2359; RV32-NEXT: mulhu a2, a1, a3360; RV32-NEXT: srli a3, a2, 1361; RV32-NEXT: andi a2, a2, -2362; RV32-NEXT: add a2, a2, a3363; RV32-NEXT: sub a1, a1, a2364; RV32-NEXT: slli a1, a1, 2365; RV32-NEXT: andi a0, a0, 3366; RV32-NEXT: or a0, a1, a0367; RV32-NEXT: li a1, 0368; RV32-NEXT: ret369;370; RV64-LABEL: test_urem_12:371; RV64: # %bb.0:372; RV64-NEXT: slli a2, a1, 62373; RV64-NEXT: srli a3, a0, 2374; RV64-NEXT: lui a4, 699051375; RV64-NEXT: or a2, a3, a2376; RV64-NEXT: addi a3, a4, -1365377; RV64-NEXT: slli a4, a3, 32378; RV64-NEXT: add a3, a3, a4379; RV64-NEXT: srli a1, a1, 2380; RV64-NEXT: add a1, a2, a1381; RV64-NEXT: sltu a2, a1, a2382; RV64-NEXT: add a1, a1, a2383; RV64-NEXT: mulhu a2, a1, a3384; RV64-NEXT: srli a3, a2, 1385; RV64-NEXT: andi a2, a2, -2386; RV64-NEXT: add a2, a2, a3387; RV64-NEXT: sub a1, a1, a2388; RV64-NEXT: slli a1, a1, 2389; RV64-NEXT: andi a0, a0, 3390; RV64-NEXT: or a0, a1, a0391; RV64-NEXT: li a1, 0392; RV64-NEXT: ret393 %a = urem iXLen2 %x, 12394 ret iXLen2 %a395}396