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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefixes=RV32,RV32I3; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefixes=RV64,RV64I4; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb | FileCheck %s --check-prefixes=RV32,RV32IZbb5; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb | FileCheck %s --check-prefixes=RV64,RV64IZbb6 7define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {8; RV32-LABEL: func:9; RV32: # %bb.0:10; RV32-NEXT: mv a2, a011; RV32-NEXT: sgtz a3, a112; RV32-NEXT: sub a0, a0, a113; RV32-NEXT: slt a1, a0, a214; RV32-NEXT: beq a3, a1, .LBB0_215; RV32-NEXT: # %bb.1:16; RV32-NEXT: srai a0, a0, 3117; RV32-NEXT: lui a1, 52428818; RV32-NEXT: xor a0, a0, a119; RV32-NEXT: .LBB0_2:20; RV32-NEXT: ret21;22; RV64I-LABEL: func:23; RV64I: # %bb.0:24; RV64I-NEXT: sub a2, a0, a125; RV64I-NEXT: subw a0, a0, a126; RV64I-NEXT: beq a0, a2, .LBB0_227; RV64I-NEXT: # %bb.1:28; RV64I-NEXT: srli a0, a0, 3129; RV64I-NEXT: li a1, 130; RV64I-NEXT: slli a1, a1, 3131; RV64I-NEXT: xor a2, a0, a132; RV64I-NEXT: .LBB0_2:33; RV64I-NEXT: sext.w a0, a234; RV64I-NEXT: ret35;36; RV64IZbb-LABEL: func:37; RV64IZbb: # %bb.0:38; RV64IZbb-NEXT: sub a0, a0, a139; RV64IZbb-NEXT: lui a1, 52428840; RV64IZbb-NEXT: addiw a2, a1, -141; RV64IZbb-NEXT: min a0, a0, a242; RV64IZbb-NEXT: max a0, a0, a143; RV64IZbb-NEXT: ret44 %tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %y);45 ret i32 %tmp;46}47 48define i64 @func2(i64 %x, i64 %y) nounwind {49; RV32-LABEL: func2:50; RV32: # %bb.0:51; RV32-NEXT: mv a4, a152; RV32-NEXT: sltu a1, a0, a253; RV32-NEXT: sub a5, a4, a354; RV32-NEXT: sub a1, a5, a155; RV32-NEXT: xor a5, a4, a156; RV32-NEXT: xor a3, a4, a357; RV32-NEXT: and a3, a3, a558; RV32-NEXT: bltz a3, .LBB1_259; RV32-NEXT: # %bb.1:60; RV32-NEXT: sub a0, a0, a261; RV32-NEXT: ret62; RV32-NEXT: .LBB1_2:63; RV32-NEXT: srai a0, a1, 3164; RV32-NEXT: lui a1, 52428865; RV32-NEXT: xor a1, a0, a166; RV32-NEXT: ret67;68; RV64-LABEL: func2:69; RV64: # %bb.0:70; RV64-NEXT: mv a2, a071; RV64-NEXT: sgtz a3, a172; RV64-NEXT: sub a0, a0, a173; RV64-NEXT: slt a1, a0, a274; RV64-NEXT: beq a3, a1, .LBB1_275; RV64-NEXT: # %bb.1:76; RV64-NEXT: srai a0, a0, 6377; RV64-NEXT: li a1, -178; RV64-NEXT: slli a1, a1, 6379; RV64-NEXT: xor a0, a0, a180; RV64-NEXT: .LBB1_2:81; RV64-NEXT: ret82 %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %y);83 ret i64 %tmp;84}85 86define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {87; RV32I-LABEL: func16:88; RV32I: # %bb.0:89; RV32I-NEXT: sub a0, a0, a190; RV32I-NEXT: lui a1, 891; RV32I-NEXT: addi a1, a1, -192; RV32I-NEXT: bge a0, a1, .LBB2_393; RV32I-NEXT: # %bb.1:94; RV32I-NEXT: lui a1, 104856895; RV32I-NEXT: bge a1, a0, .LBB2_496; RV32I-NEXT: .LBB2_2:97; RV32I-NEXT: ret98; RV32I-NEXT: .LBB2_3:99; RV32I-NEXT: mv a0, a1100; RV32I-NEXT: lui a1, 1048568101; RV32I-NEXT: blt a1, a0, .LBB2_2102; RV32I-NEXT: .LBB2_4:103; RV32I-NEXT: lui a0, 1048568104; RV32I-NEXT: ret105;106; RV64I-LABEL: func16:107; RV64I: # %bb.0:108; RV64I-NEXT: sub a0, a0, a1109; RV64I-NEXT: lui a1, 8110; RV64I-NEXT: addi a1, a1, -1111; RV64I-NEXT: bge a0, a1, .LBB2_3112; RV64I-NEXT: # %bb.1:113; RV64I-NEXT: lui a1, 1048568114; RV64I-NEXT: bge a1, a0, .LBB2_4115; RV64I-NEXT: .LBB2_2:116; RV64I-NEXT: ret117; RV64I-NEXT: .LBB2_3:118; RV64I-NEXT: mv a0, a1119; RV64I-NEXT: lui a1, 1048568120; RV64I-NEXT: blt a1, a0, .LBB2_2121; RV64I-NEXT: .LBB2_4:122; RV64I-NEXT: lui a0, 1048568123; RV64I-NEXT: ret124;125; RV32IZbb-LABEL: func16:126; RV32IZbb: # %bb.0:127; RV32IZbb-NEXT: sub a0, a0, a1128; RV32IZbb-NEXT: lui a1, 8129; RV32IZbb-NEXT: addi a1, a1, -1130; RV32IZbb-NEXT: min a0, a0, a1131; RV32IZbb-NEXT: lui a1, 1048568132; RV32IZbb-NEXT: max a0, a0, a1133; RV32IZbb-NEXT: ret134;135; RV64IZbb-LABEL: func16:136; RV64IZbb: # %bb.0:137; RV64IZbb-NEXT: sub a0, a0, a1138; RV64IZbb-NEXT: lui a1, 8139; RV64IZbb-NEXT: addi a1, a1, -1140; RV64IZbb-NEXT: min a0, a0, a1141; RV64IZbb-NEXT: lui a1, 1048568142; RV64IZbb-NEXT: max a0, a0, a1143; RV64IZbb-NEXT: ret144 %tmp = call i16 @llvm.ssub.sat.i16(i16 %x, i16 %y);145 ret i16 %tmp;146}147 148define signext i8 @func8(i8 signext %x, i8 signext %y) nounwind {149; RV32I-LABEL: func8:150; RV32I: # %bb.0:151; RV32I-NEXT: sub a0, a0, a1152; RV32I-NEXT: li a1, 127153; RV32I-NEXT: bge a0, a1, .LBB3_3154; RV32I-NEXT: # %bb.1:155; RV32I-NEXT: li a1, -128156; RV32I-NEXT: bge a1, a0, .LBB3_4157; RV32I-NEXT: .LBB3_2:158; RV32I-NEXT: ret159; RV32I-NEXT: .LBB3_3:160; RV32I-NEXT: li a0, 127161; RV32I-NEXT: li a1, -128162; RV32I-NEXT: blt a1, a0, .LBB3_2163; RV32I-NEXT: .LBB3_4:164; RV32I-NEXT: li a0, -128165; RV32I-NEXT: ret166;167; RV64I-LABEL: func8:168; RV64I: # %bb.0:169; RV64I-NEXT: sub a0, a0, a1170; RV64I-NEXT: li a1, 127171; RV64I-NEXT: bge a0, a1, .LBB3_3172; RV64I-NEXT: # %bb.1:173; RV64I-NEXT: li a1, -128174; RV64I-NEXT: bge a1, a0, .LBB3_4175; RV64I-NEXT: .LBB3_2:176; RV64I-NEXT: ret177; RV64I-NEXT: .LBB3_3:178; RV64I-NEXT: li a0, 127179; RV64I-NEXT: li a1, -128180; RV64I-NEXT: blt a1, a0, .LBB3_2181; RV64I-NEXT: .LBB3_4:182; RV64I-NEXT: li a0, -128183; RV64I-NEXT: ret184;185; RV32IZbb-LABEL: func8:186; RV32IZbb: # %bb.0:187; RV32IZbb-NEXT: sub a0, a0, a1188; RV32IZbb-NEXT: li a1, 127189; RV32IZbb-NEXT: min a0, a0, a1190; RV32IZbb-NEXT: li a1, -128191; RV32IZbb-NEXT: max a0, a0, a1192; RV32IZbb-NEXT: ret193;194; RV64IZbb-LABEL: func8:195; RV64IZbb: # %bb.0:196; RV64IZbb-NEXT: sub a0, a0, a1197; RV64IZbb-NEXT: li a1, 127198; RV64IZbb-NEXT: min a0, a0, a1199; RV64IZbb-NEXT: li a1, -128200; RV64IZbb-NEXT: max a0, a0, a1201; RV64IZbb-NEXT: ret202 %tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %y);203 ret i8 %tmp;204}205 206define signext i4 @func3(i4 signext %x, i4 signext %y) nounwind {207; RV32I-LABEL: func3:208; RV32I: # %bb.0:209; RV32I-NEXT: sub a0, a0, a1210; RV32I-NEXT: li a1, 7211; RV32I-NEXT: bge a0, a1, .LBB4_3212; RV32I-NEXT: # %bb.1:213; RV32I-NEXT: li a1, -8214; RV32I-NEXT: bge a1, a0, .LBB4_4215; RV32I-NEXT: .LBB4_2:216; RV32I-NEXT: ret217; RV32I-NEXT: .LBB4_3:218; RV32I-NEXT: li a0, 7219; RV32I-NEXT: li a1, -8220; RV32I-NEXT: blt a1, a0, .LBB4_2221; RV32I-NEXT: .LBB4_4:222; RV32I-NEXT: li a0, -8223; RV32I-NEXT: ret224;225; RV64I-LABEL: func3:226; RV64I: # %bb.0:227; RV64I-NEXT: sub a0, a0, a1228; RV64I-NEXT: li a1, 7229; RV64I-NEXT: bge a0, a1, .LBB4_3230; RV64I-NEXT: # %bb.1:231; RV64I-NEXT: li a1, -8232; RV64I-NEXT: bge a1, a0, .LBB4_4233; RV64I-NEXT: .LBB4_2:234; RV64I-NEXT: ret235; RV64I-NEXT: .LBB4_3:236; RV64I-NEXT: li a0, 7237; RV64I-NEXT: li a1, -8238; RV64I-NEXT: blt a1, a0, .LBB4_2239; RV64I-NEXT: .LBB4_4:240; RV64I-NEXT: li a0, -8241; RV64I-NEXT: ret242;243; RV32IZbb-LABEL: func3:244; RV32IZbb: # %bb.0:245; RV32IZbb-NEXT: sub a0, a0, a1246; RV32IZbb-NEXT: li a1, 7247; RV32IZbb-NEXT: min a0, a0, a1248; RV32IZbb-NEXT: li a1, -8249; RV32IZbb-NEXT: max a0, a0, a1250; RV32IZbb-NEXT: ret251;252; RV64IZbb-LABEL: func3:253; RV64IZbb: # %bb.0:254; RV64IZbb-NEXT: sub a0, a0, a1255; RV64IZbb-NEXT: li a1, 7256; RV64IZbb-NEXT: min a0, a0, a1257; RV64IZbb-NEXT: li a1, -8258; RV64IZbb-NEXT: max a0, a0, a1259; RV64IZbb-NEXT: ret260 %tmp = call i4 @llvm.ssub.sat.i4(i4 %x, i4 %y);261 ret i4 %tmp;262}263