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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+m -O2 < %s -verify-machineinstrs \3; RUN: | FileCheck %s -check-prefix=RV64I4; RUN: llc -mtriple=riscv32 -mattr=+m -O2 < %s -verify-machineinstrs \5; RUN: | FileCheck %s -check-prefix=RV32I6 7; Tests copied from PowerPC.8 9; Free probe10define i8 @f0() #0 nounwind {11; RV64I-LABEL: f0:12; RV64I: # %bb.0: # %entry13; RV64I-NEXT: addi sp, sp, -6414; RV64I-NEXT: li a0, 315; RV64I-NEXT: sb a0, 0(sp)16; RV64I-NEXT: lbu a0, 0(sp)17; RV64I-NEXT: addi sp, sp, 6418; RV64I-NEXT: ret19;20; RV32I-LABEL: f0:21; RV32I: # %bb.0: # %entry22; RV32I-NEXT: addi sp, sp, -6423; RV32I-NEXT: li a0, 324; RV32I-NEXT: sb a0, 0(sp)25; RV32I-NEXT: lbu a0, 0(sp)26; RV32I-NEXT: addi sp, sp, 6427; RV32I-NEXT: ret28entry:29 %a = alloca i8, i64 6430 %b = getelementptr inbounds i8, ptr %a, i64 6331 store volatile i8 3, ptr %a32 %c = load volatile i8, ptr %a33 ret i8 %c34}35 36define i8 @f1() #0 nounwind {37; RV64I-LABEL: f1:38; RV64I: # %bb.0: # %entry39; RV64I-NEXT: lui a0, 140; RV64I-NEXT: sub sp, sp, a041; RV64I-NEXT: sd zero, 0(sp)42; RV64I-NEXT: addi sp, sp, -1643; RV64I-NEXT: li a0, 344; RV64I-NEXT: sb a0, 16(sp)45; RV64I-NEXT: lbu a0, 16(sp)46; RV64I-NEXT: lui a1, 147; RV64I-NEXT: addi a1, a1, 1648; RV64I-NEXT: add sp, sp, a149; RV64I-NEXT: ret50;51; RV32I-LABEL: f1:52; RV32I: # %bb.0: # %entry53; RV32I-NEXT: lui a0, 154; RV32I-NEXT: sub sp, sp, a055; RV32I-NEXT: sw zero, 0(sp)56; RV32I-NEXT: addi sp, sp, -1657; RV32I-NEXT: li a0, 358; RV32I-NEXT: sb a0, 16(sp)59; RV32I-NEXT: lbu a0, 16(sp)60; RV32I-NEXT: lui a1, 161; RV32I-NEXT: addi a1, a1, 1662; RV32I-NEXT: add sp, sp, a163; RV32I-NEXT: ret64entry:65 %a = alloca i8, i64 409666 %b = getelementptr inbounds i8, ptr %a, i64 6367 store volatile i8 3, ptr %a68 %c = load volatile i8, ptr %a69 ret i8 %c70}71 72define i8 @f2() #0 nounwind {73; RV64I-LABEL: f2:74; RV64I: # %bb.0: # %entry75; RV64I-NEXT: lui a0, 1676; RV64I-NEXT: sub t1, sp, a077; RV64I-NEXT: lui t2, 178; RV64I-NEXT: .LBB2_1: # %entry79; RV64I-NEXT: # =>This Inner Loop Header: Depth=180; RV64I-NEXT: sub sp, sp, t281; RV64I-NEXT: sd zero, 0(sp)82; RV64I-NEXT: bne sp, t1, .LBB2_183; RV64I-NEXT: # %bb.2: # %entry84; RV64I-NEXT: addi sp, sp, -1685; RV64I-NEXT: li a0, 386; RV64I-NEXT: sb a0, 16(sp)87; RV64I-NEXT: lbu a0, 16(sp)88; RV64I-NEXT: lui a1, 1689; RV64I-NEXT: addi a1, a1, 1690; RV64I-NEXT: add sp, sp, a191; RV64I-NEXT: ret92;93; RV32I-LABEL: f2:94; RV32I: # %bb.0: # %entry95; RV32I-NEXT: lui a0, 1696; RV32I-NEXT: sub t1, sp, a097; RV32I-NEXT: lui t2, 198; RV32I-NEXT: .LBB2_1: # %entry99; RV32I-NEXT: # =>This Inner Loop Header: Depth=1100; RV32I-NEXT: sub sp, sp, t2101; RV32I-NEXT: sw zero, 0(sp)102; RV32I-NEXT: bne sp, t1, .LBB2_1103; RV32I-NEXT: # %bb.2: # %entry104; RV32I-NEXT: addi sp, sp, -16105; RV32I-NEXT: li a0, 3106; RV32I-NEXT: sb a0, 16(sp)107; RV32I-NEXT: lbu a0, 16(sp)108; RV32I-NEXT: lui a1, 16109; RV32I-NEXT: addi a1, a1, 16110; RV32I-NEXT: add sp, sp, a1111; RV32I-NEXT: ret112entry:113 %a = alloca i8, i64 65536114 %b = getelementptr inbounds i8, ptr %a, i64 63115 store volatile i8 3, ptr %a116 %c = load volatile i8, ptr %a117 ret i8 %c118}119 120define i8 @f3() #0 "stack-probe-size"="32768" nounwind {121; RV64I-LABEL: f3:122; RV64I: # %bb.0: # %entry123; RV64I-NEXT: lui a0, 8124; RV64I-NEXT: sub sp, sp, a0125; RV64I-NEXT: sd zero, 0(sp)126; RV64I-NEXT: lui a0, 8127; RV64I-NEXT: sub sp, sp, a0128; RV64I-NEXT: sd zero, 0(sp)129; RV64I-NEXT: addi sp, sp, -16130; RV64I-NEXT: li a0, 3131; RV64I-NEXT: sb a0, 16(sp)132; RV64I-NEXT: lbu a0, 16(sp)133; RV64I-NEXT: lui a1, 16134; RV64I-NEXT: addi a1, a1, 16135; RV64I-NEXT: add sp, sp, a1136; RV64I-NEXT: ret137;138; RV32I-LABEL: f3:139; RV32I: # %bb.0: # %entry140; RV32I-NEXT: lui a0, 8141; RV32I-NEXT: sub sp, sp, a0142; RV32I-NEXT: sw zero, 0(sp)143; RV32I-NEXT: lui a0, 8144; RV32I-NEXT: sub sp, sp, a0145; RV32I-NEXT: sw zero, 0(sp)146; RV32I-NEXT: addi sp, sp, -16147; RV32I-NEXT: li a0, 3148; RV32I-NEXT: sb a0, 16(sp)149; RV32I-NEXT: lbu a0, 16(sp)150; RV32I-NEXT: lui a1, 16151; RV32I-NEXT: addi a1, a1, 16152; RV32I-NEXT: add sp, sp, a1153; RV32I-NEXT: ret154entry:155 %a = alloca i8, i64 65536156 %b = getelementptr inbounds i8, ptr %a, i64 63157 store volatile i8 3, ptr %a158 %c = load volatile i8, ptr %a159 ret i8 %c160}161 162; Same as f2, but without protection.163define i8 @f4() nounwind {164; RV64I-LABEL: f4:165; RV64I: # %bb.0: # %entry166; RV64I-NEXT: lui a0, 16167; RV64I-NEXT: addi a0, a0, 16168; RV64I-NEXT: sub sp, sp, a0169; RV64I-NEXT: li a0, 3170; RV64I-NEXT: sb a0, 16(sp)171; RV64I-NEXT: lbu a0, 16(sp)172; RV64I-NEXT: lui a1, 16173; RV64I-NEXT: addi a1, a1, 16174; RV64I-NEXT: add sp, sp, a1175; RV64I-NEXT: ret176;177; RV32I-LABEL: f4:178; RV32I: # %bb.0: # %entry179; RV32I-NEXT: lui a0, 16180; RV32I-NEXT: addi a0, a0, 16181; RV32I-NEXT: sub sp, sp, a0182; RV32I-NEXT: li a0, 3183; RV32I-NEXT: sb a0, 16(sp)184; RV32I-NEXT: lbu a0, 16(sp)185; RV32I-NEXT: lui a1, 16186; RV32I-NEXT: addi a1, a1, 16187; RV32I-NEXT: add sp, sp, a1188; RV32I-NEXT: ret189entry:190 %a = alloca i8, i64 65536191 %b = getelementptr inbounds i8, ptr %a, i64 63192 store volatile i8 3, ptr %a193 %c = load volatile i8, ptr %a194 ret i8 %c195}196 197define i8 @f5() #0 "stack-probe-size"="65536" nounwind {198; RV64I-LABEL: f5:199; RV64I: # %bb.0: # %entry200; RV64I-NEXT: lui a0, 256201; RV64I-NEXT: sub t1, sp, a0202; RV64I-NEXT: lui t2, 16203; RV64I-NEXT: .LBB5_1: # %entry204; RV64I-NEXT: # =>This Inner Loop Header: Depth=1205; RV64I-NEXT: sub sp, sp, t2206; RV64I-NEXT: sd zero, 0(sp)207; RV64I-NEXT: bne sp, t1, .LBB5_1208; RV64I-NEXT: # %bb.2: # %entry209; RV64I-NEXT: addi sp, sp, -16210; RV64I-NEXT: li a0, 3211; RV64I-NEXT: sb a0, 16(sp)212; RV64I-NEXT: lbu a0, 16(sp)213; RV64I-NEXT: lui a1, 256214; RV64I-NEXT: addi a1, a1, 16215; RV64I-NEXT: add sp, sp, a1216; RV64I-NEXT: ret217;218; RV32I-LABEL: f5:219; RV32I: # %bb.0: # %entry220; RV32I-NEXT: lui a0, 256221; RV32I-NEXT: sub t1, sp, a0222; RV32I-NEXT: lui t2, 16223; RV32I-NEXT: .LBB5_1: # %entry224; RV32I-NEXT: # =>This Inner Loop Header: Depth=1225; RV32I-NEXT: sub sp, sp, t2226; RV32I-NEXT: sw zero, 0(sp)227; RV32I-NEXT: bne sp, t1, .LBB5_1228; RV32I-NEXT: # %bb.2: # %entry229; RV32I-NEXT: addi sp, sp, -16230; RV32I-NEXT: li a0, 3231; RV32I-NEXT: sb a0, 16(sp)232; RV32I-NEXT: lbu a0, 16(sp)233; RV32I-NEXT: lui a1, 256234; RV32I-NEXT: addi a1, a1, 16235; RV32I-NEXT: add sp, sp, a1236; RV32I-NEXT: ret237entry:238 %a = alloca i8, i64 1048576239 %b = getelementptr inbounds i8, ptr %a, i64 63240 store volatile i8 3, ptr %a241 %c = load volatile i8, ptr %a242 ret i8 %c243}244 245define i8 @f6() #0 nounwind {246; RV64I-LABEL: f6:247; RV64I: # %bb.0: # %entry248; RV64I-NEXT: lui a0, 262144249; RV64I-NEXT: sub t1, sp, a0250; RV64I-NEXT: lui t2, 1251; RV64I-NEXT: .LBB6_1: # %entry252; RV64I-NEXT: # =>This Inner Loop Header: Depth=1253; RV64I-NEXT: sub sp, sp, t2254; RV64I-NEXT: sd zero, 0(sp)255; RV64I-NEXT: bne sp, t1, .LBB6_1256; RV64I-NEXT: # %bb.2: # %entry257; RV64I-NEXT: addi sp, sp, -16258; RV64I-NEXT: li a0, 3259; RV64I-NEXT: sb a0, 16(sp)260; RV64I-NEXT: lbu a0, 16(sp)261; RV64I-NEXT: lui a1, 262144262; RV64I-NEXT: addi a1, a1, 16263; RV64I-NEXT: add sp, sp, a1264; RV64I-NEXT: ret265;266; RV32I-LABEL: f6:267; RV32I: # %bb.0: # %entry268; RV32I-NEXT: lui a0, 262144269; RV32I-NEXT: sub t1, sp, a0270; RV32I-NEXT: lui t2, 1271; RV32I-NEXT: .LBB6_1: # %entry272; RV32I-NEXT: # =>This Inner Loop Header: Depth=1273; RV32I-NEXT: sub sp, sp, t2274; RV32I-NEXT: sw zero, 0(sp)275; RV32I-NEXT: bne sp, t1, .LBB6_1276; RV32I-NEXT: # %bb.2: # %entry277; RV32I-NEXT: addi sp, sp, -16278; RV32I-NEXT: li a0, 3279; RV32I-NEXT: sb a0, 16(sp)280; RV32I-NEXT: lbu a0, 16(sp)281; RV32I-NEXT: lui a1, 262144282; RV32I-NEXT: addi a1, a1, 16283; RV32I-NEXT: add sp, sp, a1284; RV32I-NEXT: ret285entry:286 %a = alloca i8, i64 1073741824287 %b = getelementptr inbounds i8, ptr %a, i64 63288 store volatile i8 3, ptr %a289 %c = load volatile i8, ptr %a290 ret i8 %c291}292 293define i8 @f7() #0 "stack-probe-size"="65536" nounwind {294; RV64I-LABEL: f7:295; RV64I: # %bb.0: # %entry296; RV64I-NEXT: lui a0, 244128297; RV64I-NEXT: sub t1, sp, a0298; RV64I-NEXT: lui t2, 16299; RV64I-NEXT: .LBB7_1: # %entry300; RV64I-NEXT: # =>This Inner Loop Header: Depth=1301; RV64I-NEXT: sub sp, sp, t2302; RV64I-NEXT: sd zero, 0(sp)303; RV64I-NEXT: bne sp, t1, .LBB7_1304; RV64I-NEXT: # %bb.2: # %entry305; RV64I-NEXT: lui a0, 13306; RV64I-NEXT: addi a0, a0, -1520307; RV64I-NEXT: sub sp, sp, a0308; RV64I-NEXT: li a0, 3309; RV64I-NEXT: sb a0, 9(sp)310; RV64I-NEXT: lbu a0, 9(sp)311; RV64I-NEXT: lui a1, 244141312; RV64I-NEXT: addi a1, a1, -1520313; RV64I-NEXT: add sp, sp, a1314; RV64I-NEXT: ret315;316; RV32I-LABEL: f7:317; RV32I: # %bb.0: # %entry318; RV32I-NEXT: lui a0, 244128319; RV32I-NEXT: sub t1, sp, a0320; RV32I-NEXT: lui t2, 16321; RV32I-NEXT: .LBB7_1: # %entry322; RV32I-NEXT: # =>This Inner Loop Header: Depth=1323; RV32I-NEXT: sub sp, sp, t2324; RV32I-NEXT: sw zero, 0(sp)325; RV32I-NEXT: bne sp, t1, .LBB7_1326; RV32I-NEXT: # %bb.2: # %entry327; RV32I-NEXT: lui a0, 13328; RV32I-NEXT: addi a0, a0, -1520329; RV32I-NEXT: sub sp, sp, a0330; RV32I-NEXT: li a0, 3331; RV32I-NEXT: sb a0, 9(sp)332; RV32I-NEXT: lbu a0, 9(sp)333; RV32I-NEXT: lui a1, 244141334; RV32I-NEXT: addi a1, a1, -1520335; RV32I-NEXT: add sp, sp, a1336; RV32I-NEXT: ret337entry:338 %a = alloca i8, i64 1000000007339 %b = getelementptr inbounds i8, ptr %a, i64 101340 store volatile i8 3, ptr %a341 %c = load volatile i8, ptr %a342 ret i8 %c343}344 345attributes #0 = { "probe-stack"="inline-asm" }346