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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv32 -run-pass=greedy,virtregrewriter,stack-slot-coloring %s -o - 2>&1 | FileCheck %s3 4--- |5 define dso_local i32 @main() local_unnamed_addr {6 entry:7 %a = alloca i32, align 48 ret i32 09 }10 11...12---13name: main14alignment: 415exposesReturnsTwice: false16legalized: false17regBankSelected: false18selected: false19failedISel: false20tracksRegLiveness: true21hasWinCFI: false22callsEHReturn: false23callsUnwindInit: false24hasEHContTarget: false25hasEHScopes: false26hasEHFunclets: false27failsVerification: false28tracksDebugUserValues: false29registers:30 - { id: 0, class: gpr, preferred-register: '' }31 - { id: 1, class: gpr, preferred-register: '' }32liveins: []33frameInfo:34 isFrameAddressTaken: false35 isReturnAddressTaken: false36 hasStackMap: false37 hasPatchPoint: false38 stackSize: 039 offsetAdjustment: 040 maxAlignment: 441 adjustsStack: false42 hasCalls: false43 stackProtector: ''44 functionContext: ''45 maxCallFrameSize: 429496729546 cvBytesOfCalleeSavedRegisters: 047 hasOpaqueSPAdjustment: false48 hasVAStart: false49 hasMustTailInVarArgFunc: false50 hasTailCall: false51 localFrameSize: 052 savePoint: []53 restorePoint: []54fixedStack: []55stack:56 - { id: 0, name: a, type: default, offset: 0, size: 4, alignment: 4,57 stack-id: default, callee-saved-register: '', callee-saved-restored: true,58 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }59callSites: []60debugValueSubstitutions: []61constants: []62machineFunctionInfo:63 varArgsFrameIndex: 064 varArgsSaveSize: 065body: |66 bb.0.entry:67 ; CHECK-LABEL: name: main68 ; CHECK: $x10 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)69 ; CHECK-NEXT: $x11 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)70 ; CHECK-NEXT: $x12 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)71 ; CHECK-NEXT: $x13 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)72 ; CHECK-NEXT: $x14 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)73 ; CHECK-NEXT: $x15 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)74 ; CHECK-NEXT: $x16 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)75 ; CHECK-NEXT: $x17 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)76 ; CHECK-NEXT: $x5 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)77 ; CHECK-NEXT: $x6 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)78 ; CHECK-NEXT: $x7 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)79 ; CHECK-NEXT: $x28 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)80 ; CHECK-NEXT: $x29 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)81 ; CHECK-NEXT: $x30 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)82 ; CHECK-NEXT: $x31 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)83 ; CHECK-NEXT: $x8 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)84 ; CHECK-NEXT: $x9 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)85 ; CHECK-NEXT: $x18 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)86 ; CHECK-NEXT: $x19 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)87 ; CHECK-NEXT: $x20 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)88 ; CHECK-NEXT: $x21 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)89 ; CHECK-NEXT: $x22 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)90 ; CHECK-NEXT: $x23 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)91 ; CHECK-NEXT: $x24 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)92 ; CHECK-NEXT: $x25 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)93 ; CHECK-NEXT: $x26 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)94 ; CHECK-NEXT: $x27 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)95 ; CHECK-NEXT: renamable $x1 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)96 ; CHECK-NEXT: SW killed renamable $x1, %stack.1, 0 :: (store (s32) into %stack.1)97 ; CHECK-NEXT: renamable $x1 = LB %stack.0.a, 0 :: (volatile dereferenceable load (s8) from %ir.a)98 ; CHECK-NEXT: SW killed renamable $x1, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)99 ; CHECK-NEXT: renamable $x1 = LW %stack.1, 0 :: (load (s32) from %stack.1)100 ; CHECK-NEXT: SW killed renamable $x1, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)101 ; CHECK-NEXT: renamable $x1 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)102 ; CHECK-NEXT: SW killed renamable $x1, %stack.1, 0 :: (store (s32) into %stack.1)103 ; CHECK-NEXT: renamable $x1 = LB %stack.0.a, 0 :: (volatile dereferenceable load (s8) from %ir.a)104 ; CHECK-NEXT: SW killed renamable $x1, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)105 ; CHECK-NEXT: renamable $x1 = LW %stack.1, 0 :: (load (s32) from %stack.1)106 ; CHECK-NEXT: SW killed renamable $x1, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)107 ; CHECK-NEXT: SW $x10, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)108 ; CHECK-NEXT: SW $x11, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)109 ; CHECK-NEXT: SW $x12, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)110 ; CHECK-NEXT: SW $x13, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)111 ; CHECK-NEXT: SW $x14, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)112 ; CHECK-NEXT: SW $x15, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)113 ; CHECK-NEXT: SW $x16, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)114 ; CHECK-NEXT: SW $x17, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)115 ; CHECK-NEXT: SW $x5, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)116 ; CHECK-NEXT: SW $x6, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)117 ; CHECK-NEXT: SW $x7, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)118 ; CHECK-NEXT: SW $x28, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)119 ; CHECK-NEXT: SW $x29, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)120 ; CHECK-NEXT: SW $x30, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)121 ; CHECK-NEXT: SW $x31, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)122 ; CHECK-NEXT: SW $x8, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)123 ; CHECK-NEXT: SW $x9, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)124 ; CHECK-NEXT: SW $x18, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)125 ; CHECK-NEXT: SW $x19, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)126 ; CHECK-NEXT: SW $x20, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)127 ; CHECK-NEXT: SW $x21, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)128 ; CHECK-NEXT: SW $x22, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)129 ; CHECK-NEXT: SW $x23, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)130 ; CHECK-NEXT: SW $x24, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)131 ; CHECK-NEXT: SW $x25, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)132 ; CHECK-NEXT: SW $x26, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)133 ; CHECK-NEXT: SW $x27, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)134 ; CHECK-NEXT: $x10 = COPY $x0135 ; CHECK-NEXT: PseudoRET implicit $x10136 $x10 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)137 $x11 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)138 $x12 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)139 $x13 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)140 $x14 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)141 $x15 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)142 $x16 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)143 $x17 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)144 $x5 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)145 $x6 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)146 $x7 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)147 $x28 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)148 $x29 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)149 $x30 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)150 $x31 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)151 $x8 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)152 $x9 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)153 $x18 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)154 $x19 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)155 $x20 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)156 $x21 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)157 $x22 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)158 $x23 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)159 $x24 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)160 $x25 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)161 $x26 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)162 $x27 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)163 164 ; First vreg load165 %1:gpr = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)166 167 ; First faulty sequence; %1 spilt168 %12:gpr = LB %stack.0.a, 0 :: (volatile dereferenceable load (s8) from %ir.a)169 SW %12, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)170 171 ; Store %1 to avoid it being optimised out, will result in a load-from-spill172 SW %1, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)173 174 ; That code sequence a second time, to generate a second spill slot that175 ; will get coloured and merged.176 %2:gpr = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a)177 178 %22:gpr = LB %stack.0.a, 0 :: (volatile dereferenceable load (s8) from %ir.a)179 SW %22, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)180 181 SW %2, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)182 183 SW $x10, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)184 SW $x11, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)185 SW $x12, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)186 SW $x13, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)187 SW $x14, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)188 SW $x15, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)189 SW $x16, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)190 SW $x17, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)191 SW $x5, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)192 SW $x6, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)193 SW $x7, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)194 SW $x28, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)195 SW $x29, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)196 SW $x30, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)197 SW $x31, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)198 SW $x8, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)199 SW $x9, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)200 SW $x18, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)201 SW $x19, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)202 SW $x20, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)203 SW $x21, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)204 SW $x22, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)205 SW $x23, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)206 SW $x24, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)207 SW $x25, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)208 SW $x26, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)209 SW $x27, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)210 $x10 = COPY $x0211 PseudoRET implicit killed $x10212 213...214