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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I3; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I4; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb | FileCheck %s --check-prefix=RV32IZbb5; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb | FileCheck %s --check-prefix=RV64IZbb6 7define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {8; RV32I-LABEL: func:9; RV32I: # %bb.0:10; RV32I-NEXT: add a1, a0, a111; RV32I-NEXT: sltu a0, a1, a012; RV32I-NEXT: neg a0, a013; RV32I-NEXT: or a0, a0, a114; RV32I-NEXT: ret15;16; RV64I-LABEL: func:17; RV64I: # %bb.0:18; RV64I-NEXT: addw a1, a0, a119; RV64I-NEXT: sltu a0, a1, a020; RV64I-NEXT: neg a0, a021; RV64I-NEXT: or a0, a0, a122; RV64I-NEXT: ret23;24; RV32IZbb-LABEL: func:25; RV32IZbb: # %bb.0:26; RV32IZbb-NEXT: not a2, a127; RV32IZbb-NEXT: minu a0, a0, a228; RV32IZbb-NEXT: add a0, a0, a129; RV32IZbb-NEXT: ret30;31; RV64IZbb-LABEL: func:32; RV64IZbb: # %bb.0:33; RV64IZbb-NEXT: not a2, a134; RV64IZbb-NEXT: minu a0, a0, a235; RV64IZbb-NEXT: addw a0, a0, a136; RV64IZbb-NEXT: ret37 %tmp = call i32 @llvm.uadd.sat.i32(i32 %x, i32 %y);38 ret i32 %tmp;39}40 41define i64 @func2(i64 %x, i64 %y) nounwind {42; RV32I-LABEL: func2:43; RV32I: # %bb.0:44; RV32I-NEXT: add a3, a1, a345; RV32I-NEXT: add a2, a0, a246; RV32I-NEXT: sltu a0, a2, a047; RV32I-NEXT: add a3, a3, a048; RV32I-NEXT: beq a3, a1, .LBB1_249; RV32I-NEXT: # %bb.1:50; RV32I-NEXT: sltu a0, a3, a151; RV32I-NEXT: .LBB1_2:52; RV32I-NEXT: neg a1, a053; RV32I-NEXT: or a0, a1, a254; RV32I-NEXT: or a1, a1, a355; RV32I-NEXT: ret56;57; RV64I-LABEL: func2:58; RV64I: # %bb.0:59; RV64I-NEXT: add a1, a0, a160; RV64I-NEXT: sltu a0, a1, a061; RV64I-NEXT: neg a0, a062; RV64I-NEXT: or a0, a0, a163; RV64I-NEXT: ret64;65; RV32IZbb-LABEL: func2:66; RV32IZbb: # %bb.0:67; RV32IZbb-NEXT: add a3, a1, a368; RV32IZbb-NEXT: add a2, a0, a269; RV32IZbb-NEXT: sltu a0, a2, a070; RV32IZbb-NEXT: add a3, a3, a071; RV32IZbb-NEXT: beq a3, a1, .LBB1_272; RV32IZbb-NEXT: # %bb.1:73; RV32IZbb-NEXT: sltu a0, a3, a174; RV32IZbb-NEXT: .LBB1_2:75; RV32IZbb-NEXT: neg a1, a076; RV32IZbb-NEXT: or a0, a1, a277; RV32IZbb-NEXT: or a1, a1, a378; RV32IZbb-NEXT: ret79;80; RV64IZbb-LABEL: func2:81; RV64IZbb: # %bb.0:82; RV64IZbb-NEXT: not a2, a183; RV64IZbb-NEXT: minu a0, a0, a284; RV64IZbb-NEXT: add a0, a0, a185; RV64IZbb-NEXT: ret86 %tmp = call i64 @llvm.uadd.sat.i64(i64 %x, i64 %y);87 ret i64 %tmp;88}89 90define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y) nounwind {91; RV32I-LABEL: func16:92; RV32I: # %bb.0:93; RV32I-NEXT: add a0, a0, a194; RV32I-NEXT: lui a1, 1695; RV32I-NEXT: addi a1, a1, -196; RV32I-NEXT: bltu a0, a1, .LBB2_297; RV32I-NEXT: # %bb.1:98; RV32I-NEXT: mv a0, a199; RV32I-NEXT: .LBB2_2:100; RV32I-NEXT: ret101;102; RV64I-LABEL: func16:103; RV64I: # %bb.0:104; RV64I-NEXT: add a0, a0, a1105; RV64I-NEXT: lui a1, 16106; RV64I-NEXT: addi a1, a1, -1107; RV64I-NEXT: bltu a0, a1, .LBB2_2108; RV64I-NEXT: # %bb.1:109; RV64I-NEXT: mv a0, a1110; RV64I-NEXT: .LBB2_2:111; RV64I-NEXT: ret112;113; RV32IZbb-LABEL: func16:114; RV32IZbb: # %bb.0:115; RV32IZbb-NEXT: add a0, a0, a1116; RV32IZbb-NEXT: lui a1, 16117; RV32IZbb-NEXT: addi a1, a1, -1118; RV32IZbb-NEXT: minu a0, a0, a1119; RV32IZbb-NEXT: ret120;121; RV64IZbb-LABEL: func16:122; RV64IZbb: # %bb.0:123; RV64IZbb-NEXT: add a0, a0, a1124; RV64IZbb-NEXT: lui a1, 16125; RV64IZbb-NEXT: addi a1, a1, -1126; RV64IZbb-NEXT: minu a0, a0, a1127; RV64IZbb-NEXT: ret128 %tmp = call i16 @llvm.uadd.sat.i16(i16 %x, i16 %y);129 ret i16 %tmp;130}131 132define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y) nounwind {133; RV32I-LABEL: func8:134; RV32I: # %bb.0:135; RV32I-NEXT: add a0, a0, a1136; RV32I-NEXT: li a1, 255137; RV32I-NEXT: bltu a0, a1, .LBB3_2138; RV32I-NEXT: # %bb.1:139; RV32I-NEXT: li a0, 255140; RV32I-NEXT: .LBB3_2:141; RV32I-NEXT: ret142;143; RV64I-LABEL: func8:144; RV64I: # %bb.0:145; RV64I-NEXT: add a0, a0, a1146; RV64I-NEXT: li a1, 255147; RV64I-NEXT: bltu a0, a1, .LBB3_2148; RV64I-NEXT: # %bb.1:149; RV64I-NEXT: li a0, 255150; RV64I-NEXT: .LBB3_2:151; RV64I-NEXT: ret152;153; RV32IZbb-LABEL: func8:154; RV32IZbb: # %bb.0:155; RV32IZbb-NEXT: add a0, a0, a1156; RV32IZbb-NEXT: li a1, 255157; RV32IZbb-NEXT: minu a0, a0, a1158; RV32IZbb-NEXT: ret159;160; RV64IZbb-LABEL: func8:161; RV64IZbb: # %bb.0:162; RV64IZbb-NEXT: add a0, a0, a1163; RV64IZbb-NEXT: li a1, 255164; RV64IZbb-NEXT: minu a0, a0, a1165; RV64IZbb-NEXT: ret166 %tmp = call i8 @llvm.uadd.sat.i8(i8 %x, i8 %y);167 ret i8 %tmp;168}169 170define zeroext i4 @func3(i4 zeroext %x, i4 zeroext %y) nounwind {171; RV32I-LABEL: func3:172; RV32I: # %bb.0:173; RV32I-NEXT: add a0, a0, a1174; RV32I-NEXT: li a1, 15175; RV32I-NEXT: bltu a0, a1, .LBB4_2176; RV32I-NEXT: # %bb.1:177; RV32I-NEXT: li a0, 15178; RV32I-NEXT: .LBB4_2:179; RV32I-NEXT: ret180;181; RV64I-LABEL: func3:182; RV64I: # %bb.0:183; RV64I-NEXT: add a0, a0, a1184; RV64I-NEXT: li a1, 15185; RV64I-NEXT: bltu a0, a1, .LBB4_2186; RV64I-NEXT: # %bb.1:187; RV64I-NEXT: li a0, 15188; RV64I-NEXT: .LBB4_2:189; RV64I-NEXT: ret190;191; RV32IZbb-LABEL: func3:192; RV32IZbb: # %bb.0:193; RV32IZbb-NEXT: add a0, a0, a1194; RV32IZbb-NEXT: li a1, 15195; RV32IZbb-NEXT: minu a0, a0, a1196; RV32IZbb-NEXT: ret197;198; RV64IZbb-LABEL: func3:199; RV64IZbb: # %bb.0:200; RV64IZbb-NEXT: add a0, a0, a1201; RV64IZbb-NEXT: li a1, 15202; RV64IZbb-NEXT: minu a0, a0, a1203; RV64IZbb-NEXT: ret204 %tmp = call i4 @llvm.uadd.sat.i4(i4 %x, i4 %y);205 ret i4 %tmp;206}207