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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I3; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I4; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb | FileCheck %s --check-prefix=RV32IZbb5; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb | FileCheck %s --check-prefix=RV64IZbb6 7define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {8; RV32I-LABEL: func32:9; RV32I: # %bb.0:10; RV32I-NEXT: mul a1, a1, a211; RV32I-NEXT: add a1, a0, a112; RV32I-NEXT: sltu a0, a1, a013; RV32I-NEXT: neg a0, a014; RV32I-NEXT: or a0, a0, a115; RV32I-NEXT: ret16;17; RV64I-LABEL: func32:18; RV64I: # %bb.0:19; RV64I-NEXT: mul a1, a1, a220; RV64I-NEXT: addw a1, a0, a121; RV64I-NEXT: sext.w a0, a022; RV64I-NEXT: sltu a0, a1, a023; RV64I-NEXT: neg a0, a024; RV64I-NEXT: or a0, a0, a125; RV64I-NEXT: ret26;27; RV32IZbb-LABEL: func32:28; RV32IZbb: # %bb.0:29; RV32IZbb-NEXT: mul a1, a1, a230; RV32IZbb-NEXT: not a2, a131; RV32IZbb-NEXT: minu a0, a0, a232; RV32IZbb-NEXT: add a0, a0, a133; RV32IZbb-NEXT: ret34;35; RV64IZbb-LABEL: func32:36; RV64IZbb: # %bb.0:37; RV64IZbb-NEXT: sext.w a0, a038; RV64IZbb-NEXT: mulw a1, a1, a239; RV64IZbb-NEXT: not a2, a140; RV64IZbb-NEXT: minu a0, a0, a241; RV64IZbb-NEXT: add a0, a0, a142; RV64IZbb-NEXT: ret43 %a = mul i32 %y, %z44 %tmp = call i32 @llvm.uadd.sat.i32(i32 %x, i32 %a)45 ret i32 %tmp46}47 48define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {49; RV32I-LABEL: func64:50; RV32I: # %bb.0:51; RV32I-NEXT: add a2, a1, a552; RV32I-NEXT: add a4, a0, a453; RV32I-NEXT: sltu a0, a4, a054; RV32I-NEXT: add a2, a2, a055; RV32I-NEXT: beq a2, a1, .LBB1_256; RV32I-NEXT: # %bb.1:57; RV32I-NEXT: sltu a0, a2, a158; RV32I-NEXT: .LBB1_2:59; RV32I-NEXT: neg a1, a060; RV32I-NEXT: or a0, a1, a461; RV32I-NEXT: or a1, a1, a262; RV32I-NEXT: ret63;64; RV64I-LABEL: func64:65; RV64I: # %bb.0:66; RV64I-NEXT: add a2, a0, a267; RV64I-NEXT: sltu a0, a2, a068; RV64I-NEXT: neg a0, a069; RV64I-NEXT: or a0, a0, a270; RV64I-NEXT: ret71;72; RV32IZbb-LABEL: func64:73; RV32IZbb: # %bb.0:74; RV32IZbb-NEXT: add a2, a1, a575; RV32IZbb-NEXT: add a4, a0, a476; RV32IZbb-NEXT: sltu a0, a4, a077; RV32IZbb-NEXT: add a2, a2, a078; RV32IZbb-NEXT: beq a2, a1, .LBB1_279; RV32IZbb-NEXT: # %bb.1:80; RV32IZbb-NEXT: sltu a0, a2, a181; RV32IZbb-NEXT: .LBB1_2:82; RV32IZbb-NEXT: neg a1, a083; RV32IZbb-NEXT: or a0, a1, a484; RV32IZbb-NEXT: or a1, a1, a285; RV32IZbb-NEXT: ret86;87; RV64IZbb-LABEL: func64:88; RV64IZbb: # %bb.0:89; RV64IZbb-NEXT: not a1, a290; RV64IZbb-NEXT: minu a0, a0, a191; RV64IZbb-NEXT: add a0, a0, a292; RV64IZbb-NEXT: ret93 %a = mul i64 %y, %z94 %tmp = call i64 @llvm.uadd.sat.i64(i64 %x, i64 %z)95 ret i64 %tmp96}97 98define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {99; RV32I-LABEL: func16:100; RV32I: # %bb.0:101; RV32I-NEXT: lui a3, 16102; RV32I-NEXT: mul a2, a1, a2103; RV32I-NEXT: addi a1, a3, -1104; RV32I-NEXT: and a0, a0, a1105; RV32I-NEXT: and a2, a2, a1106; RV32I-NEXT: add a0, a0, a2107; RV32I-NEXT: bltu a0, a1, .LBB2_2108; RV32I-NEXT: # %bb.1:109; RV32I-NEXT: mv a0, a1110; RV32I-NEXT: .LBB2_2:111; RV32I-NEXT: ret112;113; RV64I-LABEL: func16:114; RV64I: # %bb.0:115; RV64I-NEXT: lui a3, 16116; RV64I-NEXT: mul a2, a1, a2117; RV64I-NEXT: addi a1, a3, -1118; RV64I-NEXT: and a0, a0, a1119; RV64I-NEXT: and a2, a2, a1120; RV64I-NEXT: add a0, a0, a2121; RV64I-NEXT: bltu a0, a1, .LBB2_2122; RV64I-NEXT: # %bb.1:123; RV64I-NEXT: mv a0, a1124; RV64I-NEXT: .LBB2_2:125; RV64I-NEXT: ret126;127; RV32IZbb-LABEL: func16:128; RV32IZbb: # %bb.0:129; RV32IZbb-NEXT: zext.h a0, a0130; RV32IZbb-NEXT: mul a1, a1, a2131; RV32IZbb-NEXT: lui a2, 16132; RV32IZbb-NEXT: zext.h a1, a1133; RV32IZbb-NEXT: add a0, a0, a1134; RV32IZbb-NEXT: addi a2, a2, -1135; RV32IZbb-NEXT: minu a0, a0, a2136; RV32IZbb-NEXT: ret137;138; RV64IZbb-LABEL: func16:139; RV64IZbb: # %bb.0:140; RV64IZbb-NEXT: zext.h a0, a0141; RV64IZbb-NEXT: mul a1, a1, a2142; RV64IZbb-NEXT: lui a2, 16143; RV64IZbb-NEXT: zext.h a1, a1144; RV64IZbb-NEXT: add a0, a0, a1145; RV64IZbb-NEXT: addi a2, a2, -1146; RV64IZbb-NEXT: minu a0, a0, a2147; RV64IZbb-NEXT: ret148 %a = mul i16 %y, %z149 %tmp = call i16 @llvm.uadd.sat.i16(i16 %x, i16 %a)150 ret i16 %tmp151}152 153define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {154; RV32I-LABEL: func8:155; RV32I: # %bb.0:156; RV32I-NEXT: zext.b a0, a0157; RV32I-NEXT: mul a1, a1, a2158; RV32I-NEXT: zext.b a1, a1159; RV32I-NEXT: add a0, a0, a1160; RV32I-NEXT: li a1, 255161; RV32I-NEXT: bltu a0, a1, .LBB3_2162; RV32I-NEXT: # %bb.1:163; RV32I-NEXT: li a0, 255164; RV32I-NEXT: .LBB3_2:165; RV32I-NEXT: ret166;167; RV64I-LABEL: func8:168; RV64I: # %bb.0:169; RV64I-NEXT: zext.b a0, a0170; RV64I-NEXT: mul a1, a1, a2171; RV64I-NEXT: zext.b a1, a1172; RV64I-NEXT: add a0, a0, a1173; RV64I-NEXT: li a1, 255174; RV64I-NEXT: bltu a0, a1, .LBB3_2175; RV64I-NEXT: # %bb.1:176; RV64I-NEXT: li a0, 255177; RV64I-NEXT: .LBB3_2:178; RV64I-NEXT: ret179;180; RV32IZbb-LABEL: func8:181; RV32IZbb: # %bb.0:182; RV32IZbb-NEXT: zext.b a0, a0183; RV32IZbb-NEXT: mul a1, a1, a2184; RV32IZbb-NEXT: zext.b a1, a1185; RV32IZbb-NEXT: add a0, a0, a1186; RV32IZbb-NEXT: li a1, 255187; RV32IZbb-NEXT: minu a0, a0, a1188; RV32IZbb-NEXT: ret189;190; RV64IZbb-LABEL: func8:191; RV64IZbb: # %bb.0:192; RV64IZbb-NEXT: zext.b a0, a0193; RV64IZbb-NEXT: mul a1, a1, a2194; RV64IZbb-NEXT: zext.b a1, a1195; RV64IZbb-NEXT: add a0, a0, a1196; RV64IZbb-NEXT: li a1, 255197; RV64IZbb-NEXT: minu a0, a0, a1198; RV64IZbb-NEXT: ret199 %a = mul i8 %y, %z200 %tmp = call i8 @llvm.uadd.sat.i8(i8 %x, i8 %a)201 ret i8 %tmp202}203 204define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {205; RV32I-LABEL: func4:206; RV32I: # %bb.0:207; RV32I-NEXT: andi a0, a0, 15208; RV32I-NEXT: mul a1, a1, a2209; RV32I-NEXT: andi a1, a1, 15210; RV32I-NEXT: add a0, a0, a1211; RV32I-NEXT: li a1, 15212; RV32I-NEXT: bltu a0, a1, .LBB4_2213; RV32I-NEXT: # %bb.1:214; RV32I-NEXT: li a0, 15215; RV32I-NEXT: .LBB4_2:216; RV32I-NEXT: ret217;218; RV64I-LABEL: func4:219; RV64I: # %bb.0:220; RV64I-NEXT: andi a0, a0, 15221; RV64I-NEXT: mul a1, a1, a2222; RV64I-NEXT: andi a1, a1, 15223; RV64I-NEXT: add a0, a0, a1224; RV64I-NEXT: li a1, 15225; RV64I-NEXT: bltu a0, a1, .LBB4_2226; RV64I-NEXT: # %bb.1:227; RV64I-NEXT: li a0, 15228; RV64I-NEXT: .LBB4_2:229; RV64I-NEXT: ret230;231; RV32IZbb-LABEL: func4:232; RV32IZbb: # %bb.0:233; RV32IZbb-NEXT: andi a0, a0, 15234; RV32IZbb-NEXT: mul a1, a1, a2235; RV32IZbb-NEXT: andi a1, a1, 15236; RV32IZbb-NEXT: add a0, a0, a1237; RV32IZbb-NEXT: li a1, 15238; RV32IZbb-NEXT: minu a0, a0, a1239; RV32IZbb-NEXT: ret240;241; RV64IZbb-LABEL: func4:242; RV64IZbb: # %bb.0:243; RV64IZbb-NEXT: andi a0, a0, 15244; RV64IZbb-NEXT: mul a1, a1, a2245; RV64IZbb-NEXT: andi a1, a1, 15246; RV64IZbb-NEXT: add a0, a0, a1247; RV64IZbb-NEXT: li a1, 15248; RV64IZbb-NEXT: minu a0, a0, a1249; RV64IZbb-NEXT: ret250 %a = mul i4 %y, %z251 %tmp = call i4 @llvm.uadd.sat.i4(i4 %x, i4 %a)252 ret i4 %tmp253}254