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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefixes=RISCV323 4define { i128, i8 } @muloti_test(i128 %l, i128 %r) #0 {5; RISCV32-LABEL: muloti_test:6; RISCV32: # %bb.0: # %start7; RISCV32-NEXT: addi sp, sp, -328; RISCV32-NEXT: sw s0, 28(sp) # 4-byte Folded Spill9; RISCV32-NEXT: sw s1, 24(sp) # 4-byte Folded Spill10; RISCV32-NEXT: sw s2, 20(sp) # 4-byte Folded Spill11; RISCV32-NEXT: sw s3, 16(sp) # 4-byte Folded Spill12; RISCV32-NEXT: sw s4, 12(sp) # 4-byte Folded Spill13; RISCV32-NEXT: sw s5, 8(sp) # 4-byte Folded Spill14; RISCV32-NEXT: lw a4, 0(a1)15; RISCV32-NEXT: lw t0, 4(a1)16; RISCV32-NEXT: lw a3, 8(a1)17; RISCV32-NEXT: lw a1, 12(a1)18; RISCV32-NEXT: lw a6, 0(a2)19; RISCV32-NEXT: lw a5, 4(a2)20; RISCV32-NEXT: lw a7, 8(a2)21; RISCV32-NEXT: lw a2, 12(a2)22; RISCV32-NEXT: mulhu t1, a4, a623; RISCV32-NEXT: mul t2, t0, a624; RISCV32-NEXT: mulhu t3, t0, a625; RISCV32-NEXT: mul t4, a4, a526; RISCV32-NEXT: mulhu t5, a4, a527; RISCV32-NEXT: mul s2, t0, a528; RISCV32-NEXT: mul t6, a7, a429; RISCV32-NEXT: mul s3, a3, a630; RISCV32-NEXT: mul s0, t0, a731; RISCV32-NEXT: mul s1, a2, a432; RISCV32-NEXT: mul s4, a5, a333; RISCV32-NEXT: add s1, s1, s034; RISCV32-NEXT: mul s0, a1, a635; RISCV32-NEXT: add s4, s0, s436; RISCV32-NEXT: mulhu s5, t0, a537; RISCV32-NEXT: add t1, t2, t138; RISCV32-NEXT: sltu t2, t1, t239; RISCV32-NEXT: add t2, t3, t240; RISCV32-NEXT: mulhu s0, a7, a441; RISCV32-NEXT: add t1, t4, t142; RISCV32-NEXT: sltu t3, t1, t443; RISCV32-NEXT: add t3, t5, t344; RISCV32-NEXT: mulhu t5, a3, a645; RISCV32-NEXT: add t4, s3, t646; RISCV32-NEXT: add s1, s0, s147; RISCV32-NEXT: add t6, t5, s448; RISCV32-NEXT: sltu s3, t4, s349; RISCV32-NEXT: add t3, t2, t350; RISCV32-NEXT: sltu t2, t3, t251; RISCV32-NEXT: add s5, s5, t252; RISCV32-NEXT: add s4, t6, s153; RISCV32-NEXT: add t3, s2, t354; RISCV32-NEXT: add t2, t3, t455; RISCV32-NEXT: sltu s2, t3, s256; RISCV32-NEXT: sltu t4, t2, t357; RISCV32-NEXT: add s2, s5, s258; RISCV32-NEXT: add s3, s4, s359; RISCV32-NEXT: add t3, s2, s360; RISCV32-NEXT: add t3, t3, t461; RISCV32-NEXT: beq t3, s2, .LBB0_262; RISCV32-NEXT: # %bb.1: # %start63; RISCV32-NEXT: sltu t4, t3, s264; RISCV32-NEXT: .LBB0_2: # %start65; RISCV32-NEXT: sltu s0, s1, s066; RISCV32-NEXT: snez s1, t067; RISCV32-NEXT: snez s2, a268; RISCV32-NEXT: sltu t5, t6, t569; RISCV32-NEXT: mulhu t6, a2, a470; RISCV32-NEXT: mulhu t0, t0, a771; RISCV32-NEXT: or a2, a7, a272; RISCV32-NEXT: snez a7, a573; RISCV32-NEXT: mul a4, a4, a674; RISCV32-NEXT: mulhu a6, a1, a675; RISCV32-NEXT: mulhu a5, a5, a376; RISCV32-NEXT: or a3, a3, a177; RISCV32-NEXT: snez a1, a178; RISCV32-NEXT: and s1, s2, s179; RISCV32-NEXT: snez t6, t680; RISCV32-NEXT: snez t0, t081; RISCV32-NEXT: and a1, a1, a782; RISCV32-NEXT: snez a6, a683; RISCV32-NEXT: snez a5, a584; RISCV32-NEXT: snez a2, a285; RISCV32-NEXT: snez a3, a386; RISCV32-NEXT: or a7, s1, t687; RISCV32-NEXT: or a1, a1, a688; RISCV32-NEXT: and a2, a3, a289; RISCV32-NEXT: or a3, a7, t090; RISCV32-NEXT: or a1, a1, a591; RISCV32-NEXT: or a3, a3, s092; RISCV32-NEXT: or a1, a1, t593; RISCV32-NEXT: or a1, a2, a194; RISCV32-NEXT: or a1, a1, a395; RISCV32-NEXT: or a1, a1, t496; RISCV32-NEXT: andi a1, a1, 197; RISCV32-NEXT: sw a4, 0(a0)98; RISCV32-NEXT: sw t1, 4(a0)99; RISCV32-NEXT: sw t2, 8(a0)100; RISCV32-NEXT: sw t3, 12(a0)101; RISCV32-NEXT: sb a1, 16(a0)102; RISCV32-NEXT: lw s0, 28(sp) # 4-byte Folded Reload103; RISCV32-NEXT: lw s1, 24(sp) # 4-byte Folded Reload104; RISCV32-NEXT: lw s2, 20(sp) # 4-byte Folded Reload105; RISCV32-NEXT: lw s3, 16(sp) # 4-byte Folded Reload106; RISCV32-NEXT: lw s4, 12(sp) # 4-byte Folded Reload107; RISCV32-NEXT: lw s5, 8(sp) # 4-byte Folded Reload108; RISCV32-NEXT: addi sp, sp, 32109; RISCV32-NEXT: ret110start:111 %0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r) #2112 %1 = extractvalue { i128, i1 } %0, 0113 %2 = extractvalue { i128, i1 } %0, 1114 %3 = zext i1 %2 to i8115 %4 = insertvalue { i128, i8 } poison, i128 %1, 0116 %5 = insertvalue { i128, i8 } %4, i8 %3, 1117 ret { i128, i8 } %5118}119 120; Function Attrs: nounwind readnone speculatable121 122attributes #0 = { nounwind readnone }123attributes #2 = { nounwind }124