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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I3; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I4; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb | FileCheck %s --check-prefix=RV32IZbb5; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb | FileCheck %s --check-prefix=RV64IZbb6 7define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {8; RV32I-LABEL: func:9; RV32I: # %bb.0:10; RV32I-NEXT: sub a1, a0, a111; RV32I-NEXT: sltu a0, a0, a112; RV32I-NEXT: addi a0, a0, -113; RV32I-NEXT: and a0, a0, a114; RV32I-NEXT: ret15;16; RV64I-LABEL: func:17; RV64I: # %bb.0:18; RV64I-NEXT: subw a1, a0, a119; RV64I-NEXT: sltu a0, a0, a120; RV64I-NEXT: addi a0, a0, -121; RV64I-NEXT: and a0, a0, a122; RV64I-NEXT: ret23;24; RV32IZbb-LABEL: func:25; RV32IZbb: # %bb.0:26; RV32IZbb-NEXT: maxu a0, a0, a127; RV32IZbb-NEXT: sub a0, a0, a128; RV32IZbb-NEXT: ret29;30; RV64IZbb-LABEL: func:31; RV64IZbb: # %bb.0:32; RV64IZbb-NEXT: maxu a0, a0, a133; RV64IZbb-NEXT: subw a0, a0, a134; RV64IZbb-NEXT: ret35 %tmp = call i32 @llvm.usub.sat.i32(i32 %x, i32 %y);36 ret i32 %tmp;37}38 39define i64 @func2(i64 %x, i64 %y) nounwind {40; RV32I-LABEL: func2:41; RV32I: # %bb.0:42; RV32I-NEXT: sltu a4, a0, a243; RV32I-NEXT: sub a3, a1, a344; RV32I-NEXT: sub a3, a3, a445; RV32I-NEXT: sub a2, a0, a246; RV32I-NEXT: beq a3, a1, .LBB1_247; RV32I-NEXT: # %bb.1:48; RV32I-NEXT: sltu a0, a1, a349; RV32I-NEXT: j .LBB1_350; RV32I-NEXT: .LBB1_2:51; RV32I-NEXT: sltu a0, a0, a252; RV32I-NEXT: .LBB1_3:53; RV32I-NEXT: addi a1, a0, -154; RV32I-NEXT: and a0, a1, a255; RV32I-NEXT: and a1, a1, a356; RV32I-NEXT: ret57;58; RV64I-LABEL: func2:59; RV64I: # %bb.0:60; RV64I-NEXT: sub a1, a0, a161; RV64I-NEXT: sltu a0, a0, a162; RV64I-NEXT: addi a0, a0, -163; RV64I-NEXT: and a0, a0, a164; RV64I-NEXT: ret65;66; RV32IZbb-LABEL: func2:67; RV32IZbb: # %bb.0:68; RV32IZbb-NEXT: sltu a4, a0, a269; RV32IZbb-NEXT: sub a3, a1, a370; RV32IZbb-NEXT: sub a3, a3, a471; RV32IZbb-NEXT: sub a2, a0, a272; RV32IZbb-NEXT: beq a3, a1, .LBB1_273; RV32IZbb-NEXT: # %bb.1:74; RV32IZbb-NEXT: sltu a0, a1, a375; RV32IZbb-NEXT: j .LBB1_376; RV32IZbb-NEXT: .LBB1_2:77; RV32IZbb-NEXT: sltu a0, a0, a278; RV32IZbb-NEXT: .LBB1_3:79; RV32IZbb-NEXT: addi a1, a0, -180; RV32IZbb-NEXT: and a0, a1, a281; RV32IZbb-NEXT: and a1, a1, a382; RV32IZbb-NEXT: ret83;84; RV64IZbb-LABEL: func2:85; RV64IZbb: # %bb.0:86; RV64IZbb-NEXT: maxu a0, a0, a187; RV64IZbb-NEXT: sub a0, a0, a188; RV64IZbb-NEXT: ret89 %tmp = call i64 @llvm.usub.sat.i64(i64 %x, i64 %y);90 ret i64 %tmp;91}92 93define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y) nounwind {94; RV32I-LABEL: func16:95; RV32I: # %bb.0:96; RV32I-NEXT: sub a1, a0, a197; RV32I-NEXT: sltu a0, a0, a198; RV32I-NEXT: addi a0, a0, -199; RV32I-NEXT: and a0, a0, a1100; RV32I-NEXT: ret101;102; RV64I-LABEL: func16:103; RV64I: # %bb.0:104; RV64I-NEXT: sub a1, a0, a1105; RV64I-NEXT: sltu a0, a0, a1106; RV64I-NEXT: addi a0, a0, -1107; RV64I-NEXT: and a0, a0, a1108; RV64I-NEXT: ret109;110; RV32IZbb-LABEL: func16:111; RV32IZbb: # %bb.0:112; RV32IZbb-NEXT: maxu a0, a0, a1113; RV32IZbb-NEXT: sub a0, a0, a1114; RV32IZbb-NEXT: ret115;116; RV64IZbb-LABEL: func16:117; RV64IZbb: # %bb.0:118; RV64IZbb-NEXT: maxu a0, a0, a1119; RV64IZbb-NEXT: sub a0, a0, a1120; RV64IZbb-NEXT: ret121 %tmp = call i16 @llvm.usub.sat.i16(i16 %x, i16 %y);122 ret i16 %tmp;123}124 125define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y) nounwind {126; RV32I-LABEL: func8:127; RV32I: # %bb.0:128; RV32I-NEXT: sub a1, a0, a1129; RV32I-NEXT: sltu a0, a0, a1130; RV32I-NEXT: addi a0, a0, -1131; RV32I-NEXT: and a0, a0, a1132; RV32I-NEXT: ret133;134; RV64I-LABEL: func8:135; RV64I: # %bb.0:136; RV64I-NEXT: sub a1, a0, a1137; RV64I-NEXT: sltu a0, a0, a1138; RV64I-NEXT: addi a0, a0, -1139; RV64I-NEXT: and a0, a0, a1140; RV64I-NEXT: ret141;142; RV32IZbb-LABEL: func8:143; RV32IZbb: # %bb.0:144; RV32IZbb-NEXT: maxu a0, a0, a1145; RV32IZbb-NEXT: sub a0, a0, a1146; RV32IZbb-NEXT: ret147;148; RV64IZbb-LABEL: func8:149; RV64IZbb: # %bb.0:150; RV64IZbb-NEXT: maxu a0, a0, a1151; RV64IZbb-NEXT: sub a0, a0, a1152; RV64IZbb-NEXT: ret153 %tmp = call i8 @llvm.usub.sat.i8(i8 %x, i8 %y);154 ret i8 %tmp;155}156 157define zeroext i4 @func3(i4 zeroext %x, i4 zeroext %y) nounwind {158; RV32I-LABEL: func3:159; RV32I: # %bb.0:160; RV32I-NEXT: sub a1, a0, a1161; RV32I-NEXT: sltu a0, a0, a1162; RV32I-NEXT: addi a0, a0, -1163; RV32I-NEXT: and a0, a0, a1164; RV32I-NEXT: ret165;166; RV64I-LABEL: func3:167; RV64I: # %bb.0:168; RV64I-NEXT: sub a1, a0, a1169; RV64I-NEXT: sltu a0, a0, a1170; RV64I-NEXT: addi a0, a0, -1171; RV64I-NEXT: and a0, a0, a1172; RV64I-NEXT: ret173;174; RV32IZbb-LABEL: func3:175; RV32IZbb: # %bb.0:176; RV32IZbb-NEXT: maxu a0, a0, a1177; RV32IZbb-NEXT: sub a0, a0, a1178; RV32IZbb-NEXT: ret179;180; RV64IZbb-LABEL: func3:181; RV64IZbb: # %bb.0:182; RV64IZbb-NEXT: maxu a0, a0, a1183; RV64IZbb-NEXT: sub a0, a0, a1184; RV64IZbb-NEXT: ret185 %tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %y);186 ret i4 %tmp;187}188