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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I3; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I4; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb | FileCheck %s --check-prefix=RV32IZbb5; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb | FileCheck %s --check-prefix=RV64IZbb6 7define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {8; RV32I-LABEL: func32:9; RV32I: # %bb.0:10; RV32I-NEXT: mul a1, a1, a211; RV32I-NEXT: sub a1, a0, a112; RV32I-NEXT: sltu a0, a0, a113; RV32I-NEXT: addi a0, a0, -114; RV32I-NEXT: and a0, a0, a115; RV32I-NEXT: ret16;17; RV64I-LABEL: func32:18; RV64I: # %bb.0:19; RV64I-NEXT: mul a1, a1, a220; RV64I-NEXT: subw a1, a0, a121; RV64I-NEXT: sext.w a0, a022; RV64I-NEXT: sltu a0, a0, a123; RV64I-NEXT: addi a0, a0, -124; RV64I-NEXT: and a0, a0, a125; RV64I-NEXT: ret26;27; RV32IZbb-LABEL: func32:28; RV32IZbb: # %bb.0:29; RV32IZbb-NEXT: mul a1, a1, a230; RV32IZbb-NEXT: maxu a0, a0, a131; RV32IZbb-NEXT: sub a0, a0, a132; RV32IZbb-NEXT: ret33;34; RV64IZbb-LABEL: func32:35; RV64IZbb: # %bb.0:36; RV64IZbb-NEXT: sext.w a0, a037; RV64IZbb-NEXT: mulw a1, a1, a238; RV64IZbb-NEXT: maxu a0, a0, a139; RV64IZbb-NEXT: sub a0, a0, a140; RV64IZbb-NEXT: ret41 %a = mul i32 %y, %z42 %tmp = call i32 @llvm.usub.sat.i32(i32 %x, i32 %a)43 ret i32 %tmp44}45 46define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {47; RV32I-LABEL: func64:48; RV32I: # %bb.0:49; RV32I-NEXT: sltu a2, a0, a450; RV32I-NEXT: sub a3, a1, a551; RV32I-NEXT: sub a2, a3, a252; RV32I-NEXT: sub a3, a0, a453; RV32I-NEXT: beq a2, a1, .LBB1_254; RV32I-NEXT: # %bb.1:55; RV32I-NEXT: sltu a0, a1, a256; RV32I-NEXT: j .LBB1_357; RV32I-NEXT: .LBB1_2:58; RV32I-NEXT: sltu a0, a0, a359; RV32I-NEXT: .LBB1_3:60; RV32I-NEXT: addi a1, a0, -161; RV32I-NEXT: and a0, a1, a362; RV32I-NEXT: and a1, a1, a263; RV32I-NEXT: ret64;65; RV64I-LABEL: func64:66; RV64I: # %bb.0:67; RV64I-NEXT: sub a1, a0, a268; RV64I-NEXT: sltu a0, a0, a169; RV64I-NEXT: addi a0, a0, -170; RV64I-NEXT: and a0, a0, a171; RV64I-NEXT: ret72;73; RV32IZbb-LABEL: func64:74; RV32IZbb: # %bb.0:75; RV32IZbb-NEXT: sltu a2, a0, a476; RV32IZbb-NEXT: sub a3, a1, a577; RV32IZbb-NEXT: sub a2, a3, a278; RV32IZbb-NEXT: sub a3, a0, a479; RV32IZbb-NEXT: beq a2, a1, .LBB1_280; RV32IZbb-NEXT: # %bb.1:81; RV32IZbb-NEXT: sltu a0, a1, a282; RV32IZbb-NEXT: j .LBB1_383; RV32IZbb-NEXT: .LBB1_2:84; RV32IZbb-NEXT: sltu a0, a0, a385; RV32IZbb-NEXT: .LBB1_3:86; RV32IZbb-NEXT: addi a1, a0, -187; RV32IZbb-NEXT: and a0, a1, a388; RV32IZbb-NEXT: and a1, a1, a289; RV32IZbb-NEXT: ret90;91; RV64IZbb-LABEL: func64:92; RV64IZbb: # %bb.0:93; RV64IZbb-NEXT: maxu a0, a0, a294; RV64IZbb-NEXT: sub a0, a0, a295; RV64IZbb-NEXT: ret96 %a = mul i64 %y, %z97 %tmp = call i64 @llvm.usub.sat.i64(i64 %x, i64 %z)98 ret i64 %tmp99}100 101define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {102; RV32I-LABEL: func16:103; RV32I: # %bb.0:104; RV32I-NEXT: lui a3, 16105; RV32I-NEXT: mul a1, a1, a2106; RV32I-NEXT: addi a3, a3, -1107; RV32I-NEXT: and a0, a0, a3108; RV32I-NEXT: and a1, a1, a3109; RV32I-NEXT: sub a1, a0, a1110; RV32I-NEXT: sltu a0, a0, a1111; RV32I-NEXT: addi a0, a0, -1112; RV32I-NEXT: and a0, a0, a1113; RV32I-NEXT: ret114;115; RV64I-LABEL: func16:116; RV64I: # %bb.0:117; RV64I-NEXT: lui a3, 16118; RV64I-NEXT: mul a1, a1, a2119; RV64I-NEXT: addi a3, a3, -1120; RV64I-NEXT: and a0, a0, a3121; RV64I-NEXT: and a1, a1, a3122; RV64I-NEXT: sub a1, a0, a1123; RV64I-NEXT: sltu a0, a0, a1124; RV64I-NEXT: addi a0, a0, -1125; RV64I-NEXT: and a0, a0, a1126; RV64I-NEXT: ret127;128; RV32IZbb-LABEL: func16:129; RV32IZbb: # %bb.0:130; RV32IZbb-NEXT: zext.h a0, a0131; RV32IZbb-NEXT: mul a1, a1, a2132; RV32IZbb-NEXT: zext.h a1, a1133; RV32IZbb-NEXT: maxu a0, a0, a1134; RV32IZbb-NEXT: sub a0, a0, a1135; RV32IZbb-NEXT: ret136;137; RV64IZbb-LABEL: func16:138; RV64IZbb: # %bb.0:139; RV64IZbb-NEXT: zext.h a0, a0140; RV64IZbb-NEXT: mul a1, a1, a2141; RV64IZbb-NEXT: zext.h a1, a1142; RV64IZbb-NEXT: maxu a0, a0, a1143; RV64IZbb-NEXT: sub a0, a0, a1144; RV64IZbb-NEXT: ret145 %a = mul i16 %y, %z146 %tmp = call i16 @llvm.usub.sat.i16(i16 %x, i16 %a)147 ret i16 %tmp148}149 150define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {151; RV32I-LABEL: func8:152; RV32I: # %bb.0:153; RV32I-NEXT: zext.b a0, a0154; RV32I-NEXT: mul a1, a1, a2155; RV32I-NEXT: zext.b a1, a1156; RV32I-NEXT: sub a1, a0, a1157; RV32I-NEXT: sltu a0, a0, a1158; RV32I-NEXT: addi a0, a0, -1159; RV32I-NEXT: and a0, a0, a1160; RV32I-NEXT: ret161;162; RV64I-LABEL: func8:163; RV64I: # %bb.0:164; RV64I-NEXT: zext.b a0, a0165; RV64I-NEXT: mul a1, a1, a2166; RV64I-NEXT: zext.b a1, a1167; RV64I-NEXT: sub a1, a0, a1168; RV64I-NEXT: sltu a0, a0, a1169; RV64I-NEXT: addi a0, a0, -1170; RV64I-NEXT: and a0, a0, a1171; RV64I-NEXT: ret172;173; RV32IZbb-LABEL: func8:174; RV32IZbb: # %bb.0:175; RV32IZbb-NEXT: zext.b a0, a0176; RV32IZbb-NEXT: mul a1, a1, a2177; RV32IZbb-NEXT: zext.b a1, a1178; RV32IZbb-NEXT: maxu a0, a0, a1179; RV32IZbb-NEXT: sub a0, a0, a1180; RV32IZbb-NEXT: ret181;182; RV64IZbb-LABEL: func8:183; RV64IZbb: # %bb.0:184; RV64IZbb-NEXT: zext.b a0, a0185; RV64IZbb-NEXT: mul a1, a1, a2186; RV64IZbb-NEXT: zext.b a1, a1187; RV64IZbb-NEXT: maxu a0, a0, a1188; RV64IZbb-NEXT: sub a0, a0, a1189; RV64IZbb-NEXT: ret190 %a = mul i8 %y, %z191 %tmp = call i8 @llvm.usub.sat.i8(i8 %x, i8 %a)192 ret i8 %tmp193}194 195define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {196; RV32I-LABEL: func4:197; RV32I: # %bb.0:198; RV32I-NEXT: andi a0, a0, 15199; RV32I-NEXT: mul a1, a1, a2200; RV32I-NEXT: andi a1, a1, 15201; RV32I-NEXT: sub a1, a0, a1202; RV32I-NEXT: sltu a0, a0, a1203; RV32I-NEXT: addi a0, a0, -1204; RV32I-NEXT: and a0, a0, a1205; RV32I-NEXT: ret206;207; RV64I-LABEL: func4:208; RV64I: # %bb.0:209; RV64I-NEXT: andi a0, a0, 15210; RV64I-NEXT: mul a1, a1, a2211; RV64I-NEXT: andi a1, a1, 15212; RV64I-NEXT: sub a1, a0, a1213; RV64I-NEXT: sltu a0, a0, a1214; RV64I-NEXT: addi a0, a0, -1215; RV64I-NEXT: and a0, a0, a1216; RV64I-NEXT: ret217;218; RV32IZbb-LABEL: func4:219; RV32IZbb: # %bb.0:220; RV32IZbb-NEXT: andi a0, a0, 15221; RV32IZbb-NEXT: mul a1, a1, a2222; RV32IZbb-NEXT: andi a1, a1, 15223; RV32IZbb-NEXT: maxu a0, a0, a1224; RV32IZbb-NEXT: sub a0, a0, a1225; RV32IZbb-NEXT: ret226;227; RV64IZbb-LABEL: func4:228; RV64IZbb: # %bb.0:229; RV64IZbb-NEXT: andi a0, a0, 15230; RV64IZbb-NEXT: mul a1, a1, a2231; RV64IZbb-NEXT: andi a1, a1, 15232; RV64IZbb-NEXT: maxu a0, a0, a1233; RV64IZbb-NEXT: sub a0, a0, a1234; RV64IZbb-NEXT: ret235 %a = mul i4 %y, %z236 %tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %a)237 ret i4 %tmp238}239