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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=riscv64 -mattr=+m,+v < %s | FileCheck %s3 4define i32 @madd_scalar(i32 %m00, i32 %m01, i32 %m10, i32 %m11) nounwind {5; CHECK-LABEL: madd_scalar:6; CHECK: # %bb.0: # %entry7; CHECK-NEXT: mul a0, a0, a18; CHECK-NEXT: mul a1, a2, a39; CHECK-NEXT: add a0, a0, a110; CHECK-NEXT: addiw a0, a0, 3211; CHECK-NEXT: ret12entry:13 %mul0 = mul i32 %m00, %m0114 %mul1 = mul i32 %m10, %m1115 %add0 = add i32 %mul0, 3216 %add1 = add i32 %add0, %mul117 ret i32 %add118}19 20define <8 x i32> @vmadd_non_constant(<8 x i32> %m00, <8 x i32> %m01, <8 x i32> %m10, <8 x i32> %m11, <8 x i32> %addend) {21; CHECK-LABEL: vmadd_non_constant:22; CHECK: # %bb.0: # %entry23; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma24; CHECK-NEXT: vmadd.vv v8, v10, v1625; CHECK-NEXT: vmacc.vv v8, v14, v1226; CHECK-NEXT: ret27entry:28 %mul0 = mul <8 x i32> %m00, %m0129 %mul1 = mul <8 x i32> %m10, %m1130 %add0 = add <8 x i32> %mul0, %addend31 %add1 = add <8 x i32> %add0, %mul132 ret <8 x i32> %add133}34 35define <vscale x 1 x i32> @vmadd_vscale_no_chain(<vscale x 1 x i32> %m00, <vscale x 1 x i32> %m01) {36; CHECK-LABEL: vmadd_vscale_no_chain:37; CHECK: # %bb.0: # %entry38; CHECK-NEXT: li a0, 3239; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma40; CHECK-NEXT: vmv.v.x v10, a041; CHECK-NEXT: vmadd.vv v8, v9, v1042; CHECK-NEXT: ret43entry:44 %mul = mul <vscale x 1 x i32> %m00, %m0145 %add = add <vscale x 1 x i32> %mul, splat (i32 32)46 ret <vscale x 1 x i32> %add47}48 49define <8 x i32> @vmadd_fixed_no_chain(<8 x i32> %m00, <8 x i32> %m01) {50; CHECK-LABEL: vmadd_fixed_no_chain:51; CHECK: # %bb.0: # %entry52; CHECK-NEXT: li a0, 3253; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma54; CHECK-NEXT: vmv.v.x v12, a055; CHECK-NEXT: vmadd.vv v8, v10, v1256; CHECK-NEXT: ret57entry:58 %mul = mul <8 x i32> %m00, %m0159 %add = add <8 x i32> %mul, splat (i32 32)60 ret <8 x i32> %add61}62 63define <vscale x 1 x i32> @vmadd_vscale(<vscale x 1 x i32> %m00, <vscale x 1 x i32> %m01, <vscale x 1 x i32> %m10, <vscale x 1 x i32> %m11) {64; CHECK-LABEL: vmadd_vscale:65; CHECK: # %bb.0: # %entry66; CHECK-NEXT: li a0, 3267; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma68; CHECK-NEXT: vmv.v.x v12, a069; CHECK-NEXT: vmadd.vv v8, v9, v1270; CHECK-NEXT: vmacc.vv v8, v11, v1071; CHECK-NEXT: ret72entry:73 %mul0 = mul <vscale x 1 x i32> %m00, %m0174 %mul1 = mul <vscale x 1 x i32> %m10, %m1175 %add0 = add <vscale x 1 x i32> %mul0, splat (i32 32)76 %add1 = add <vscale x 1 x i32> %add0, %mul177 ret <vscale x 1 x i32> %add178}79 80define <8 x i32> @vmadd_fixed(<8 x i32> %m00, <8 x i32> %m01, <8 x i32> %m10, <8 x i32> %m11) {81; CHECK-LABEL: vmadd_fixed:82; CHECK: # %bb.0: # %entry83; CHECK-NEXT: li a0, 3284; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma85; CHECK-NEXT: vmv.v.x v16, a086; CHECK-NEXT: vmadd.vv v8, v10, v1687; CHECK-NEXT: vmacc.vv v8, v14, v1288; CHECK-NEXT: ret89entry:90 %mul0 = mul <8 x i32> %m00, %m0191 %mul1 = mul <8 x i32> %m10, %m1192 %add0 = add <8 x i32> %mul0, splat (i32 32)93 %add1 = add <8 x i32> %add0, %mul194 ret <8 x i32> %add195}96 97define <vscale x 1 x i32> @vmadd_vscale_long(<vscale x 1 x i32> %m00, <vscale x 1 x i32> %m01, <vscale x 1 x i32> %m10, <vscale x 1 x i32> %m11,98; CHECK-LABEL: vmadd_vscale_long:99; CHECK: # %bb.0: # %entry100; CHECK-NEXT: li a0, 32101; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma102; CHECK-NEXT: vmv.v.x v16, a0103; CHECK-NEXT: vmadd.vv v8, v9, v16104; CHECK-NEXT: vmacc.vv v8, v11, v10105; CHECK-NEXT: vmacc.vv v8, v13, v12106; CHECK-NEXT: vmacc.vv v8, v15, v14107; CHECK-NEXT: ret108 <vscale x 1 x i32> %m20, <vscale x 1 x i32> %m21, <vscale x 1 x i32> %m30, <vscale x 1 x i32> %m31) {109entry:110 %mul0 = mul <vscale x 1 x i32> %m00, %m01111 %mul1 = mul <vscale x 1 x i32> %m10, %m11112 %mul2 = mul <vscale x 1 x i32> %m20, %m21113 %mul3 = mul <vscale x 1 x i32> %m30, %m31114 %add0 = add <vscale x 1 x i32> %mul0, splat (i32 32)115 %add1 = add <vscale x 1 x i32> %add0, %mul1116 %add2 = add <vscale x 1 x i32> %add1, %mul2117 %add3 = add <vscale x 1 x i32> %add2, %mul3118 ret <vscale x 1 x i32> %add3119}120 121define <8 x i32> @vmadd_fixed_long(<8 x i32> %m00, <8 x i32> %m01, <8 x i32> %m10, <8 x i32> %m11,122; CHECK-LABEL: vmadd_fixed_long:123; CHECK: # %bb.0: # %entry124; CHECK-NEXT: li a0, 32125; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma126; CHECK-NEXT: vmv.v.x v24, a0127; CHECK-NEXT: vmadd.vv v8, v10, v24128; CHECK-NEXT: vmacc.vv v8, v14, v12129; CHECK-NEXT: vmacc.vv v8, v18, v16130; CHECK-NEXT: vmacc.vv v8, v22, v20131; CHECK-NEXT: ret132 <8 x i32> %m20, <8 x i32> %m21, <8 x i32> %m30, <8 x i32> %m31) {133entry:134 %mul0 = mul <8 x i32> %m00, %m01135 %mul1 = mul <8 x i32> %m10, %m11136 %mul2 = mul <8 x i32> %m20, %m21137 %mul3 = mul <8 x i32> %m30, %m31138 %add0 = add <8 x i32> %mul0, splat (i32 32)139 %add1 = add <8 x i32> %add0, %mul1140 %add2 = add <8 x i32> %add1, %mul2141 %add3 = add <8 x i32> %add2, %mul3142 ret <8 x i32> %add3143}144