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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple riscv64 -mattr +v -filetype asm -o - %s | FileCheck %s3 4define <vscale x 8 x i8> @f() #0 {5; CHECK-LABEL: f:6; CHECK: # %bb.0: # %entry7; CHECK-NEXT: csrr a0, vlenb8; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma9; CHECK-NEXT: vid.v v810; CHECK-NEXT: vadd.vx v8, v8, a011; CHECK-NEXT: ret12entry:13 %0 = tail call i8 @llvm.vscale.i8()14 %1 = shl i8 %0, 315 %.splat.insert = insertelement <vscale x 8 x i8> poison, i8 %1, i64 016 %.splat = shufflevector <vscale x 8 x i8> %.splat.insert, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer17 %2 = tail call <vscale x 8 x i8> @llvm.stepvector.nxv8i8()18 %3 = add <vscale x 8 x i8> %2, %.splat19 ret <vscale x 8 x i8> %320}21 22attributes #0 = { vscale_range(2,1024) }23