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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; Test that we are able to generate the Xqcia instructions3; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \4; RUN: | FileCheck %s --check-prefixes=RV32I5; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcia -verify-machineinstrs < %s \6; RUN: | FileCheck %s --check-prefixes=RV32IXQCIA7 8define i32 @addsat(i32 %a, i32 %b) {9; RV32I-LABEL: addsat:10; RV32I: # %bb.0:11; RV32I-NEXT: mv a2, a012; RV32I-NEXT: add a0, a0, a113; RV32I-NEXT: slt a2, a0, a214; RV32I-NEXT: srli a1, a1, 3115; RV32I-NEXT: beq a1, a2, .LBB0_216; RV32I-NEXT: # %bb.1:17; RV32I-NEXT: srai a0, a0, 3118; RV32I-NEXT: lui a1, 52428819; RV32I-NEXT: xor a0, a0, a120; RV32I-NEXT: .LBB0_2:21; RV32I-NEXT: ret22;23; RV32IXQCIA-LABEL: addsat:24; RV32IXQCIA: # %bb.0:25; RV32IXQCIA-NEXT: qc.addsat a0, a0, a126; RV32IXQCIA-NEXT: ret27 %saddsat = tail call i32 @llvm.sadd.sat.i32(i32 %a,i32 %b)28 ret i32 %saddsat29}30 31define i32 @addusat(i32 %a, i32 %b) {32; RV32I-LABEL: addusat:33; RV32I: # %bb.0:34; RV32I-NEXT: add a1, a0, a135; RV32I-NEXT: sltu a0, a1, a036; RV32I-NEXT: neg a0, a037; RV32I-NEXT: or a0, a0, a138; RV32I-NEXT: ret39;40; RV32IXQCIA-LABEL: addusat:41; RV32IXQCIA: # %bb.0:42; RV32IXQCIA-NEXT: qc.addusat a0, a0, a143; RV32IXQCIA-NEXT: ret44 %uaddsat = tail call i32 @llvm.uadd.sat.i32(i32 %a,i32 %b)45 ret i32 %uaddsat46}47 48define i32 @subsat(i32 %a, i32 %b) {49; RV32I-LABEL: subsat:50; RV32I: # %bb.0:51; RV32I-NEXT: mv a2, a052; RV32I-NEXT: sgtz a3, a153; RV32I-NEXT: sub a0, a0, a154; RV32I-NEXT: slt a1, a0, a255; RV32I-NEXT: beq a3, a1, .LBB2_256; RV32I-NEXT: # %bb.1:57; RV32I-NEXT: srai a0, a0, 3158; RV32I-NEXT: lui a1, 52428859; RV32I-NEXT: xor a0, a0, a160; RV32I-NEXT: .LBB2_2:61; RV32I-NEXT: ret62;63; RV32IXQCIA-LABEL: subsat:64; RV32IXQCIA: # %bb.0:65; RV32IXQCIA-NEXT: qc.subsat a0, a0, a166; RV32IXQCIA-NEXT: ret67 %ssubsat = tail call i32 @llvm.ssub.sat.i32(i32 %a,i32 %b)68 ret i32 %ssubsat69}70 71define i32 @subusat(i32 %a, i32 %b) {72; RV32I-LABEL: subusat:73; RV32I: # %bb.0:74; RV32I-NEXT: sub a1, a0, a175; RV32I-NEXT: sltu a0, a0, a176; RV32I-NEXT: addi a0, a0, -177; RV32I-NEXT: and a0, a0, a178; RV32I-NEXT: ret79;80; RV32IXQCIA-LABEL: subusat:81; RV32IXQCIA: # %bb.0:82; RV32IXQCIA-NEXT: qc.subusat a0, a0, a183; RV32IXQCIA-NEXT: ret84 %usubsat = tail call i32 @llvm.usub.sat.i32(i32 %a,i32 %b)85 ret i32 %usubsat86}87 88define i32 @shlusat(i32 %a, i32 %b) {89; RV32I-LABEL: shlusat:90; RV32I: # %bb.0:91; RV32I-NEXT: sll a2, a0, a192; RV32I-NEXT: srl a1, a2, a193; RV32I-NEXT: xor a0, a0, a194; RV32I-NEXT: seqz a0, a095; RV32I-NEXT: addi a0, a0, -196; RV32I-NEXT: or a0, a0, a297; RV32I-NEXT: ret98;99; RV32IXQCIA-LABEL: shlusat:100; RV32IXQCIA: # %bb.0:101; RV32IXQCIA-NEXT: qc.shlusat a0, a0, a1102; RV32IXQCIA-NEXT: ret103 %ushlsat = tail call i32 @llvm.ushl.sat.i32(i32 %a,i32 %b)104 ret i32 %ushlsat105}106 107define i32 @shlsat(i32 %a, i32 %b) {108; RV32I-LABEL: shlsat:109; RV32I: # %bb.0:110; RV32I-NEXT: mv a2, a0111; RV32I-NEXT: sll a0, a0, a1112; RV32I-NEXT: sra a1, a0, a1113; RV32I-NEXT: beq a2, a1, .LBB5_2114; RV32I-NEXT: # %bb.1:115; RV32I-NEXT: srai a2, a2, 31116; RV32I-NEXT: lui a0, 524288117; RV32I-NEXT: addi a0, a0, -1118; RV32I-NEXT: xor a0, a2, a0119; RV32I-NEXT: .LBB5_2:120; RV32I-NEXT: ret121;122; RV32IXQCIA-LABEL: shlsat:123; RV32IXQCIA: # %bb.0:124; RV32IXQCIA-NEXT: qc.shlsat a0, a0, a1125; RV32IXQCIA-NEXT: ret126 %sshlsat = tail call i32 @llvm.sshl.sat.i32(i32 %a,i32 %b)127 ret i32 %sshlsat128}129