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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I4; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcibm -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefixes=CHECK,RV32XQCIBM6; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcibm,+zbb -verify-machineinstrs < %s \7; RUN: | FileCheck %s -check-prefixes=CHECK,RV32XQCIBMZBB8 9define i32 @sexti1_i32(i1 %a) nounwind {10; RV32I-LABEL: sexti1_i32:11; RV32I: # %bb.0:12; RV32I-NEXT: slli a0, a0, 3113; RV32I-NEXT: srai a0, a0, 3114; RV32I-NEXT: ret15;16; RV32XQCIBM-LABEL: sexti1_i32:17; RV32XQCIBM: # %bb.0:18; RV32XQCIBM-NEXT: qc.ext a0, a0, 1, 019; RV32XQCIBM-NEXT: ret20;21; RV32XQCIBMZBB-LABEL: sexti1_i32:22; RV32XQCIBMZBB: # %bb.0:23; RV32XQCIBMZBB-NEXT: qc.ext a0, a0, 1, 024; RV32XQCIBMZBB-NEXT: ret25 %sext = sext i1 %a to i3226 ret i32 %sext27}28 29define i32 @sexti1_i32_2(i32 %a) {30; RV32I-LABEL: sexti1_i32_2:31; RV32I: # %bb.0:32; RV32I-NEXT: slli a0, a0, 3133; RV32I-NEXT: srai a0, a0, 3134; RV32I-NEXT: ret35;36; RV32XQCIBM-LABEL: sexti1_i32_2:37; RV32XQCIBM: # %bb.0:38; RV32XQCIBM-NEXT: qc.ext a0, a0, 1, 039; RV32XQCIBM-NEXT: ret40;41; RV32XQCIBMZBB-LABEL: sexti1_i32_2:42; RV32XQCIBMZBB: # %bb.0:43; RV32XQCIBMZBB-NEXT: qc.ext a0, a0, 1, 044; RV32XQCIBMZBB-NEXT: ret45 %shl = shl i32 %a, 3146 %shr = ashr exact i32 %shl, 3147 ret i32 %shr48}49 50; Make sure we don't use not+qc.ext51define zeroext i8 @sexti1_i32_setcc(i32 signext %a) {52; RV32I-LABEL: sexti1_i32_setcc:53; RV32I: # %bb.0:54; RV32I-NEXT: srli a0, a0, 3155; RV32I-NEXT: addi a0, a0, -156; RV32I-NEXT: zext.b a0, a057; RV32I-NEXT: ret58;59; RV32XQCIBM-LABEL: sexti1_i32_setcc:60; RV32XQCIBM: # %bb.0:61; RV32XQCIBM-NEXT: srli a0, a0, 3162; RV32XQCIBM-NEXT: addi a0, a0, -163; RV32XQCIBM-NEXT: qc.extu a0, a0, 8, 064; RV32XQCIBM-NEXT: ret65;66; RV32XQCIBMZBB-LABEL: sexti1_i32_setcc:67; RV32XQCIBMZBB: # %bb.0:68; RV32XQCIBMZBB-NEXT: srli a0, a0, 3169; RV32XQCIBMZBB-NEXT: addi a0, a0, -170; RV32XQCIBMZBB-NEXT: qc.extu a0, a0, 8, 071; RV32XQCIBMZBB-NEXT: ret72 %icmp = icmp sgt i32 %a, -173 %sext = sext i1 %icmp to i874 ret i8 %sext75}76 77; Make sure we don't use seqz+qc.ext instead of snez+addi78define i32 @sexti1_i32_setcc_2(i32 %a, i32 %b) {79; CHECK-LABEL: sexti1_i32_setcc_2:80; CHECK: # %bb.0:81; CHECK-NEXT: xor a0, a0, a182; CHECK-NEXT: snez a0, a083; CHECK-NEXT: addi a0, a0, -184; CHECK-NEXT: ret85 %icmp = icmp eq i32 %a, %b86 %sext = sext i1 %icmp to i3287 ret i32 %sext88}89 90; Make sure we don't use qc.ext instead of neg.91define i32 @sexti1_i32_setcc_3(i32 %a, i32 %b) {92; CHECK-LABEL: sexti1_i32_setcc_3:93; CHECK: # %bb.0:94; CHECK-NEXT: slt a0, a0, a195; CHECK-NEXT: neg a0, a096; CHECK-NEXT: ret97 %icmp = icmp slt i32 %a, %b98 %sext = sext i1 %icmp to i3299 ret i32 %sext100}101 102define i32 @sexti8_i32(i8 %a) nounwind {103; RV32I-LABEL: sexti8_i32:104; RV32I: # %bb.0:105; RV32I-NEXT: slli a0, a0, 24106; RV32I-NEXT: srai a0, a0, 24107; RV32I-NEXT: ret108;109; RV32XQCIBM-LABEL: sexti8_i32:110; RV32XQCIBM: # %bb.0:111; RV32XQCIBM-NEXT: qc.ext a0, a0, 8, 0112; RV32XQCIBM-NEXT: ret113;114; RV32XQCIBMZBB-LABEL: sexti8_i32:115; RV32XQCIBMZBB: # %bb.0:116; RV32XQCIBMZBB-NEXT: sext.b a0, a0117; RV32XQCIBMZBB-NEXT: ret118 %sext = sext i8 %a to i32119 ret i32 %sext120}121 122define i32 @sexti8_i32_2(i32 %a) {123; RV32I-LABEL: sexti8_i32_2:124; RV32I: # %bb.0:125; RV32I-NEXT: slli a0, a0, 24126; RV32I-NEXT: srai a0, a0, 24127; RV32I-NEXT: ret128;129; RV32XQCIBM-LABEL: sexti8_i32_2:130; RV32XQCIBM: # %bb.0:131; RV32XQCIBM-NEXT: qc.ext a0, a0, 8, 0132; RV32XQCIBM-NEXT: ret133;134; RV32XQCIBMZBB-LABEL: sexti8_i32_2:135; RV32XQCIBMZBB: # %bb.0:136; RV32XQCIBMZBB-NEXT: sext.b a0, a0137; RV32XQCIBMZBB-NEXT: ret138 %shl = shl i32 %a, 24139 %shr = ashr exact i32 %shl, 24140 ret i32 %shr141}142 143define i32 @sexti16_i32(i16 %a) nounwind {144; RV32I-LABEL: sexti16_i32:145; RV32I: # %bb.0:146; RV32I-NEXT: slli a0, a0, 16147; RV32I-NEXT: srai a0, a0, 16148; RV32I-NEXT: ret149;150; RV32XQCIBM-LABEL: sexti16_i32:151; RV32XQCIBM: # %bb.0:152; RV32XQCIBM-NEXT: qc.ext a0, a0, 16, 0153; RV32XQCIBM-NEXT: ret154;155; RV32XQCIBMZBB-LABEL: sexti16_i32:156; RV32XQCIBMZBB: # %bb.0:157; RV32XQCIBMZBB-NEXT: sext.h a0, a0158; RV32XQCIBMZBB-NEXT: ret159 %sext = sext i16 %a to i32160 ret i32 %sext161}162 163define i32 @sexti16_i32_2(i32 %a) {164; RV32I-LABEL: sexti16_i32_2:165; RV32I: # %bb.0:166; RV32I-NEXT: slli a0, a0, 16167; RV32I-NEXT: srai a0, a0, 16168; RV32I-NEXT: ret169;170; RV32XQCIBM-LABEL: sexti16_i32_2:171; RV32XQCIBM: # %bb.0:172; RV32XQCIBM-NEXT: qc.ext a0, a0, 16, 0173; RV32XQCIBM-NEXT: ret174;175; RV32XQCIBMZBB-LABEL: sexti16_i32_2:176; RV32XQCIBMZBB: # %bb.0:177; RV32XQCIBMZBB-NEXT: sext.h a0, a0178; RV32XQCIBMZBB-NEXT: ret179 %shl = shl i32 %a, 16180 %shr = ashr exact i32 %shl, 16181 ret i32 %shr182}183 184define i64 @sexti1_i64(i64 %a) {185; RV32I-LABEL: sexti1_i64:186; RV32I: # %bb.0:187; RV32I-NEXT: slli a0, a0, 31188; RV32I-NEXT: srai a0, a0, 31189; RV32I-NEXT: mv a1, a0190; RV32I-NEXT: ret191;192; RV32XQCIBM-LABEL: sexti1_i64:193; RV32XQCIBM: # %bb.0:194; RV32XQCIBM-NEXT: qc.ext a0, a0, 1, 0195; RV32XQCIBM-NEXT: mv a1, a0196; RV32XQCIBM-NEXT: ret197;198; RV32XQCIBMZBB-LABEL: sexti1_i64:199; RV32XQCIBMZBB: # %bb.0:200; RV32XQCIBMZBB-NEXT: qc.ext a0, a0, 1, 0201; RV32XQCIBMZBB-NEXT: mv a1, a0202; RV32XQCIBMZBB-NEXT: ret203 %shl = shl i64 %a, 63204 %shr = ashr exact i64 %shl, 63205 ret i64 %shr206}207 208define i64 @sexti1_i64_2(i1 %a) {209; RV32I-LABEL: sexti1_i64_2:210; RV32I: # %bb.0:211; RV32I-NEXT: slli a0, a0, 31212; RV32I-NEXT: srai a0, a0, 31213; RV32I-NEXT: mv a1, a0214; RV32I-NEXT: ret215;216; RV32XQCIBM-LABEL: sexti1_i64_2:217; RV32XQCIBM: # %bb.0:218; RV32XQCIBM-NEXT: qc.ext a0, a0, 1, 0219; RV32XQCIBM-NEXT: mv a1, a0220; RV32XQCIBM-NEXT: ret221;222; RV32XQCIBMZBB-LABEL: sexti1_i64_2:223; RV32XQCIBMZBB: # %bb.0:224; RV32XQCIBMZBB-NEXT: qc.ext a0, a0, 1, 0225; RV32XQCIBMZBB-NEXT: mv a1, a0226; RV32XQCIBMZBB-NEXT: ret227 %1 = sext i1 %a to i64228 ret i64 %1229}230 231define i64 @sexti8_i64(i64 %a) {232; RV32I-LABEL: sexti8_i64:233; RV32I: # %bb.0:234; RV32I-NEXT: slli a1, a0, 24235; RV32I-NEXT: srai a0, a1, 24236; RV32I-NEXT: srai a1, a1, 31237; RV32I-NEXT: ret238;239; RV32XQCIBM-LABEL: sexti8_i64:240; RV32XQCIBM: # %bb.0:241; RV32XQCIBM-NEXT: qc.ext a0, a0, 8, 0242; RV32XQCIBM-NEXT: srai a1, a0, 31243; RV32XQCIBM-NEXT: ret244;245; RV32XQCIBMZBB-LABEL: sexti8_i64:246; RV32XQCIBMZBB: # %bb.0:247; RV32XQCIBMZBB-NEXT: sext.b a0, a0248; RV32XQCIBMZBB-NEXT: srai a1, a0, 31249; RV32XQCIBMZBB-NEXT: ret250 %shl = shl i64 %a, 56251 %shr = ashr exact i64 %shl, 56252 ret i64 %shr253}254 255define i64 @sexti8_i64_2(i8 %a) {256; RV32I-LABEL: sexti8_i64_2:257; RV32I: # %bb.0:258; RV32I-NEXT: slli a1, a0, 24259; RV32I-NEXT: srai a0, a1, 24260; RV32I-NEXT: srai a1, a1, 31261; RV32I-NEXT: ret262;263; RV32XQCIBM-LABEL: sexti8_i64_2:264; RV32XQCIBM: # %bb.0:265; RV32XQCIBM-NEXT: qc.ext a0, a0, 8, 0266; RV32XQCIBM-NEXT: srai a1, a0, 31267; RV32XQCIBM-NEXT: ret268;269; RV32XQCIBMZBB-LABEL: sexti8_i64_2:270; RV32XQCIBMZBB: # %bb.0:271; RV32XQCIBMZBB-NEXT: sext.b a0, a0272; RV32XQCIBMZBB-NEXT: srai a1, a0, 31273; RV32XQCIBMZBB-NEXT: ret274 %1 = sext i8 %a to i64275 ret i64 %1276}277 278define i64 @sexti16_i64(i64 %a) {279; RV32I-LABEL: sexti16_i64:280; RV32I: # %bb.0:281; RV32I-NEXT: slli a1, a0, 16282; RV32I-NEXT: srai a0, a1, 16283; RV32I-NEXT: srai a1, a1, 31284; RV32I-NEXT: ret285;286; RV32XQCIBM-LABEL: sexti16_i64:287; RV32XQCIBM: # %bb.0:288; RV32XQCIBM-NEXT: qc.ext a0, a0, 16, 0289; RV32XQCIBM-NEXT: srai a1, a0, 31290; RV32XQCIBM-NEXT: ret291;292; RV32XQCIBMZBB-LABEL: sexti16_i64:293; RV32XQCIBMZBB: # %bb.0:294; RV32XQCIBMZBB-NEXT: sext.h a0, a0295; RV32XQCIBMZBB-NEXT: srai a1, a0, 31296; RV32XQCIBMZBB-NEXT: ret297 %shl = shl i64 %a, 48298 %shr = ashr exact i64 %shl, 48299 ret i64 %shr300}301 302define i64 @sexti16_i64_2(i16 %a) {303; RV32I-LABEL: sexti16_i64_2:304; RV32I: # %bb.0:305; RV32I-NEXT: slli a1, a0, 16306; RV32I-NEXT: srai a0, a1, 16307; RV32I-NEXT: srai a1, a1, 31308; RV32I-NEXT: ret309;310; RV32XQCIBM-LABEL: sexti16_i64_2:311; RV32XQCIBM: # %bb.0:312; RV32XQCIBM-NEXT: qc.ext a0, a0, 16, 0313; RV32XQCIBM-NEXT: srai a1, a0, 31314; RV32XQCIBM-NEXT: ret315;316; RV32XQCIBMZBB-LABEL: sexti16_i64_2:317; RV32XQCIBMZBB: # %bb.0:318; RV32XQCIBMZBB-NEXT: sext.h a0, a0319; RV32XQCIBMZBB-NEXT: srai a1, a0, 31320; RV32XQCIBMZBB-NEXT: ret321 %1 = sext i16 %a to i64322 ret i64 %1323}324 325define i64 @sexti32_i64(i64 %a) {326; CHECK-LABEL: sexti32_i64:327; CHECK: # %bb.0:328; CHECK-NEXT: srai a1, a0, 31329; CHECK-NEXT: ret330 %shl = shl i64 %a, 32331 %shr = ashr exact i64 %shl, 32332 ret i64 %shr333}334 335define i64 @sexti32_i64_2(i32 %a) {336; CHECK-LABEL: sexti32_i64_2:337; CHECK: # %bb.0:338; CHECK-NEXT: srai a1, a0, 31339; CHECK-NEXT: ret340 %1 = sext i32 %a to i64341 ret i64 %1342}343 344define i32 @extu_from_and_i32(i32 %x) {345; RV32I-LABEL: extu_from_and_i32:346; RV32I: # %bb.0:347; RV32I-NEXT: slli a0, a0, 20348; RV32I-NEXT: srli a0, a0, 20349; RV32I-NEXT: ret350;351; RV32XQCIBM-LABEL: extu_from_and_i32:352; RV32XQCIBM: # %bb.0:353; RV32XQCIBM-NEXT: qc.extu a0, a0, 12, 0354; RV32XQCIBM-NEXT: ret355;356; RV32XQCIBMZBB-LABEL: extu_from_and_i32:357; RV32XQCIBMZBB: # %bb.0:358; RV32XQCIBMZBB-NEXT: qc.extu a0, a0, 12, 0359; RV32XQCIBMZBB-NEXT: ret360 %a = and i32 %x, 4095361 ret i32 %a362}363 364define i32 @no_extu_from_and_i32(i32 %x) {365; CHECK-LABEL: no_extu_from_and_i32:366; CHECK: # %bb.0:367; CHECK-NEXT: andi a0, a0, 31368; CHECK-NEXT: ret369 %a = and i32 %x, 31370 ret i32 %a371}372 373define i32 @extu_from_and_i32_simm12_lb(i32 %x) {374; RV32I-LABEL: extu_from_and_i32_simm12_lb:375; RV32I: # %bb.0:376; RV32I-NEXT: andi a0, a0, 63377; RV32I-NEXT: ret378;379; RV32XQCIBM-LABEL: extu_from_and_i32_simm12_lb:380; RV32XQCIBM: # %bb.0:381; RV32XQCIBM-NEXT: qc.extu a0, a0, 6, 0382; RV32XQCIBM-NEXT: ret383;384; RV32XQCIBMZBB-LABEL: extu_from_and_i32_simm12_lb:385; RV32XQCIBMZBB: # %bb.0:386; RV32XQCIBMZBB-NEXT: qc.extu a0, a0, 6, 0387; RV32XQCIBMZBB-NEXT: ret388 %a = and i32 %x, 63389 ret i32 %a390}391 392define i32 @extu_from_and_i32_simm12_ub(i32 %x) {393; RV32I-LABEL: extu_from_and_i32_simm12_ub:394; RV32I: # %bb.0:395; RV32I-NEXT: andi a0, a0, 2047396; RV32I-NEXT: ret397;398; RV32XQCIBM-LABEL: extu_from_and_i32_simm12_ub:399; RV32XQCIBM: # %bb.0:400; RV32XQCIBM-NEXT: qc.extu a0, a0, 11, 0401; RV32XQCIBM-NEXT: ret402;403; RV32XQCIBMZBB-LABEL: extu_from_and_i32_simm12_ub:404; RV32XQCIBMZBB: # %bb.0:405; RV32XQCIBMZBB-NEXT: qc.extu a0, a0, 11, 0406; RV32XQCIBMZBB-NEXT: ret407 %a = and i32 %x, 2047408 ret i32 %a409}410 411define i64 @extu_from_and_i64(i64 %x) {412; RV32I-LABEL: extu_from_and_i64:413; RV32I: # %bb.0:414; RV32I-NEXT: slli a0, a0, 20415; RV32I-NEXT: srli a0, a0, 20416; RV32I-NEXT: li a1, 0417; RV32I-NEXT: ret418;419; RV32XQCIBM-LABEL: extu_from_and_i64:420; RV32XQCIBM: # %bb.0:421; RV32XQCIBM-NEXT: qc.extu a0, a0, 12, 0422; RV32XQCIBM-NEXT: li a1, 0423; RV32XQCIBM-NEXT: ret424;425; RV32XQCIBMZBB-LABEL: extu_from_and_i64:426; RV32XQCIBMZBB: # %bb.0:427; RV32XQCIBMZBB-NEXT: qc.extu a0, a0, 12, 0428; RV32XQCIBMZBB-NEXT: li a1, 0429; RV32XQCIBMZBB-NEXT: ret430 %a = and i64 %x, 4095431 ret i64 %a432}433 434define i32 @extu_from_and_lshr_i32(i32 %x) {435; RV32I-LABEL: extu_from_and_lshr_i32:436; RV32I: # %bb.0:437; RV32I-NEXT: slli a0, a0, 6438; RV32I-NEXT: srli a0, a0, 29439; RV32I-NEXT: ret440;441; RV32XQCIBM-LABEL: extu_from_and_lshr_i32:442; RV32XQCIBM: # %bb.0:443; RV32XQCIBM-NEXT: qc.extu a0, a0, 3, 23444; RV32XQCIBM-NEXT: ret445;446; RV32XQCIBMZBB-LABEL: extu_from_and_lshr_i32:447; RV32XQCIBMZBB: # %bb.0:448; RV32XQCIBMZBB-NEXT: qc.extu a0, a0, 3, 23449; RV32XQCIBMZBB-NEXT: ret450 %shifted = lshr i32 %x, 23451 %masked = and i32 %shifted, 7452 ret i32 %masked453}454 455define i64 @extu_from_and_lshr_i64(i64 %x) {456; RV32I-LABEL: extu_from_and_lshr_i64:457; RV32I: # %bb.0:458; RV32I-NEXT: slli a0, a1, 6459; RV32I-NEXT: srli a0, a0, 20460; RV32I-NEXT: li a1, 0461; RV32I-NEXT: ret462;463; RV32XQCIBM-LABEL: extu_from_and_lshr_i64:464; RV32XQCIBM: # %bb.0:465; RV32XQCIBM-NEXT: qc.extu a0, a1, 12, 14466; RV32XQCIBM-NEXT: li a1, 0467; RV32XQCIBM-NEXT: ret468;469; RV32XQCIBMZBB-LABEL: extu_from_and_lshr_i64:470; RV32XQCIBMZBB: # %bb.0:471; RV32XQCIBMZBB-NEXT: qc.extu a0, a1, 12, 14472; RV32XQCIBMZBB-NEXT: li a1, 0473; RV32XQCIBMZBB-NEXT: ret474 %shifted = lshr i64 %x, 46475 %masked = and i64 %shifted, 4095476 ret i64 %masked477}478 479define i32 @extu_from_lshr_and_i32(i32 %x) {480; RV32I-LABEL: extu_from_lshr_and_i32:481; RV32I: # %bb.0:482; RV32I-NEXT: slli a0, a0, 8483; RV32I-NEXT: srli a0, a0, 20484; RV32I-NEXT: ret485;486; RV32XQCIBM-LABEL: extu_from_lshr_and_i32:487; RV32XQCIBM: # %bb.0:488; RV32XQCIBM-NEXT: qc.extu a0, a0, 12, 12489; RV32XQCIBM-NEXT: ret490;491; RV32XQCIBMZBB-LABEL: extu_from_lshr_and_i32:492; RV32XQCIBMZBB: # %bb.0:493; RV32XQCIBMZBB-NEXT: qc.extu a0, a0, 12, 12494; RV32XQCIBMZBB-NEXT: ret495 %masked = and i32 %x, 16773120496 %shifted = lshr i32 %masked, 12497 ret i32 %shifted498}499 500define i64 @extu_from_lshr_and_i64(i64 %x) {501; RV32I-LABEL: extu_from_lshr_and_i64:502; RV32I: # %bb.0:503; RV32I-NEXT: slli a0, a0, 8504; RV32I-NEXT: srli a0, a0, 20505; RV32I-NEXT: li a1, 0506; RV32I-NEXT: ret507;508; RV32XQCIBM-LABEL: extu_from_lshr_and_i64:509; RV32XQCIBM: # %bb.0:510; RV32XQCIBM-NEXT: qc.extu a0, a0, 12, 12511; RV32XQCIBM-NEXT: li a1, 0512; RV32XQCIBM-NEXT: ret513;514; RV32XQCIBMZBB-LABEL: extu_from_lshr_and_i64:515; RV32XQCIBMZBB: # %bb.0:516; RV32XQCIBMZBB-NEXT: qc.extu a0, a0, 12, 12517; RV32XQCIBMZBB-NEXT: li a1, 0518; RV32XQCIBMZBB-NEXT: ret519 %masked = and i64 %x, 16773120520 %shifted = lshr i64 %masked, 12521 ret i64 %shifted522}523 524define i32 @ext_from_ashr_shl_i32(i32 %x) {525; RV32I-LABEL: ext_from_ashr_shl_i32:526; RV32I: # %bb.0:527; RV32I-NEXT: slli a0, a0, 8528; RV32I-NEXT: srai a0, a0, 24529; RV32I-NEXT: ret530;531; RV32XQCIBM-LABEL: ext_from_ashr_shl_i32:532; RV32XQCIBM: # %bb.0:533; RV32XQCIBM-NEXT: qc.ext a0, a0, 8, 16534; RV32XQCIBM-NEXT: ret535;536; RV32XQCIBMZBB-LABEL: ext_from_ashr_shl_i32:537; RV32XQCIBMZBB: # %bb.0:538; RV32XQCIBMZBB-NEXT: qc.ext a0, a0, 8, 16539; RV32XQCIBMZBB-NEXT: ret540 %shl = shl i32 %x, 8541 %ashr = ashr i32 %shl, 24542 ret i32 %ashr543}544 545define i32 @ext_from_ashr_sexti8_i32(i8 %x) {546; RV32I-LABEL: ext_from_ashr_sexti8_i32:547; RV32I: # %bb.0:548; RV32I-NEXT: slli a0, a0, 24549; RV32I-NEXT: srai a0, a0, 29550; RV32I-NEXT: ret551;552; RV32XQCIBM-LABEL: ext_from_ashr_sexti8_i32:553; RV32XQCIBM: # %bb.0:554; RV32XQCIBM-NEXT: qc.ext a0, a0, 3, 5555; RV32XQCIBM-NEXT: ret556;557; RV32XQCIBMZBB-LABEL: ext_from_ashr_sexti8_i32:558; RV32XQCIBMZBB: # %bb.0:559; RV32XQCIBMZBB-NEXT: qc.ext a0, a0, 3, 5560; RV32XQCIBMZBB-NEXT: ret561 %sext = sext i8 %x to i32562 %ashr = ashr i32 %sext, 5563 ret i32 %ashr564}565 566define i32 @ext_from_ashr_sexti16_i32(i16 %x) {567; RV32I-LABEL: ext_from_ashr_sexti16_i32:568; RV32I: # %bb.0:569; RV32I-NEXT: slli a0, a0, 16570; RV32I-NEXT: srai a0, a0, 31571; RV32I-NEXT: ret572;573; RV32XQCIBM-LABEL: ext_from_ashr_sexti16_i32:574; RV32XQCIBM: # %bb.0:575; RV32XQCIBM-NEXT: qc.ext a0, a0, 1, 15576; RV32XQCIBM-NEXT: ret577;578; RV32XQCIBMZBB-LABEL: ext_from_ashr_sexti16_i32:579; RV32XQCIBMZBB: # %bb.0:580; RV32XQCIBMZBB-NEXT: qc.ext a0, a0, 1, 15581; RV32XQCIBMZBB-NEXT: ret582 %sext = sext i16 %x to i32583 %ashr = ashr i32 %sext, 24584 ret i32 %ashr585}586