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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=riscv32 --verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefixes=RV32I4; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcibm --verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefixes=RV32XQCIBM6 7define i32 @insb(i32 %in1, i32 %in2) {8; RV32I-LABEL: insb:9; RV32I: # %bb.0:10; RV32I-NEXT: slli a1, a1, 111; RV32I-NEXT: andi a2, a0, -212; RV32I-NEXT: xor a1, a1, a213; RV32I-NEXT: xor a0, a0, a114; RV32I-NEXT: ret15;16; RV32XQCIBM-LABEL: insb:17; RV32XQCIBM: # %bb.0:18; RV32XQCIBM-NEXT: qc.ext a1, a1, 31, 019; RV32XQCIBM-NEXT: qc.insb a0, a1, 31, 120; RV32XQCIBM-NEXT: ret21 %shl1 = shl i32 %in2, 122 %in1.masked = and i32 %in1, -223 %xor1 = xor i32 %shl1, %in1.masked24 %xor2 = xor i32 %in1, %xor125 ret i32 %xor226}27 28define i32 @insb_and_multiple(i32 %in1, i32 %in2) {29; RV32I-LABEL: insb_and_multiple:30; RV32I: # %bb.0:31; RV32I-NEXT: slli a1, a1, 132; RV32I-NEXT: andi a2, a0, -233; RV32I-NEXT: xor a1, a1, a234; RV32I-NEXT: xor a0, a0, a135; RV32I-NEXT: add a0, a0, a236; RV32I-NEXT: ret37;38; RV32XQCIBM-LABEL: insb_and_multiple:39; RV32XQCIBM: # %bb.0:40; RV32XQCIBM-NEXT: slli a1, a1, 141; RV32XQCIBM-NEXT: andi a2, a0, -242; RV32XQCIBM-NEXT: xor a1, a1, a243; RV32XQCIBM-NEXT: xor a0, a0, a144; RV32XQCIBM-NEXT: add a0, a0, a245; RV32XQCIBM-NEXT: ret46 %shl1 = shl i32 %in2, 147 %in1.masked = and i32 %in1, -248 %xor1 = xor i32 %shl1, %in1.masked49 %xor2 = xor i32 %in1, %xor150 %add1 = add i32 %xor2, %in1.masked51 ret i32 %add152}53 54define i32 @insb_xor_multiple(i32 %in1, i32 %in2) {55; RV32I-LABEL: insb_xor_multiple:56; RV32I: # %bb.0:57; RV32I-NEXT: slli a1, a1, 158; RV32I-NEXT: andi a2, a0, -259; RV32I-NEXT: xor a1, a1, a260; RV32I-NEXT: xor a0, a0, a161; RV32I-NEXT: add a0, a0, a162; RV32I-NEXT: ret63;64; RV32XQCIBM-LABEL: insb_xor_multiple:65; RV32XQCIBM: # %bb.0:66; RV32XQCIBM-NEXT: slli a1, a1, 167; RV32XQCIBM-NEXT: andi a2, a0, -268; RV32XQCIBM-NEXT: xor a1, a1, a269; RV32XQCIBM-NEXT: xor a0, a0, a170; RV32XQCIBM-NEXT: add a0, a0, a171; RV32XQCIBM-NEXT: ret72 %shl1 = shl i32 %in2, 173 %in1.masked = and i32 %in1, -274 %xor1 = xor i32 %shl1, %in1.masked75 %xor2 = xor i32 %in1, %xor176 %add1 = add i32 %xor2, %xor177 ret i32 %add178}79 80define i32 @insb_shl_multiple(i32 %in1, i32 %in2) {81; RV32I-LABEL: insb_shl_multiple:82; RV32I: # %bb.0:83; RV32I-NEXT: slli a1, a1, 184; RV32I-NEXT: andi a2, a0, -285; RV32I-NEXT: xor a2, a1, a286; RV32I-NEXT: xor a0, a0, a287; RV32I-NEXT: add a0, a0, a188; RV32I-NEXT: ret89;90; RV32XQCIBM-LABEL: insb_shl_multiple:91; RV32XQCIBM: # %bb.0:92; RV32XQCIBM-NEXT: slli a1, a1, 193; RV32XQCIBM-NEXT: srai a2, a1, 194; RV32XQCIBM-NEXT: qc.insb a0, a2, 31, 195; RV32XQCIBM-NEXT: add a0, a0, a196; RV32XQCIBM-NEXT: ret97 %shl1 = shl i32 %in2, 198 %in1.masked = and i32 %in1, -299 %and1 = xor i32 %shl1, %in1.masked100 %xor2 = xor i32 %in1, %and1101 %add1 = add i32 %xor2, %shl1102 ret i32 %add1103}104 105define i32 @insb_comm(i32 %in1, i32 %in2) {106; RV32I-LABEL: insb_comm:107; RV32I: # %bb.0:108; RV32I-NEXT: slli a1, a1, 1109; RV32I-NEXT: andi a2, a0, -2110; RV32I-NEXT: xor a1, a2, a1111; RV32I-NEXT: xor a0, a0, a1112; RV32I-NEXT: ret113;114; RV32XQCIBM-LABEL: insb_comm:115; RV32XQCIBM: # %bb.0:116; RV32XQCIBM-NEXT: qc.ext a1, a1, 31, 0117; RV32XQCIBM-NEXT: qc.insb a0, a1, 31, 1118; RV32XQCIBM-NEXT: ret119 %shl1 = shl i32 %in2, 1120 %in1.masked = and i32 %in1, -2121 %xor1 = xor i32 %in1.masked, %shl1122 %xor2 = xor i32 %in1, %xor1123 ret i32 %xor2124}125 126define i32 @insb_comm1(i32 %in1, i32 %in2) {127; RV32I-LABEL: insb_comm1:128; RV32I: # %bb.0:129; RV32I-NEXT: slli a1, a1, 1130; RV32I-NEXT: andi a2, a0, -2131; RV32I-NEXT: xor a1, a2, a1132; RV32I-NEXT: xor a0, a1, a0133; RV32I-NEXT: ret134;135; RV32XQCIBM-LABEL: insb_comm1:136; RV32XQCIBM: # %bb.0:137; RV32XQCIBM-NEXT: qc.ext a1, a1, 31, 0138; RV32XQCIBM-NEXT: qc.insb a0, a1, 31, 1139; RV32XQCIBM-NEXT: ret140 %shl1 = shl i32 %in2, 1141 %in1.masked = and i32 %in1, -2142 %xor1 = xor i32 %in1.masked, %shl1143 %xor2 = xor i32 %xor1, %in1144 ret i32 %xor2145}146 147define i64 @insb_i64(i64 %in1, i64 %in2) {148; RV32I-LABEL: insb_i64:149; RV32I: # %bb.0:150; RV32I-NEXT: srli a1, a2, 31151; RV32I-NEXT: slli a3, a3, 1152; RV32I-NEXT: slli a2, a2, 1153; RV32I-NEXT: or a1, a3, a1154; RV32I-NEXT: andi a3, a0, -2155; RV32I-NEXT: xor a2, a3, a2156; RV32I-NEXT: xor a0, a2, a0157; RV32I-NEXT: ret158;159; RV32XQCIBM-LABEL: insb_i64:160; RV32XQCIBM: # %bb.0:161; RV32XQCIBM-NEXT: srli a1, a2, 31162; RV32XQCIBM-NEXT: slli a3, a3, 1163; RV32XQCIBM-NEXT: qc.ext a2, a2, 31, 0164; RV32XQCIBM-NEXT: or a1, a1, a3165; RV32XQCIBM-NEXT: qc.insb a0, a2, 31, 1166; RV32XQCIBM-NEXT: ret167 %shl1 = shl i64 %in2, 1168 %in1.masked = and i64 %in1, -2169 %xor1 = xor i64 %in1.masked, %shl1170 %xor2 = xor i64 %xor1, %in1171 ret i64 %xor2172}173 174define i8 @tgt2_insb_neg(i8 %x, i8 %y) {175; RV32I-LABEL: tgt2_insb_neg:176; RV32I: # %bb.0:177; RV32I-NEXT: andi a2, a0, -2178; RV32I-NEXT: xor a0, a0, a1179; RV32I-NEXT: xor a0, a0, a2180; RV32I-NEXT: ret181;182; RV32XQCIBM-LABEL: tgt2_insb_neg:183; RV32XQCIBM: # %bb.0:184; RV32XQCIBM-NEXT: andi a2, a0, -2185; RV32XQCIBM-NEXT: xor a0, a0, a1186; RV32XQCIBM-NEXT: xor a0, a0, a2187; RV32XQCIBM-NEXT: ret188 %and = and i8 %x, -2189 %xor1 = xor i8 %and, %y190 %xor2 = xor i8 %x, %xor1191 ret i8 %xor2192}193 194