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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefixes=RV32I4; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcibm -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefixes=RV32IXQCIBM6; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcibm,+zbs -verify-machineinstrs < %s \7; RUN: | FileCheck %s -check-prefixes=RV32IXQCIBMZBS8 9 10define i32 @test_ori(i32 %a) nounwind {11; RV32I-LABEL: test_ori:12; RV32I: # %bb.0:13; RV32I-NEXT: ori a0, a0, 51114; RV32I-NEXT: ret15;16; RV32IXQCIBM-LABEL: test_ori:17; RV32IXQCIBM: # %bb.0:18; RV32IXQCIBM-NEXT: ori a0, a0, 51119; RV32IXQCIBM-NEXT: ret20;21; RV32IXQCIBMZBS-LABEL: test_ori:22; RV32IXQCIBMZBS: # %bb.0:23; RV32IXQCIBMZBS-NEXT: ori a0, a0, 51124; RV32IXQCIBMZBS-NEXT: ret25 %or = or i32 %a, 51126 ret i32 %or27}28 29define i32 @test_insbi_mask(i32 %a) nounwind {30; RV32I-LABEL: test_insbi_mask:31; RV32I: # %bb.0:32; RV32I-NEXT: lui a1, 1633; RV32I-NEXT: addi a1, a1, -134; RV32I-NEXT: or a0, a0, a135; RV32I-NEXT: ret36;37; RV32IXQCIBM-LABEL: test_insbi_mask:38; RV32IXQCIBM: # %bb.0:39; RV32IXQCIBM-NEXT: qc.insbi a0, -1, 16, 040; RV32IXQCIBM-NEXT: ret41;42; RV32IXQCIBMZBS-LABEL: test_insbi_mask:43; RV32IXQCIBMZBS: # %bb.0:44; RV32IXQCIBMZBS-NEXT: qc.insbi a0, -1, 16, 045; RV32IXQCIBMZBS-NEXT: ret46 %or = or i32 %a, 6553547 ret i32 %or48}49 50define i32 @test_insbi_mask_mv(i32 %a, i32 %b) nounwind {51; RV32I-LABEL: test_insbi_mask_mv:52; RV32I: # %bb.0:53; RV32I-NEXT: lui a0, 1654; RV32I-NEXT: addi a0, a0, -155; RV32I-NEXT: or a0, a1, a056; RV32I-NEXT: ret57;58; RV32IXQCIBM-LABEL: test_insbi_mask_mv:59; RV32IXQCIBM: # %bb.0:60; RV32IXQCIBM-NEXT: mv a0, a161; RV32IXQCIBM-NEXT: qc.insbi a0, -1, 16, 062; RV32IXQCIBM-NEXT: ret63;64; RV32IXQCIBMZBS-LABEL: test_insbi_mask_mv:65; RV32IXQCIBMZBS: # %bb.0:66; RV32IXQCIBMZBS-NEXT: mv a0, a167; RV32IXQCIBMZBS-NEXT: qc.insbi a0, -1, 16, 068; RV32IXQCIBMZBS-NEXT: ret69 %or = or i32 %b, 6553570 ret i32 %or71}72 73define i32 @test_insbi_shifted_mask(i32 %a) nounwind {74; RV32I-LABEL: test_insbi_shifted_mask:75; RV32I: # %bb.0:76; RV32I-NEXT: lui a1, 1577; RV32I-NEXT: or a0, a0, a178; RV32I-NEXT: ret79;80; RV32IXQCIBM-LABEL: test_insbi_shifted_mask:81; RV32IXQCIBM: # %bb.0:82; RV32IXQCIBM-NEXT: qc.insbi a0, -1, 4, 1283; RV32IXQCIBM-NEXT: ret84;85; RV32IXQCIBMZBS-LABEL: test_insbi_shifted_mask:86; RV32IXQCIBMZBS: # %bb.0:87; RV32IXQCIBMZBS-NEXT: qc.insbi a0, -1, 4, 1288; RV32IXQCIBMZBS-NEXT: ret89 %or = or i32 %a, 6144090 ret i32 %or91}92 93define i32 @test_insbi_shifted_mask_multiple_uses(i32 %a) nounwind {94; RV32I-LABEL: test_insbi_shifted_mask_multiple_uses:95; RV32I: # %bb.0:96; RV32I-NEXT: lui a1, 1597; RV32I-NEXT: or a1, a0, a198; RV32I-NEXT: addi a0, a0, 1099; RV32I-NEXT: xor a0, a1, a0100; RV32I-NEXT: ret101;102; RV32IXQCIBM-LABEL: test_insbi_shifted_mask_multiple_uses:103; RV32IXQCIBM: # %bb.0:104; RV32IXQCIBM-NEXT: lui a1, 15105; RV32IXQCIBM-NEXT: or a1, a1, a0106; RV32IXQCIBM-NEXT: addi a0, a0, 10107; RV32IXQCIBM-NEXT: xor a0, a0, a1108; RV32IXQCIBM-NEXT: ret109;110; RV32IXQCIBMZBS-LABEL: test_insbi_shifted_mask_multiple_uses:111; RV32IXQCIBMZBS: # %bb.0:112; RV32IXQCIBMZBS-NEXT: lui a1, 15113; RV32IXQCIBMZBS-NEXT: or a1, a1, a0114; RV32IXQCIBMZBS-NEXT: addi a0, a0, 10115; RV32IXQCIBMZBS-NEXT: xor a0, a0, a1116; RV32IXQCIBMZBS-NEXT: ret117 %or = or i32 %a, 61440118 %add = add i32 %a, 10119 %xor = xor i32 %or, %add120 ret i32 %xor121}122 123define i32 @test_single_bit_set(i32 %a) nounwind {124; RV32I-LABEL: test_single_bit_set:125; RV32I: # %bb.0:126; RV32I-NEXT: lui a1, 1127; RV32I-NEXT: or a0, a0, a1128; RV32I-NEXT: ret129;130; RV32IXQCIBM-LABEL: test_single_bit_set:131; RV32IXQCIBM: # %bb.0:132; RV32IXQCIBM-NEXT: qc.insbi a0, -1, 1, 12133; RV32IXQCIBM-NEXT: ret134;135; RV32IXQCIBMZBS-LABEL: test_single_bit_set:136; RV32IXQCIBMZBS: # %bb.0:137; RV32IXQCIBMZBS-NEXT: bseti a0, a0, 12138; RV32IXQCIBMZBS-NEXT: ret139 %or = or i32 %a, 4096140 ret i32 %or141}142 143 144; Tests for INSB(I) generation from OR and AND145 146define i32 @test1(i32 %a) {147; RV32I-LABEL: test1:148; RV32I: # %bb.0:149; RV32I-NEXT: andi a0, a0, -16150; RV32I-NEXT: addi a0, a0, 5151; RV32I-NEXT: ret152;153; RV32IXQCIBM-LABEL: test1:154; RV32IXQCIBM: # %bb.0:155; RV32IXQCIBM-NEXT: qc.insbi a0, 5, 4, 0156; RV32IXQCIBM-NEXT: ret157;158; RV32IXQCIBMZBS-LABEL: test1:159; RV32IXQCIBMZBS: # %bb.0:160; RV32IXQCIBMZBS-NEXT: qc.insbi a0, 5, 4, 0161; RV32IXQCIBMZBS-NEXT: ret162 %1 = and i32 %a, -16 ; 0xfffffff0163 %2 = or i32 %1, 5 ; 0x00000005164 ret i32 %2165}166 167define i32 @test2(i32 %a) {168; RV32I-LABEL: test2:169; RV32I: # %bb.0:170; RV32I-NEXT: lui a1, 1033216171; RV32I-NEXT: addi a1, a1, -1172; RV32I-NEXT: and a0, a0, a1173; RV32I-NEXT: lui a1, 10240174; RV32I-NEXT: or a0, a0, a1175; RV32I-NEXT: ret176;177; RV32IXQCIBM-LABEL: test2:178; RV32IXQCIBM: # %bb.0:179; RV32IXQCIBM-NEXT: qc.insbi a0, 10, 4, 22180; RV32IXQCIBM-NEXT: ret181;182; RV32IXQCIBMZBS-LABEL: test2:183; RV32IXQCIBMZBS: # %bb.0:184; RV32IXQCIBMZBS-NEXT: qc.insbi a0, 10, 4, 22185; RV32IXQCIBMZBS-NEXT: ret186 %1 = and i32 %a, -62914561 ; 0xfc3fffff187 %2 = or i32 %1, 41943040 ; 0x02800000188 ret i32 %2189}190 191define i64 @test3(i64 %a) {192; RV32I-LABEL: test3:193; RV32I: # %bb.0:194; RV32I-NEXT: andi a0, a0, -8195; RV32I-NEXT: addi a0, a0, 5196; RV32I-NEXT: ret197;198; RV32IXQCIBM-LABEL: test3:199; RV32IXQCIBM: # %bb.0:200; RV32IXQCIBM-NEXT: qc.insbi a0, 5, 3, 0201; RV32IXQCIBM-NEXT: ret202;203; RV32IXQCIBMZBS-LABEL: test3:204; RV32IXQCIBMZBS: # %bb.0:205; RV32IXQCIBMZBS-NEXT: qc.insbi a0, 5, 3, 0206; RV32IXQCIBMZBS-NEXT: ret207 %1 = and i64 %a, -8 ; 0xfffffffffffffff8208 %2 = or i64 %1, 5 ; 0x0000000000000005209 ret i64 %2210}211 212define i64 @test4(i64 %a) {213; RV32I-LABEL: test4:214; RV32I: # %bb.0:215; RV32I-NEXT: andi a0, a0, -255216; RV32I-NEXT: addi a0, a0, 18217; RV32I-NEXT: ret218;219; RV32IXQCIBM-LABEL: test4:220; RV32IXQCIBM: # %bb.0:221; RV32IXQCIBM-NEXT: qc.insbi a0, 9, 7, 1222; RV32IXQCIBM-NEXT: ret223;224; RV32IXQCIBMZBS-LABEL: test4:225; RV32IXQCIBMZBS: # %bb.0:226; RV32IXQCIBMZBS-NEXT: qc.insbi a0, 9, 7, 1227; RV32IXQCIBMZBS-NEXT: ret228 %1 = and i64 %a, -255 ; 0xffffffffffffff01229 %2 = or i64 %1, 18 ; 0x0000000000000012230 ret i64 %2231}232 233define i32 @test5(i32 %a) {234; RV32I-LABEL: test5:235; RV32I: # %bb.0:236; RV32I-NEXT: andi a0, a0, -16237; RV32I-NEXT: addi a0, a0, 6238; RV32I-NEXT: ret239;240; RV32IXQCIBM-LABEL: test5:241; RV32IXQCIBM: # %bb.0:242; RV32IXQCIBM-NEXT: qc.insbi a0, 6, 4, 0243; RV32IXQCIBM-NEXT: ret244;245; RV32IXQCIBMZBS-LABEL: test5:246; RV32IXQCIBMZBS: # %bb.0:247; RV32IXQCIBMZBS-NEXT: qc.insbi a0, 6, 4, 0248; RV32IXQCIBMZBS-NEXT: ret249 %1 = and i32 %a, 4294967280 ; 0xfffffff0250 %2 = or i32 %1, 6 ; 0x00000006251 ret i32 %2252}253 254define i32 @test6(i32 %a) {255; RV32I-LABEL: test6:256; RV32I: # %bb.0:257; RV32I-NEXT: lui a1, 1048320258; RV32I-NEXT: and a0, a0, a1259; RV32I-NEXT: lui a1, 182260; RV32I-NEXT: addi a1, a1, -1326261; RV32I-NEXT: or a0, a0, a1262; RV32I-NEXT: ret263;264; RV32IXQCIBM-LABEL: test6:265; RV32IXQCIBM: # %bb.0:266; RV32IXQCIBM-NEXT: lui a1, 182267; RV32IXQCIBM-NEXT: addi a1, a1, -1326268; RV32IXQCIBM-NEXT: qc.insb a0, a1, 20, 0269; RV32IXQCIBM-NEXT: ret270;271; RV32IXQCIBMZBS-LABEL: test6:272; RV32IXQCIBMZBS: # %bb.0:273; RV32IXQCIBMZBS-NEXT: lui a1, 182274; RV32IXQCIBMZBS-NEXT: addi a1, a1, -1326275; RV32IXQCIBMZBS-NEXT: qc.insb a0, a1, 20, 0276; RV32IXQCIBMZBS-NEXT: ret277 %1 = and i32 %a, 4293918720 ; 0xfff00000278 %2 = or i32 %1, 744146 ; 0x000b5ad2279 ret i32 %2280}281 282define i32 @test7(i32 %a) {283; RV32I-LABEL: test7:284; RV32I: # %bb.0:285; RV32I-NEXT: lui a1, 1048320286; RV32I-NEXT: addi a1, a1, 1287; RV32I-NEXT: and a0, a0, a1288; RV32I-NEXT: lui a1, 182289; RV32I-NEXT: addi a1, a1, -1326290; RV32I-NEXT: or a0, a0, a1291; RV32I-NEXT: ret292;293; RV32IXQCIBM-LABEL: test7:294; RV32IXQCIBM: # %bb.0:295; RV32IXQCIBM-NEXT: lui a1, 91296; RV32IXQCIBM-NEXT: addi a1, a1, -663297; RV32IXQCIBM-NEXT: qc.insb a0, a1, 19, 1298; RV32IXQCIBM-NEXT: ret299;300; RV32IXQCIBMZBS-LABEL: test7:301; RV32IXQCIBMZBS: # %bb.0:302; RV32IXQCIBMZBS-NEXT: lui a1, 91303; RV32IXQCIBMZBS-NEXT: addi a1, a1, -663304; RV32IXQCIBMZBS-NEXT: qc.insb a0, a1, 19, 1305; RV32IXQCIBMZBS-NEXT: ret306 %1 = and i32 %a, 4293918721 ; 0xfff00001307 %2 = or i32 %1, 744146 ; 0x000b5ad2308 ret i32 %2309}310 311define i64 @test8(i64 %a) {312; RV32I-LABEL: test8:313; RV32I: # %bb.0:314; RV32I-NEXT: lui a2, 1044480315; RV32I-NEXT: zext.b a0, a0316; RV32I-NEXT: and a1, a1, a2317; RV32I-NEXT: lui a2, 496944318; RV32I-NEXT: or a0, a0, a2319; RV32I-NEXT: lui a2, 9320; RV32I-NEXT: addi a2, a2, -170321; RV32I-NEXT: or a1, a1, a2322; RV32I-NEXT: ret323;324; RV32IXQCIBM-LABEL: test8:325; RV32IXQCIBM: # %bb.0:326; RV32IXQCIBM-NEXT: lui a2, 1941327; RV32IXQCIBM-NEXT: addi a2, a2, 768328; RV32IXQCIBM-NEXT: qc.insb a0, a2, 24, 8329; RV32IXQCIBM-NEXT: lui a2, 9330; RV32IXQCIBM-NEXT: addi a2, a2, -170331; RV32IXQCIBM-NEXT: qc.insb a1, a2, 24, 0332; RV32IXQCIBM-NEXT: ret333;334; RV32IXQCIBMZBS-LABEL: test8:335; RV32IXQCIBMZBS: # %bb.0:336; RV32IXQCIBMZBS-NEXT: lui a2, 1941337; RV32IXQCIBMZBS-NEXT: addi a2, a2, 768338; RV32IXQCIBMZBS-NEXT: qc.insb a0, a2, 24, 8339; RV32IXQCIBMZBS-NEXT: lui a2, 9340; RV32IXQCIBMZBS-NEXT: addi a2, a2, -170341; RV32IXQCIBMZBS-NEXT: qc.insb a1, a2, 24, 0342; RV32IXQCIBMZBS-NEXT: ret343 %1 = and i64 %a, -72057594037927681 ; 0xff000000000000ff344 %2 = or i64 %1, 157601565442048 ; 0x00008f5679530000345 ret i64 %2346}347