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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; Test that we are able to generate the Xqcilia instructions3; RUN: llc < %s -mtriple=riscv32 | FileCheck %s -check-prefix=RV32I4; RUN: llc < %s -mtriple=riscv32 -mattr=+experimental-xqcilia | FileCheck %s -check-prefix=RV32XQCILIA5 6define i32 @add(i32 %a, i32 %b) {7; RV32I-LABEL: add:8; RV32I: # %bb.0:9; RV32I-NEXT: lui a2, 6553610; RV32I-NEXT: add a0, a0, a211; RV32I-NEXT: lui a2, 57312; RV32I-NEXT: addi a2, a2, -133013; RV32I-NEXT: add a1, a1, a214; RV32I-NEXT: and a0, a1, a015; RV32I-NEXT: addi a0, a0, 1316; RV32I-NEXT: ret17;18; RV32XQCILIA-LABEL: add:19; RV32XQCILIA: # %bb.0:20; RV32XQCILIA-NEXT: qc.e.addi a1, a1, 234567821; RV32XQCILIA-NEXT: qc.e.addai a0, 26843545622; RV32XQCILIA-NEXT: and a0, a0, a123; RV32XQCILIA-NEXT: addi a0, a0, 1324; RV32XQCILIA-NEXT: ret25 %addai = add i32 %a, 26843545626 %add = add i32 %b, 234567827 %and = and i32 %add, %addai28 %res = add i32 %and, 1329 ret i32 %res30}31 32define i32 @and(i32 %a, i32 %b) {33; RV32I-LABEL: and:34; RV32I: # %bb.0:35; RV32I-NEXT: lui a2, 6553636; RV32I-NEXT: and a0, a0, a237; RV32I-NEXT: lui a2, 57338; RV32I-NEXT: addi a2, a2, -133039; RV32I-NEXT: and a1, a1, a240; RV32I-NEXT: srl a0, a1, a041; RV32I-NEXT: andi a0, a0, 1042; RV32I-NEXT: ret43;44; RV32XQCILIA-LABEL: and:45; RV32XQCILIA: # %bb.0:46; RV32XQCILIA-NEXT: qc.e.andi a1, a1, 234567847; RV32XQCILIA-NEXT: qc.e.andai a0, 26843545648; RV32XQCILIA-NEXT: srl a0, a1, a049; RV32XQCILIA-NEXT: andi a0, a0, 1050; RV32XQCILIA-NEXT: ret51 %andai = and i32 %a, 26843545652 %and = and i32 %b, 234567853 %srl = lshr i32 %and, %andai54 %res = and i32 %srl, 1055 ret i32 %res56}57 58define i32 @or(i32 %a, i32 %b) {59; RV32I-LABEL: or:60; RV32I: # %bb.0:61; RV32I-NEXT: lui a2, 6553662; RV32I-NEXT: or a0, a0, a263; RV32I-NEXT: lui a2, 57364; RV32I-NEXT: addi a2, a2, -133065; RV32I-NEXT: or a1, a1, a266; RV32I-NEXT: add a0, a1, a067; RV32I-NEXT: ori a0, a0, 1368; RV32I-NEXT: ret69;70; RV32XQCILIA-LABEL: or:71; RV32XQCILIA: # %bb.0:72; RV32XQCILIA-NEXT: qc.e.ori a1, a1, 234567873; RV32XQCILIA-NEXT: qc.e.orai a0, 26843545674; RV32XQCILIA-NEXT: add a0, a0, a175; RV32XQCILIA-NEXT: ori a0, a0, 1376; RV32XQCILIA-NEXT: ret77 %orai = or i32 %a, 26843545678 %or = or i32 %b, 234567879 %add = add i32 %or, %orai80 %res = or i32 %add, 1381 ret i32 %res82}83 84define i32 @xor(i32 %a, i32 %b) {85; RV32I-LABEL: xor:86; RV32I: # %bb.0:87; RV32I-NEXT: lui a2, 6553688; RV32I-NEXT: xor a0, a0, a289; RV32I-NEXT: lui a2, 57390; RV32I-NEXT: addi a2, a2, -133091; RV32I-NEXT: xor a1, a1, a292; RV32I-NEXT: add a0, a1, a093; RV32I-NEXT: xori a0, a0, 1394; RV32I-NEXT: ret95;96; RV32XQCILIA-LABEL: xor:97; RV32XQCILIA: # %bb.0:98; RV32XQCILIA-NEXT: qc.e.xori a1, a1, 234567899; RV32XQCILIA-NEXT: qc.e.xorai a0, 268435456100; RV32XQCILIA-NEXT: add a0, a0, a1101; RV32XQCILIA-NEXT: xori a0, a0, 13102; RV32XQCILIA-NEXT: ret103 %xorai = xor i32 %a, 268435456104 %xor = xor i32 %b, 2345678105 %add = add i32 %xor, %xorai106 %res = xor i32 %add, 13107 ret i32 %res108}109