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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefixes=RV32I4; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilo -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefixes=RV32IXQCILO6 7define i32 @lb_ri(i8* %a) {8; RV32I-LABEL: lb_ri:9; RV32I: # %bb.0:10; RV32I-NEXT: lui a1, 211; RV32I-NEXT: add a0, a0, a112; RV32I-NEXT: lb a0, 1808(a0)13; RV32I-NEXT: ret14;15; RV32IXQCILO-LABEL: lb_ri:16; RV32IXQCILO: # %bb.0:17; RV32IXQCILO-NEXT: qc.e.lb a0, 10000(a0)18; RV32IXQCILO-NEXT: ret19 %1 = getelementptr i8, i8* %a, i32 1000020 %2 = load i8, i8* %121 %3 = sext i8 %2 to i3222 ret i32 %323}24 25define i32 @lbu_ri(i8* %a) {26; RV32I-LABEL: lbu_ri:27; RV32I: # %bb.0:28; RV32I-NEXT: lui a1, 104857429; RV32I-NEXT: add a0, a0, a130; RV32I-NEXT: lbu a0, 192(a0)31; RV32I-NEXT: ret32;33; RV32IXQCILO-LABEL: lbu_ri:34; RV32IXQCILO: # %bb.0:35; RV32IXQCILO-NEXT: qc.e.lbu a0, -8000(a0)36; RV32IXQCILO-NEXT: ret37 %1 = getelementptr i8, i8* %a, i32 -800038 %2 = load i8, i8* %139 %3 = zext i8 %2 to i3240 ret i32 %341}42 43define i32 @lh_ri(i16* %a) {44; RV32I-LABEL: lh_ri:45; RV32I: # %bb.0:46; RV32I-NEXT: lui a1, 1147; RV32I-NEXT: add a0, a0, a148; RV32I-NEXT: lhu a0, -612(a0)49; RV32I-NEXT: ret50;51; RV32IXQCILO-LABEL: lh_ri:52; RV32IXQCILO: # %bb.0:53; RV32IXQCILO-NEXT: qc.e.lhu a0, 44444(a0)54; RV32IXQCILO-NEXT: ret55 %1 = getelementptr i16, i16* %a, i32 2222256 %2 = load i16, i16* %157 %3 = zext i16 %2 to i3258 ret i32 %359}60 61define i32 @lhu_ri(i16* %a) {62; RV32I-LABEL: lhu_ri:63; RV32I: # %bb.0:64; RV32I-NEXT: lui a1, 104857065; RV32I-NEXT: add a0, a0, a166; RV32I-NEXT: lhu a0, 120(a0)67; RV32I-NEXT: ret68;69; RV32IXQCILO-LABEL: lhu_ri:70; RV32IXQCILO: # %bb.0:71; RV32IXQCILO-NEXT: qc.e.lhu a0, -24456(a0)72; RV32IXQCILO-NEXT: ret73 %1 = getelementptr i16, i16* %a, i32 -1222874 %2 = load i16, i16* %175 %3 = zext i16 %2 to i3276 ret i32 %377}78 79define i32 @lw_ri(i32* %a) {80; RV32I-LABEL: lw_ri:81; RV32I: # %bb.0:82; RV32I-NEXT: addi a0, a0, 204783; RV32I-NEXT: lw a0, 1953(a0)84; RV32I-NEXT: ret85;86; RV32IXQCILO-LABEL: lw_ri:87; RV32IXQCILO: # %bb.0:88; RV32IXQCILO-NEXT: qc.e.lw a0, 4000(a0)89; RV32IXQCILO-NEXT: ret90 %1 = getelementptr i32, i32* %a, i32 100091 %2 = load i32, i32* %192 ret i32 %293}94 95define void @sb_ri(i8* %a, i8 %b) {96; RV32I-LABEL: sb_ri:97; RV32I: # %bb.0:98; RV32I-NEXT: lui a2, 299; RV32I-NEXT: add a0, a0, a2100; RV32I-NEXT: sb a1, 1808(a0)101; RV32I-NEXT: ret102;103; RV32IXQCILO-LABEL: sb_ri:104; RV32IXQCILO: # %bb.0:105; RV32IXQCILO-NEXT: qc.e.sb a1, 10000(a0)106; RV32IXQCILO-NEXT: ret107 %1 = getelementptr i8, i8* %a, i32 10000108 store i8 %b, i8* %1109 ret void110}111 112define void @sh_ri(i16* %a, i16 %b) {113; RV32I-LABEL: sh_ri:114; RV32I: # %bb.0:115; RV32I-NEXT: lui a2, 11116; RV32I-NEXT: add a0, a0, a2117; RV32I-NEXT: sh a1, -612(a0)118; RV32I-NEXT: ret119;120; RV32IXQCILO-LABEL: sh_ri:121; RV32IXQCILO: # %bb.0:122; RV32IXQCILO-NEXT: qc.e.sh a1, 44444(a0)123; RV32IXQCILO-NEXT: ret124 %1 = getelementptr i16, i16* %a, i32 22222125 store i16 %b, i16* %1126 ret void127}128 129define void @sw_ri(i32* %a, i32 %b) {130; RV32I-LABEL: sw_ri:131; RV32I: # %bb.0:132; RV32I-NEXT: addi a0, a0, 2047133; RV32I-NEXT: sw a1, 1953(a0)134; RV32I-NEXT: ret135;136; RV32IXQCILO-LABEL: sw_ri:137; RV32IXQCILO: # %bb.0:138; RV32IXQCILO-NEXT: qc.e.sw a1, 4000(a0)139; RV32IXQCILO-NEXT: ret140 %1 = getelementptr i32, i32* %a, i32 1000141 store i32 %b, i32* %1142 ret void143}144