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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d,+xtheadfmemidx \3; RUN: -verify-machineinstrs | FileCheck %s -check-prefixes=CHECK,RV32XTHEADFMEMIDX4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d,+xtheadfmemidx \5; RUN: -verify-machineinstrs | FileCheck %s -check-prefixes=CHECK,RV64XTHEADFMEMIDX6 7define float @flrw(ptr %a, iXLen %b) {8; CHECK-LABEL: flrw:9; CHECK: # %bb.0:10; CHECK-NEXT: th.flrw fa5, a0, a1, 211; CHECK-NEXT: fadd.s fa0, fa5, fa512; CHECK-NEXT: ret13 %1 = getelementptr float, ptr %a, iXLen %b14 %2 = load float, ptr %1, align 415 %3 = fadd float %2, %216 ret float %317}18 19define float @flurw(ptr %a, i32 %b) {20; RV32XTHEADFMEMIDX-LABEL: flurw:21; RV32XTHEADFMEMIDX: # %bb.0:22; RV32XTHEADFMEMIDX-NEXT: th.flrw fa5, a0, a1, 223; RV32XTHEADFMEMIDX-NEXT: fadd.s fa0, fa5, fa524; RV32XTHEADFMEMIDX-NEXT: ret25;26; RV64XTHEADFMEMIDX-LABEL: flurw:27; RV64XTHEADFMEMIDX: # %bb.0:28; RV64XTHEADFMEMIDX-NEXT: th.flurw fa5, a0, a1, 229; RV64XTHEADFMEMIDX-NEXT: fadd.s fa0, fa5, fa530; RV64XTHEADFMEMIDX-NEXT: ret31 %1 = zext i32 %b to i6432 %2 = getelementptr float, ptr %a, i64 %133 %3 = load float, ptr %2, align 434 %4 = fadd float %3, %335 ret float %436}37 38define void @fsrw(ptr %a, iXLen %b, float %c) {39; CHECK-LABEL: fsrw:40; CHECK: # %bb.0:41; CHECK-NEXT: fadd.s fa5, fa0, fa042; CHECK-NEXT: th.fsrw fa5, a0, a1, 243; CHECK-NEXT: ret44 %1 = fadd float %c, %c45 %2 = getelementptr float, ptr %a, iXLen %b46 store float %1, ptr %2, align 447 ret void48}49 50define void @fsurw(ptr %a, i32 %b, float %c) {51; RV32XTHEADFMEMIDX-LABEL: fsurw:52; RV32XTHEADFMEMIDX: # %bb.0:53; RV32XTHEADFMEMIDX-NEXT: fadd.s fa5, fa0, fa054; RV32XTHEADFMEMIDX-NEXT: th.fsrw fa5, a0, a1, 255; RV32XTHEADFMEMIDX-NEXT: ret56;57; RV64XTHEADFMEMIDX-LABEL: fsurw:58; RV64XTHEADFMEMIDX: # %bb.0:59; RV64XTHEADFMEMIDX-NEXT: fadd.s fa5, fa0, fa060; RV64XTHEADFMEMIDX-NEXT: th.fsurw fa5, a0, a1, 261; RV64XTHEADFMEMIDX-NEXT: ret62 %1 = zext i32 %b to i6463 %2 = fadd float %c, %c64 %3 = getelementptr float, ptr %a, i64 %165 store float %2, ptr %3, align 466 ret void67}68 69define double @flrd(ptr %a, iXLen %b) {70; CHECK-LABEL: flrd:71; CHECK: # %bb.0:72; CHECK-NEXT: th.flrd fa5, a0, a1, 373; CHECK-NEXT: fadd.d fa0, fa5, fa574; CHECK-NEXT: ret75 %1 = getelementptr double, ptr %a, iXLen %b76 %2 = load double, ptr %1, align 877 %3 = fadd double %2, %278 ret double %379}80 81define double @flurd(ptr %a, i32 %b) {82; RV32XTHEADFMEMIDX-LABEL: flurd:83; RV32XTHEADFMEMIDX: # %bb.0:84; RV32XTHEADFMEMIDX-NEXT: th.flrd fa5, a0, a1, 385; RV32XTHEADFMEMIDX-NEXT: fadd.d fa0, fa5, fa586; RV32XTHEADFMEMIDX-NEXT: ret87;88; RV64XTHEADFMEMIDX-LABEL: flurd:89; RV64XTHEADFMEMIDX: # %bb.0:90; RV64XTHEADFMEMIDX-NEXT: th.flurd fa5, a0, a1, 391; RV64XTHEADFMEMIDX-NEXT: fadd.d fa0, fa5, fa592; RV64XTHEADFMEMIDX-NEXT: ret93 %1 = zext i32 %b to i6494 %2 = getelementptr double, ptr %a, i64 %195 %3 = load double, ptr %2, align 896 %4 = fadd double %3, %397 ret double %498}99 100define void @fsrd(ptr %a, iXLen %b, double %c) {101; CHECK-LABEL: fsrd:102; CHECK: # %bb.0:103; CHECK-NEXT: fadd.d fa5, fa0, fa0104; CHECK-NEXT: th.fsrd fa5, a0, a1, 3105; CHECK-NEXT: ret106 %1 = fadd double %c, %c107 %2 = getelementptr double, ptr %a, iXLen %b108 store double %1, ptr %2, align 8109 ret void110}111 112define void @fsurd(ptr %a, i32 %b, double %c) {113; RV32XTHEADFMEMIDX-LABEL: fsurd:114; RV32XTHEADFMEMIDX: # %bb.0:115; RV32XTHEADFMEMIDX-NEXT: fadd.d fa5, fa0, fa0116; RV32XTHEADFMEMIDX-NEXT: th.fsrd fa5, a0, a1, 3117; RV32XTHEADFMEMIDX-NEXT: ret118;119; RV64XTHEADFMEMIDX-LABEL: fsurd:120; RV64XTHEADFMEMIDX: # %bb.0:121; RV64XTHEADFMEMIDX-NEXT: fadd.d fa5, fa0, fa0122; RV64XTHEADFMEMIDX-NEXT: th.fsurd fa5, a0, a1, 3123; RV64XTHEADFMEMIDX-NEXT: ret124 %1 = zext i32 %b to i64125 %2 = fadd double %c, %c126 %3 = getelementptr double, ptr %a, i64 %1127 store double %2, ptr %3, align 8128 ret void129}130