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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+xtheadmac -mattr=+m -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV32XTHEADMAC4; RUN: llc -mtriple=riscv64 -mattr=+xtheadmac -mattr=+m -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefix=RV64XTHEADMAC6 7define i32 @mula_i32(i32 %a, i32 %b, i32 %c) {8; RV32XTHEADMAC-LABEL: mula_i32:9; RV32XTHEADMAC: # %bb.0:10; RV32XTHEADMAC-NEXT: th.mula a0, a1, a211; RV32XTHEADMAC-NEXT: ret12;13; RV64XTHEADMAC-LABEL: mula_i32:14; RV64XTHEADMAC: # %bb.0:15; RV64XTHEADMAC-NEXT: th.mulaw a0, a1, a216; RV64XTHEADMAC-NEXT: ret17 %d = mul i32 %b, %c18 %e = add i32 %a, %d19 ret i32 %e20}21 22define i32 @muls_i32(i32 %a, i32 %b, i32 %c) {23; RV32XTHEADMAC-LABEL: muls_i32:24; RV32XTHEADMAC: # %bb.0:25; RV32XTHEADMAC-NEXT: th.muls a0, a1, a226; RV32XTHEADMAC-NEXT: ret27;28; RV64XTHEADMAC-LABEL: muls_i32:29; RV64XTHEADMAC: # %bb.0:30; RV64XTHEADMAC-NEXT: th.mulsw a0, a1, a231; RV64XTHEADMAC-NEXT: ret32 %d = mul i32 %b, %c33 %e = sub i32 %a, %d34 ret i32 %e35}36 37define i64 @mula_i64(i64 %a, i64 %b, i64 %c) {38; RV32XTHEADMAC-LABEL: mula_i64:39; RV32XTHEADMAC: # %bb.0:40; RV32XTHEADMAC-NEXT: mulhu a6, a2, a441; RV32XTHEADMAC-NEXT: th.mula a6, a2, a542; RV32XTHEADMAC-NEXT: mv a5, a043; RV32XTHEADMAC-NEXT: th.mula a5, a2, a444; RV32XTHEADMAC-NEXT: th.mula a6, a3, a445; RV32XTHEADMAC-NEXT: sltu a0, a5, a046; RV32XTHEADMAC-NEXT: add a0, a1, a047; RV32XTHEADMAC-NEXT: add a1, a0, a648; RV32XTHEADMAC-NEXT: mv a0, a549; RV32XTHEADMAC-NEXT: ret50;51; RV64XTHEADMAC-LABEL: mula_i64:52; RV64XTHEADMAC: # %bb.0:53; RV64XTHEADMAC-NEXT: th.mula a0, a1, a254; RV64XTHEADMAC-NEXT: ret55 %d = mul i64 %b, %c56 %f = add i64 %a, %d57 ret i64 %f58}59 60define i64 @mulaw_i64(i32 %a, i32 %b, i32 %c) {61; RV32XTHEADMAC-LABEL: mulaw_i64:62; RV32XTHEADMAC: # %bb.0:63; RV32XTHEADMAC-NEXT: th.mula a0, a1, a264; RV32XTHEADMAC-NEXT: srai a1, a0, 3165; RV32XTHEADMAC-NEXT: ret66;67; RV64XTHEADMAC-LABEL: mulaw_i64:68; RV64XTHEADMAC: # %bb.0:69; RV64XTHEADMAC-NEXT: th.mulaw a0, a1, a270; RV64XTHEADMAC-NEXT: ret71 %d = mul i32 %b, %c72 %e = add i32 %a, %d73 %f = sext i32 %e to i6474 ret i64 %f75}76 77define i64 @mulah_i64(i32 %a, i16 %b, i16 %c) {78; RV32XTHEADMAC-LABEL: mulah_i64:79; RV32XTHEADMAC: # %bb.0:80; RV32XTHEADMAC-NEXT: th.mulah a0, a1, a281; RV32XTHEADMAC-NEXT: srai a1, a0, 3182; RV32XTHEADMAC-NEXT: ret83;84; RV64XTHEADMAC-LABEL: mulah_i64:85; RV64XTHEADMAC: # %bb.0:86; RV64XTHEADMAC-NEXT: th.mulah a0, a1, a287; RV64XTHEADMAC-NEXT: ret88 %d = sext i16 %b to i3289 %e = sext i16 %c to i3290 %f = mul i32 %d, %e91 %g = add i32 %a, %f92 %h = sext i32 %g to i6493 ret i64 %h94}95 96define i64 @muls_i64(i64 %a, i64 %b, i64 %c) {97; RV32XTHEADMAC-LABEL: muls_i64:98; RV32XTHEADMAC: # %bb.0:99; RV32XTHEADMAC-NEXT: mulhu a6, a2, a4100; RV32XTHEADMAC-NEXT: th.mula a6, a2, a5101; RV32XTHEADMAC-NEXT: mul a5, a2, a4102; RV32XTHEADMAC-NEXT: sltu a5, a0, a5103; RV32XTHEADMAC-NEXT: th.muls a0, a2, a4104; RV32XTHEADMAC-NEXT: th.mula a6, a3, a4105; RV32XTHEADMAC-NEXT: sub a1, a1, a5106; RV32XTHEADMAC-NEXT: sub a1, a1, a6107; RV32XTHEADMAC-NEXT: ret108;109; RV64XTHEADMAC-LABEL: muls_i64:110; RV64XTHEADMAC: # %bb.0:111; RV64XTHEADMAC-NEXT: th.muls a0, a1, a2112; RV64XTHEADMAC-NEXT: ret113 %d = mul i64 %b, %c114 %f = sub i64 %a, %d115 ret i64 %f116}117 118define i64 @mulsw_i64(i32 %a, i32 %b, i32 %c) {119; RV32XTHEADMAC-LABEL: mulsw_i64:120; RV32XTHEADMAC: # %bb.0:121; RV32XTHEADMAC-NEXT: th.muls a0, a1, a2122; RV32XTHEADMAC-NEXT: srai a1, a0, 31123; RV32XTHEADMAC-NEXT: ret124;125; RV64XTHEADMAC-LABEL: mulsw_i64:126; RV64XTHEADMAC: # %bb.0:127; RV64XTHEADMAC-NEXT: th.mulsw a0, a1, a2128; RV64XTHEADMAC-NEXT: ret129 %d = mul i32 %b, %c130 %e = sub i32 %a, %d131 %f = sext i32 %e to i64132 ret i64 %f133}134 135define i64 @mulsh_i64(i32 %a, i16 %b, i16 %c) {136; RV32XTHEADMAC-LABEL: mulsh_i64:137; RV32XTHEADMAC: # %bb.0:138; RV32XTHEADMAC-NEXT: th.mulsh a0, a1, a2139; RV32XTHEADMAC-NEXT: srai a1, a0, 31140; RV32XTHEADMAC-NEXT: ret141;142; RV64XTHEADMAC-LABEL: mulsh_i64:143; RV64XTHEADMAC: # %bb.0:144; RV64XTHEADMAC-NEXT: th.mulsh a0, a1, a2145; RV64XTHEADMAC-NEXT: ret146 %d = sext i16 %b to i32147 %e = sext i16 %c to i32148 %f = mul i32 %d, %e149 %g = sub i32 %a, %f150 %h = sext i32 %g to i64151 ret i64 %h152}153 154define i32 @commutative1(i32 %A, i32 %B, i32 %C) {155; RV32XTHEADMAC-LABEL: commutative1:156; RV32XTHEADMAC: # %bb.0:157; RV32XTHEADMAC-NEXT: th.mula a2, a1, a0158; RV32XTHEADMAC-NEXT: mv a0, a2159; RV32XTHEADMAC-NEXT: ret160;161; RV64XTHEADMAC-LABEL: commutative1:162; RV64XTHEADMAC: # %bb.0:163; RV64XTHEADMAC-NEXT: th.mulaw a2, a1, a0164; RV64XTHEADMAC-NEXT: mv a0, a2165; RV64XTHEADMAC-NEXT: ret166 %mul = mul nsw i32 %B, %A167 %add = add i32 %mul, %C168 ret i32 %add169}170 171define i32 @commutative2(i32 %A, i32 %B, i32 %C) {172; RV32XTHEADMAC-LABEL: commutative2:173; RV32XTHEADMAC: # %bb.0:174; RV32XTHEADMAC-NEXT: th.mula a0, a1, a2175; RV32XTHEADMAC-NEXT: ret176;177; RV64XTHEADMAC-LABEL: commutative2:178; RV64XTHEADMAC: # %bb.0:179; RV64XTHEADMAC-NEXT: th.mulaw a0, a1, a2180; RV64XTHEADMAC-NEXT: ret181 %mul = mul nsw i32 %B, %C182 %add = add i32 %mul, %A183 ret i32 %add184}185 186define i32 @commutative3(i32 %A, i32 %B, i32 %C) {187; RV32XTHEADMAC-LABEL: commutative3:188; RV32XTHEADMAC: # %bb.0:189; RV32XTHEADMAC-NEXT: th.mula a1, a2, a0190; RV32XTHEADMAC-NEXT: mv a0, a1191; RV32XTHEADMAC-NEXT: ret192;193; RV64XTHEADMAC-LABEL: commutative3:194; RV64XTHEADMAC: # %bb.0:195; RV64XTHEADMAC-NEXT: th.mulaw a1, a2, a0196; RV64XTHEADMAC-NEXT: mv a0, a1197; RV64XTHEADMAC-NEXT: ret198 %mul = mul nsw i32 %C, %A199 %add = add i32 %mul, %B200 ret i32 %add201}202