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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+zbb -O3 < %s \3; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64I4; RUN: llc -mtriple=riscv64 -mattr=+zbb,+f -target-abi=lp64f -O3 < %s \5; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64IF6; Tests aimed to check optimization which combines7; two comparison operations and logic operation into8; one select(min/max) operation and one comparison9; operation.10 11; 4 patterns below will be converted to umin+less.12define i1 @ulo(i64 %c, i64 %a, i64 %b) {13; CHECK-LABEL: ulo:14; CHECK: # %bb.0:15; CHECK-NEXT: minu a1, a1, a216; CHECK-NEXT: sltu a0, a1, a017; CHECK-NEXT: ret18 %l0 = icmp ult i64 %a, %c19 %l1 = icmp ult i64 %b, %c20 %res = or i1 %l0, %l121 ret i1 %res22}23 24define i1 @ulo_swap1(i64 %c, i64 %a, i64 %b) {25; CHECK-LABEL: ulo_swap1:26; CHECK: # %bb.0:27; CHECK-NEXT: minu a1, a1, a228; CHECK-NEXT: sltu a0, a1, a029; CHECK-NEXT: ret30 %l0 = icmp ugt i64 %c, %a31 %l1 = icmp ult i64 %b, %c32 %res = or i1 %l0, %l133 ret i1 %res34}35 36define i1 @ulo_swap2(i64 %c, i64 %a, i64 %b) {37; CHECK-LABEL: ulo_swap2:38; CHECK: # %bb.0:39; CHECK-NEXT: minu a1, a1, a240; CHECK-NEXT: sltu a0, a1, a041; CHECK-NEXT: ret42 %l0 = icmp ult i64 %a, %c43 %l1 = icmp ugt i64 %c, %b44 %res = or i1 %l0, %l145 ret i1 %res46}47 48define i1 @ulo_swap12(i64 %c, i64 %a, i64 %b) {49; CHECK-LABEL: ulo_swap12:50; CHECK: # %bb.0:51; CHECK-NEXT: minu a1, a1, a252; CHECK-NEXT: sltu a0, a1, a053; CHECK-NEXT: ret54 %l0 = icmp ugt i64 %c, %a55 %l1 = icmp ugt i64 %c, %b56 %res = or i1 %l0, %l157 ret i1 %res58}59 60; 4 patterns below will be converted to umax+less.61define i1 @ula(i64 %c, i64 %a, i64 %b) {62; CHECK-LABEL: ula:63; CHECK: # %bb.0:64; CHECK-NEXT: maxu a1, a1, a265; CHECK-NEXT: sltu a0, a1, a066; CHECK-NEXT: ret67 %l0 = icmp ult i64 %a, %c68 %l1 = icmp ult i64 %b, %c69 %res = and i1 %l0, %l170 ret i1 %res71}72 73define i1 @ula_swap1(i64 %c, i64 %a, i64 %b) {74; CHECK-LABEL: ula_swap1:75; CHECK: # %bb.0:76; CHECK-NEXT: maxu a1, a1, a277; CHECK-NEXT: sltu a0, a1, a078; CHECK-NEXT: ret79 %l0 = icmp ugt i64 %c, %a80 %l1 = icmp ult i64 %b, %c81 %res = and i1 %l0, %l182 ret i1 %res83}84 85define i1 @ula_swap2(i64 %c, i64 %a, i64 %b) {86; CHECK-LABEL: ula_swap2:87; CHECK: # %bb.0:88; CHECK-NEXT: maxu a1, a1, a289; CHECK-NEXT: sltu a0, a1, a090; CHECK-NEXT: ret91 %l0 = icmp ult i64 %a, %c92 %l1 = icmp ugt i64 %c, %b93 %res = and i1 %l0, %l194 ret i1 %res95}96 97define i1 @ula_swap12(i64 %c, i64 %a, i64 %b) {98; CHECK-LABEL: ula_swap12:99; CHECK: # %bb.0:100; CHECK-NEXT: maxu a1, a1, a2101; CHECK-NEXT: sltu a0, a1, a0102; CHECK-NEXT: ret103 %l0 = icmp ugt i64 %c, %a104 %l1 = icmp ugt i64 %c, %b105 %res = and i1 %l0, %l1106 ret i1 %res107}108 109; 4 patterns below will be converted to umax+greater110; (greater will be converted to setult somehow)111define i1 @ugo(i64 %c, i64 %a, i64 %b) {112; CHECK-LABEL: ugo:113; CHECK: # %bb.0:114; CHECK-NEXT: maxu a1, a1, a2115; CHECK-NEXT: sltu a0, a0, a1116; CHECK-NEXT: ret117 %l0 = icmp ugt i64 %a, %c118 %l1 = icmp ugt i64 %b, %c119 %res = or i1 %l0, %l1120 ret i1 %res121}122 123define i1 @ugo_swap1(i64 %c, i64 %a, i64 %b) {124; CHECK-LABEL: ugo_swap1:125; CHECK: # %bb.0:126; CHECK-NEXT: maxu a1, a1, a2127; CHECK-NEXT: sltu a0, a0, a1128; CHECK-NEXT: ret129 %l0 = icmp ult i64 %c, %a130 %l1 = icmp ugt i64 %b, %c131 %res = or i1 %l0, %l1132 ret i1 %res133}134 135define i1 @ugo_swap2(i64 %c, i64 %a, i64 %b) {136; CHECK-LABEL: ugo_swap2:137; CHECK: # %bb.0:138; CHECK-NEXT: maxu a1, a1, a2139; CHECK-NEXT: sltu a0, a0, a1140; CHECK-NEXT: ret141 %l0 = icmp ugt i64 %a, %c142 %l1 = icmp ult i64 %c, %b143 %res = or i1 %l0, %l1144 ret i1 %res145}146 147define i1 @ugo_swap12(i64 %c, i64 %a, i64 %b) {148; CHECK-LABEL: ugo_swap12:149; CHECK: # %bb.0:150; CHECK-NEXT: maxu a1, a1, a2151; CHECK-NEXT: sltu a0, a0, a1152; CHECK-NEXT: ret153 %l0 = icmp ult i64 %c, %a154 %l1 = icmp ult i64 %c, %b155 %res = or i1 %l0, %l1156 ret i1 %res157}158 159; Pattern below will be converted to umin+greater or equal160; (greater will be converted to setult somehow)161define i1 @ugea(i64 %c, i64 %a, i64 %b) {162; CHECK-LABEL: ugea:163; CHECK: # %bb.0:164; CHECK-NEXT: minu a1, a1, a2165; CHECK-NEXT: sltu a0, a1, a0166; CHECK-NEXT: xori a0, a0, 1167; CHECK-NEXT: ret168 %l0 = icmp uge i64 %a, %c169 %l1 = icmp uge i64 %b, %c170 %res = and i1 %l0, %l1171 ret i1 %res172}173 174; Pattern below will be converted to umin+greater175; (greater will be converted to setult somehow)176define i1 @uga(i64 %c, i64 %a, i64 %b) {177; CHECK-LABEL: uga:178; CHECK: # %bb.0:179; CHECK-NEXT: minu a1, a1, a2180; CHECK-NEXT: sltu a0, a0, a1181; CHECK-NEXT: ret182 %l0 = icmp ugt i64 %a, %c183 %l1 = icmp ugt i64 %b, %c184 %res = and i1 %l0, %l1185 ret i1 %res186}187 188; Patterns below will be converted to smax+less.189; Sign check.190define i1 @sla(i64 %c, i64 %a, i64 %b) {191; CHECK-LABEL: sla:192; CHECK: # %bb.0:193; CHECK-NEXT: max a1, a1, a2194; CHECK-NEXT: slt a0, a1, a0195; CHECK-NEXT: ret196 %l0 = icmp slt i64 %a, %c197 %l1 = icmp slt i64 %b, %c198 %res = and i1 %l0, %l1199 ret i1 %res200}201 202; Negative test203; Float check.204define i1 @flo(float %c, float %a, float %b) {205; CHECK-RV64I-LABEL: flo:206; CHECK-RV64I: # %bb.0:207; CHECK-RV64I-NEXT: addi sp, sp, -32208; CHECK-RV64I-NEXT: .cfi_def_cfa_offset 32209; CHECK-RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill210; CHECK-RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill211; CHECK-RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill212; CHECK-RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill213; CHECK-RV64I-NEXT: .cfi_offset ra, -8214; CHECK-RV64I-NEXT: .cfi_offset s0, -16215; CHECK-RV64I-NEXT: .cfi_offset s1, -24216; CHECK-RV64I-NEXT: .cfi_offset s2, -32217; CHECK-RV64I-NEXT: mv s0, a2218; CHECK-RV64I-NEXT: mv s1, a0219; CHECK-RV64I-NEXT: mv a0, a1220; CHECK-RV64I-NEXT: mv a1, s1221; CHECK-RV64I-NEXT: call __gesf2222; CHECK-RV64I-NEXT: mv s2, a0223; CHECK-RV64I-NEXT: mv a0, s0224; CHECK-RV64I-NEXT: mv a1, s1225; CHECK-RV64I-NEXT: call __gesf2226; CHECK-RV64I-NEXT: or a0, s2, a0227; CHECK-RV64I-NEXT: srli a0, a0, 63228; CHECK-RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload229; CHECK-RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload230; CHECK-RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload231; CHECK-RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload232; CHECK-RV64I-NEXT: .cfi_restore ra233; CHECK-RV64I-NEXT: .cfi_restore s0234; CHECK-RV64I-NEXT: .cfi_restore s1235; CHECK-RV64I-NEXT: .cfi_restore s2236; CHECK-RV64I-NEXT: addi sp, sp, 32237; CHECK-RV64I-NEXT: .cfi_def_cfa_offset 0238; CHECK-RV64I-NEXT: ret239;240; CHECK-RV64IF-LABEL: flo:241; CHECK-RV64IF: # %bb.0:242; CHECK-RV64IF-NEXT: fle.s a0, fa0, fa1243; CHECK-RV64IF-NEXT: fle.s a1, fa0, fa2244; CHECK-RV64IF-NEXT: and a0, a0, a1245; CHECK-RV64IF-NEXT: xori a0, a0, 1246; CHECK-RV64IF-NEXT: ret247 %l0 = fcmp ult float %a, %c248 %l1 = fcmp ult float %b, %c249 %res = or i1 %l0, %l1250 ret i1 %res251}252 253; Negative test254; Double check.255define i1 @dlo(double %c, double %a, double %b) {256; CHECK-LABEL: dlo:257; CHECK: # %bb.0:258; CHECK-NEXT: addi sp, sp, -32259; CHECK-NEXT: .cfi_def_cfa_offset 32260; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill261; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill262; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill263; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill264; CHECK-NEXT: .cfi_offset ra, -8265; CHECK-NEXT: .cfi_offset s0, -16266; CHECK-NEXT: .cfi_offset s1, -24267; CHECK-NEXT: .cfi_offset s2, -32268; CHECK-NEXT: mv s0, a2269; CHECK-NEXT: mv s1, a0270; CHECK-NEXT: mv a0, a1271; CHECK-NEXT: mv a1, s1272; CHECK-NEXT: call __gedf2273; CHECK-NEXT: mv s2, a0274; CHECK-NEXT: mv a0, s0275; CHECK-NEXT: mv a1, s1276; CHECK-NEXT: call __gedf2277; CHECK-NEXT: or a0, s2, a0278; CHECK-NEXT: srli a0, a0, 63279; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload280; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload281; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload282; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload283; CHECK-NEXT: .cfi_restore ra284; CHECK-NEXT: .cfi_restore s0285; CHECK-NEXT: .cfi_restore s1286; CHECK-NEXT: .cfi_restore s2287; CHECK-NEXT: addi sp, sp, 32288; CHECK-NEXT: .cfi_def_cfa_offset 0289; CHECK-NEXT: ret290 %l0 = fcmp ult double %a, %c291 %l1 = fcmp ult double %b, %c292 %res = or i1 %l0, %l1293 ret i1 %res294}295 296; Negative test297; More than one user298define i1 @multi_user(i64 %c, i64 %a, i64 %b) {299; CHECK-LABEL: multi_user:300; CHECK: # %bb.0:301; CHECK-NEXT: sltu a1, a1, a0302; CHECK-NEXT: sltu a0, a2, a0303; CHECK-NEXT: or a0, a1, a0304; CHECK-NEXT: and a0, a1, a0305; CHECK-NEXT: ret306 %l0 = icmp ugt i64 %c, %a307 %l1 = icmp ult i64 %b, %c308 %res = or i1 %l0, %l1309 310 %out = and i1 %l0, %res311 ret i1 %out312}313 314; Negative test315; No same comparations316define i1 @no_same_ops(i64 %c, i64 %a, i64 %b) {317; CHECK-LABEL: no_same_ops:318; CHECK: # %bb.0:319; CHECK-NEXT: sltu a1, a0, a1320; CHECK-NEXT: sltu a0, a2, a0321; CHECK-NEXT: or a0, a1, a0322; CHECK-NEXT: ret323 %l0 = icmp ult i64 %c, %a324 %l1 = icmp ugt i64 %c, %b325 %res = or i1 %l0, %l1326 ret i1 %res327}328