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1# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42# RUN: llc %s -mtriple=riscv32 -mattr=+zdinx -start-before=prologepilog -o - | FileCheck %s3 4# We want to make sure eliminateFrameIndex doesn't fold sp+2044 as an offset in5# a GPR pair spill/reload instruction. When we split the pair spill, we would be6# unable to add 4 to the immediate without overflowing simm12.7 8--- |9 define void @foo() {10 ; CHECK-LABEL: foo:11 ; CHECK: # %bb.0:12 ; CHECK-NEXT: addi sp, sp, -204813 ; CHECK-NEXT: addi sp, sp, -3214 ; CHECK-NEXT: .cfi_def_cfa_offset 208015 ; CHECK-NEXT: lui t0, 116 ; CHECK-NEXT: add t0, sp, t017 ; CHECK-NEXT: sw a0, -2024(t0) # 4-byte Folded Spill18 ; CHECK-NEXT: sw a1, -2020(t0) # 4-byte Folded Spill19 ; CHECK-NEXT: lui a0, 120 ; CHECK-NEXT: add a0, sp, a021 ; CHECK-NEXT: sw a2, -2032(a0) # 4-byte Folded Spill22 ; CHECK-NEXT: sw a3, -2028(a0) # 4-byte Folded Spill23 ; CHECK-NEXT: lui a0, 124 ; CHECK-NEXT: add a0, sp, a025 ; CHECK-NEXT: sw a4, -2040(a0) # 4-byte Folded Spill26 ; CHECK-NEXT: sw a5, -2036(a0) # 4-byte Folded Spill27 ; CHECK-NEXT: addi a0, sp, 204428 ; CHECK-NEXT: sw a6, 0(a0) # 4-byte Folded Spill29 ; CHECK-NEXT: sw a7, 4(a0) # 4-byte Folded Spill30 ; CHECK-NEXT: lui a0, 131 ; CHECK-NEXT: add a0, sp, a032 ; CHECK-NEXT: lw a1, -2020(a0) # 4-byte Folded Reload33 ; CHECK-NEXT: lw a0, -2024(a0) # 4-byte Folded Reload34 ; CHECK-NEXT: lui a0, 135 ; CHECK-NEXT: add a0, sp, a036 ; CHECK-NEXT: lw a2, -2032(a0) # 4-byte Folded Reload37 ; CHECK-NEXT: lw a3, -2028(a0) # 4-byte Folded Reload38 ; CHECK-NEXT: lui a0, 139 ; CHECK-NEXT: add a0, sp, a040 ; CHECK-NEXT: lw a4, -2040(a0) # 4-byte Folded Reload41 ; CHECK-NEXT: lw a5, -2036(a0) # 4-byte Folded Reload42 ; CHECK-NEXT: addi a0, sp, 204443 ; CHECK-NEXT: lw a6, 0(a0) # 4-byte Folded Reload44 ; CHECK-NEXT: lw a7, 4(a0) # 4-byte Folded Reload45 ; CHECK-NEXT: addi sp, sp, 203246 ; CHECK-NEXT: addi sp, sp, 4847 ; CHECK-NEXT: .cfi_def_cfa_offset 048 ; CHECK-NEXT: ret49 ret void50 }51...52---53name: foo54tracksRegLiveness: true55tracksDebugUserValues: true56frameInfo:57 maxAlignment: 458stack:59 - { id: 0, type: spill-slot, size: 8, alignment: 4 }60 - { id: 1, type: spill-slot, size: 8, alignment: 4 }61 - { id: 2, type: spill-slot, size: 8, alignment: 4 }62 - { id: 3, type: spill-slot, size: 4, alignment: 4 }63 - { id: 4, type: spill-slot, size: 8, alignment: 4 }64 - { id: 5, type: spill-slot, size: 2028, alignment: 4 }65machineFunctionInfo:66 varArgsFrameIndex: 067 varArgsSaveSize: 068body: |69 bb.0:70 liveins: $x10_x11, $x12_x13, $x14_x15, $x16_x1771 72 PseudoRV32ZdinxSD killed renamable $x10_x11, %stack.0, 0 :: (store (s64) into %stack.0, align 4)73 PseudoRV32ZdinxSD killed renamable $x12_x13, %stack.1, 0 :: (store (s64) into %stack.1, align 4)74 PseudoRV32ZdinxSD killed renamable $x14_x15, %stack.2, 0 :: (store (s64) into %stack.2, align 4)75 PseudoRV32ZdinxSD killed renamable $x16_x17, %stack.4, 0 :: (store (s64) into %stack.4, align 4)76 renamable $x10_x11 = PseudoRV32ZdinxLD %stack.0, 0 :: (load (s64) from %stack.0, align 4)77 renamable $x12_x13 = PseudoRV32ZdinxLD %stack.1, 0 :: (load (s64) from %stack.1, align 4)78 renamable $x14_x15 = PseudoRV32ZdinxLD %stack.2, 0 :: (load (s64) from %stack.2, align 4)79 renamable $x16_x17 = PseudoRV32ZdinxLD %stack.4, 0 :: (load (s64) from %stack.4, align 4)80 PseudoRET81 82...83