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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfh \3; RUN: -verify-machineinstrs -target-abi ilp32f | \4; RUN: FileCheck -check-prefix=RV32IZFH %s5; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfh \6; RUN: -verify-machineinstrs -target-abi lp64f | \7; RUN: FileCheck -check-prefix=RV64IZFH %s8; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=zhinx \9; RUN: -verify-machineinstrs -target-abi ilp32 | \10; RUN: FileCheck -check-prefix=RV32IZHINX %s11; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=zhinx \12; RUN: -verify-machineinstrs -target-abi lp64 | \13; RUN: FileCheck -check-prefix=RV64IZHINX %s14; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \15; RUN: -mattr=+zfh -verify-machineinstrs -target-abi ilp32d | \16; RUN: FileCheck -check-prefix=RV32IDZFH %s17; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \18; RUN: -mattr=+zfh -verify-machineinstrs -target-abi lp64d | \19; RUN: FileCheck -check-prefix=RV64IDZFH %s20; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zdinx \21; RUN: -mattr=+zhinx -verify-machineinstrs -target-abi ilp32 | \22; RUN: FileCheck -check-prefix=RV32IZDINXZHINX %s23; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zdinx \24; RUN: -mattr=+zhinx -verify-machineinstrs -target-abi lp64 | \25; RUN: FileCheck -check-prefix=RV64IZDINXZHINX %s26 27; These intrinsics require half to be a legal type.28 29define iXLen @lrint_f16(half %a) nounwind {30; RV32IZFH-LABEL: lrint_f16:31; RV32IZFH: # %bb.0:32; RV32IZFH-NEXT: fcvt.w.h a0, fa033; RV32IZFH-NEXT: ret34;35; RV64IZFH-LABEL: lrint_f16:36; RV64IZFH: # %bb.0:37; RV64IZFH-NEXT: fcvt.l.h a0, fa038; RV64IZFH-NEXT: ret39;40; RV32IZHINX-LABEL: lrint_f16:41; RV32IZHINX: # %bb.0:42; RV32IZHINX-NEXT: fcvt.w.h a0, a043; RV32IZHINX-NEXT: ret44;45; RV64IZHINX-LABEL: lrint_f16:46; RV64IZHINX: # %bb.0:47; RV64IZHINX-NEXT: fcvt.l.h a0, a048; RV64IZHINX-NEXT: ret49;50; RV32IDZFH-LABEL: lrint_f16:51; RV32IDZFH: # %bb.0:52; RV32IDZFH-NEXT: fcvt.w.h a0, fa053; RV32IDZFH-NEXT: ret54;55; RV64IDZFH-LABEL: lrint_f16:56; RV64IDZFH: # %bb.0:57; RV64IDZFH-NEXT: fcvt.l.h a0, fa058; RV64IDZFH-NEXT: ret59;60; RV32IZDINXZHINX-LABEL: lrint_f16:61; RV32IZDINXZHINX: # %bb.0:62; RV32IZDINXZHINX-NEXT: fcvt.w.h a0, a063; RV32IZDINXZHINX-NEXT: ret64;65; RV64IZDINXZHINX-LABEL: lrint_f16:66; RV64IZDINXZHINX: # %bb.0:67; RV64IZDINXZHINX-NEXT: fcvt.l.h a0, a068; RV64IZDINXZHINX-NEXT: ret69 %1 = call iXLen @llvm.lrint.iXLen.f16(half %a)70 ret iXLen %171}72 73define iXLen @lround_f16(half %a) nounwind {74; RV32IZFH-LABEL: lround_f16:75; RV32IZFH: # %bb.0:76; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm77; RV32IZFH-NEXT: ret78;79; RV64IZFH-LABEL: lround_f16:80; RV64IZFH: # %bb.0:81; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rmm82; RV64IZFH-NEXT: ret83;84; RV32IZHINX-LABEL: lround_f16:85; RV32IZHINX: # %bb.0:86; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rmm87; RV32IZHINX-NEXT: ret88;89; RV64IZHINX-LABEL: lround_f16:90; RV64IZHINX: # %bb.0:91; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rmm92; RV64IZHINX-NEXT: ret93;94; RV32IDZFH-LABEL: lround_f16:95; RV32IDZFH: # %bb.0:96; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rmm97; RV32IDZFH-NEXT: ret98;99; RV64IDZFH-LABEL: lround_f16:100; RV64IDZFH: # %bb.0:101; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rmm102; RV64IDZFH-NEXT: ret103;104; RV32IZDINXZHINX-LABEL: lround_f16:105; RV32IZDINXZHINX: # %bb.0:106; RV32IZDINXZHINX-NEXT: fcvt.w.h a0, a0, rmm107; RV32IZDINXZHINX-NEXT: ret108;109; RV64IZDINXZHINX-LABEL: lround_f16:110; RV64IZDINXZHINX: # %bb.0:111; RV64IZDINXZHINX-NEXT: fcvt.l.h a0, a0, rmm112; RV64IZDINXZHINX-NEXT: ret113 %1 = call iXLen @llvm.lround.iXLen.f16(half %a)114 ret iXLen %1115}116 117define i32 @lround_i32_f16(half %a) nounwind {118; RV32IZFH-LABEL: lround_i32_f16:119; RV32IZFH: # %bb.0:120; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm121; RV32IZFH-NEXT: ret122;123; RV64IZFH-LABEL: lround_i32_f16:124; RV64IZFH: # %bb.0:125; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rmm126; RV64IZFH-NEXT: ret127;128; RV32IZHINX-LABEL: lround_i32_f16:129; RV32IZHINX: # %bb.0:130; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rmm131; RV32IZHINX-NEXT: ret132;133; RV64IZHINX-LABEL: lround_i32_f16:134; RV64IZHINX: # %bb.0:135; RV64IZHINX-NEXT: fcvt.w.h a0, a0, rmm136; RV64IZHINX-NEXT: ret137;138; RV32IDZFH-LABEL: lround_i32_f16:139; RV32IDZFH: # %bb.0:140; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rmm141; RV32IDZFH-NEXT: ret142;143; RV64IDZFH-LABEL: lround_i32_f16:144; RV64IDZFH: # %bb.0:145; RV64IDZFH-NEXT: fcvt.w.h a0, fa0, rmm146; RV64IDZFH-NEXT: ret147;148; RV32IZDINXZHINX-LABEL: lround_i32_f16:149; RV32IZDINXZHINX: # %bb.0:150; RV32IZDINXZHINX-NEXT: fcvt.w.h a0, a0, rmm151; RV32IZDINXZHINX-NEXT: ret152;153; RV64IZDINXZHINX-LABEL: lround_i32_f16:154; RV64IZDINXZHINX: # %bb.0:155; RV64IZDINXZHINX-NEXT: fcvt.w.h a0, a0, rmm156; RV64IZDINXZHINX-NEXT: ret157 %1 = call i32 @llvm.lround.i32.f16(half %a)158 ret i32 %1159}160