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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfhmin \3; RUN: -verify-machineinstrs -target-abi ilp32f | \4; RUN: FileCheck -check-prefix=RV32IZFHMIN %s5; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfhmin \6; RUN: -verify-machineinstrs -target-abi lp64f | \7; RUN: FileCheck -check-prefix=RV64IZFHMIN %s8; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \9; RUN: -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32d | \10; RUN: FileCheck -check-prefix=RV32IDZFHMIN %s11; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \12; RUN: -mattr=+zfhmin -verify-machineinstrs -target-abi lp64d | \13; RUN: FileCheck -check-prefix=RV64IDZFHMIN %s14; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zhinxmin \15; RUN: -verify-machineinstrs -target-abi ilp32 | \16; RUN: FileCheck -check-prefix=RV32IZHINXMIN %s17; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zhinxmin \18; RUN: -verify-machineinstrs -target-abi lp64 | \19; RUN: FileCheck -check-prefix=RV64IZHINXMIN %s20; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zdinx \21; RUN: -mattr=+zhinxmin -verify-machineinstrs -target-abi ilp32 | \22; RUN: FileCheck -check-prefix=RV32IZDINXZHINXMIN %s23; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zdinx \24; RUN: -mattr=+zhinxmin -verify-machineinstrs -target-abi lp64 | \25; RUN: FileCheck -check-prefix=RV64IZDINXZHINXMIN %s26 27; These intrinsics require half to be a legal type.28 29define iXLen @lrint_f16(half %a) nounwind {30; RV32IZFHMIN-LABEL: lrint_f16:31; RV32IZFHMIN: # %bb.0:32; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa033; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa534; RV32IZFHMIN-NEXT: ret35;36; RV64IZFHMIN-LABEL: lrint_f16:37; RV64IZFHMIN: # %bb.0:38; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa039; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa540; RV64IZFHMIN-NEXT: ret41;42; RV32IDZFHMIN-LABEL: lrint_f16:43; RV32IDZFHMIN: # %bb.0:44; RV32IDZFHMIN-NEXT: fcvt.s.h fa5, fa045; RV32IDZFHMIN-NEXT: fcvt.w.s a0, fa546; RV32IDZFHMIN-NEXT: ret47;48; RV64IDZFHMIN-LABEL: lrint_f16:49; RV64IDZFHMIN: # %bb.0:50; RV64IDZFHMIN-NEXT: fcvt.s.h fa5, fa051; RV64IDZFHMIN-NEXT: fcvt.l.s a0, fa552; RV64IDZFHMIN-NEXT: ret53;54; RV32IZHINXMIN-LABEL: lrint_f16:55; RV32IZHINXMIN: # %bb.0:56; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a057; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a058; RV32IZHINXMIN-NEXT: ret59;60; RV64IZHINXMIN-LABEL: lrint_f16:61; RV64IZHINXMIN: # %bb.0:62; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a063; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a064; RV64IZHINXMIN-NEXT: ret65;66; RV32IZDINXZHINXMIN-LABEL: lrint_f16:67; RV32IZDINXZHINXMIN: # %bb.0:68; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a069; RV32IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a070; RV32IZDINXZHINXMIN-NEXT: ret71;72; RV64IZDINXZHINXMIN-LABEL: lrint_f16:73; RV64IZDINXZHINXMIN: # %bb.0:74; RV64IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a075; RV64IZDINXZHINXMIN-NEXT: fcvt.l.s a0, a076; RV64IZDINXZHINXMIN-NEXT: ret77 %1 = call iXLen @llvm.lrint.iXLen.f16(half %a)78 ret iXLen %179}80 81define iXLen @lround_f16(half %a) nounwind {82; RV32IZFHMIN-LABEL: lround_f16:83; RV32IZFHMIN: # %bb.0:84; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa085; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm86; RV32IZFHMIN-NEXT: ret87;88; RV64IZFHMIN-LABEL: lround_f16:89; RV64IZFHMIN: # %bb.0:90; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa091; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rmm92; RV64IZFHMIN-NEXT: ret93;94; RV32IDZFHMIN-LABEL: lround_f16:95; RV32IDZFHMIN: # %bb.0:96; RV32IDZFHMIN-NEXT: fcvt.s.h fa5, fa097; RV32IDZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm98; RV32IDZFHMIN-NEXT: ret99;100; RV64IDZFHMIN-LABEL: lround_f16:101; RV64IDZFHMIN: # %bb.0:102; RV64IDZFHMIN-NEXT: fcvt.s.h fa5, fa0103; RV64IDZFHMIN-NEXT: fcvt.l.s a0, fa5, rmm104; RV64IDZFHMIN-NEXT: ret105;106; RV32IZHINXMIN-LABEL: lround_f16:107; RV32IZHINXMIN: # %bb.0:108; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0109; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rmm110; RV32IZHINXMIN-NEXT: ret111;112; RV64IZHINXMIN-LABEL: lround_f16:113; RV64IZHINXMIN: # %bb.0:114; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0115; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rmm116; RV64IZHINXMIN-NEXT: ret117;118; RV32IZDINXZHINXMIN-LABEL: lround_f16:119; RV32IZDINXZHINXMIN: # %bb.0:120; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0121; RV32IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rmm122; RV32IZDINXZHINXMIN-NEXT: ret123;124; RV64IZDINXZHINXMIN-LABEL: lround_f16:125; RV64IZDINXZHINXMIN: # %bb.0:126; RV64IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0127; RV64IZDINXZHINXMIN-NEXT: fcvt.l.s a0, a0, rmm128; RV64IZDINXZHINXMIN-NEXT: ret129 %1 = call iXLen @llvm.lround.iXLen.f16(half %a)130 ret iXLen %1131}132 133define i32 @lround_i32_f16(half %a) nounwind {134; RV32IZFHMIN-LABEL: lround_i32_f16:135; RV32IZFHMIN: # %bb.0:136; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0137; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm138; RV32IZFHMIN-NEXT: ret139;140; RV64IZFHMIN-LABEL: lround_i32_f16:141; RV64IZFHMIN: # %bb.0:142; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0143; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm144; RV64IZFHMIN-NEXT: ret145;146; RV32IDZFHMIN-LABEL: lround_i32_f16:147; RV32IDZFHMIN: # %bb.0:148; RV32IDZFHMIN-NEXT: fcvt.s.h fa5, fa0149; RV32IDZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm150; RV32IDZFHMIN-NEXT: ret151;152; RV64IDZFHMIN-LABEL: lround_i32_f16:153; RV64IDZFHMIN: # %bb.0:154; RV64IDZFHMIN-NEXT: fcvt.s.h fa5, fa0155; RV64IDZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm156; RV64IDZFHMIN-NEXT: ret157;158; RV32IZHINXMIN-LABEL: lround_i32_f16:159; RV32IZHINXMIN: # %bb.0:160; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0161; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rmm162; RV32IZHINXMIN-NEXT: ret163;164; RV64IZHINXMIN-LABEL: lround_i32_f16:165; RV64IZHINXMIN: # %bb.0:166; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0167; RV64IZHINXMIN-NEXT: fcvt.w.s a0, a0, rmm168; RV64IZHINXMIN-NEXT: ret169;170; RV32IZDINXZHINXMIN-LABEL: lround_i32_f16:171; RV32IZDINXZHINXMIN: # %bb.0:172; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0173; RV32IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rmm174; RV32IZDINXZHINXMIN-NEXT: ret175;176; RV64IZDINXZHINXMIN-LABEL: lround_i32_f16:177; RV64IZDINXZHINXMIN: # %bb.0:178; RV64IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0179; RV64IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rmm180; RV64IZDINXZHINXMIN-NEXT: ret181 %1 = call i32 @llvm.lround.i32.f16(half %a)182 ret i32 %1183}184