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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=riscv32 -O2 -verify-machineinstrs -mattr=+b,+zicond < %s | FileCheck %s -check-prefix=RV32ZICOND3; RUN: llc -mtriple=riscv64 -O2 -verify-machineinstrs -mattr=+b,+zicond < %s | FileCheck %s -check-prefix=RV64ZICOND4 5; (and (icmp x. 0, ne), (icmp y, 0, ne)) -> (czero.eqz (icmp x, 0, ne), y)6define i32 @icmp_and(i64 %x, i64 %y) {7; RV32ZICOND-LABEL: icmp_and:8; RV32ZICOND: # %bb.0:9; RV32ZICOND-NEXT: or a2, a2, a310; RV32ZICOND-NEXT: snez a2, a211; RV32ZICOND-NEXT: or a0, a0, a112; RV32ZICOND-NEXT: czero.eqz a0, a2, a013; RV32ZICOND-NEXT: ret14;15; RV64ZICOND-LABEL: icmp_and:16; RV64ZICOND: # %bb.0:17; RV64ZICOND-NEXT: snez a1, a118; RV64ZICOND-NEXT: czero.eqz a0, a1, a019; RV64ZICOND-NEXT: ret20 %3 = icmp ne i64 %y, 021 %4 = icmp ne i64 %x, 022 %5 = and i1 %4, %323 %6 = zext i1 %5 to i3224 ret i32 %625}26 27; Make sure we choose the replace the single use icmp28define i32 @icmp_and_x_multiple_uses(i64 %x, i64 %y) {29; RV32ZICOND-LABEL: icmp_and_x_multiple_uses:30; RV32ZICOND: # %bb.0:31; RV32ZICOND-NEXT: or a2, a2, a332; RV32ZICOND-NEXT: or a0, a0, a133; RV32ZICOND-NEXT: snez a0, a034; RV32ZICOND-NEXT: czero.eqz a1, a0, a235; RV32ZICOND-NEXT: add a0, a1, a036; RV32ZICOND-NEXT: ret37;38; RV64ZICOND-LABEL: icmp_and_x_multiple_uses:39; RV64ZICOND: # %bb.0:40; RV64ZICOND-NEXT: snez a0, a041; RV64ZICOND-NEXT: czero.eqz a1, a0, a142; RV64ZICOND-NEXT: add a0, a1, a043; RV64ZICOND-NEXT: ret44 %3 = icmp ne i64 %y, 045 %4 = icmp ne i64 %x, 046 %5 = and i1 %4, %347 %6 = zext i1 %5 to i3248 %7 = zext i1 %4 to i3249 %8 = add i32 %6, %750 ret i32 %851}52 53; Make sure we choose the replace the single use icmp54define i32 @icmp_and_y_multiple_uses(i64 %x, i64 %y) {55; RV32ZICOND-LABEL: icmp_and_y_multiple_uses:56; RV32ZICOND: # %bb.0:57; RV32ZICOND-NEXT: or a2, a2, a358; RV32ZICOND-NEXT: snez a2, a259; RV32ZICOND-NEXT: or a0, a0, a160; RV32ZICOND-NEXT: czero.eqz a0, a2, a061; RV32ZICOND-NEXT: add a0, a0, a262; RV32ZICOND-NEXT: ret63;64; RV64ZICOND-LABEL: icmp_and_y_multiple_uses:65; RV64ZICOND: # %bb.0:66; RV64ZICOND-NEXT: snez a1, a167; RV64ZICOND-NEXT: czero.eqz a0, a1, a068; RV64ZICOND-NEXT: add a0, a0, a169; RV64ZICOND-NEXT: ret70 %3 = icmp ne i64 %y, 071 %4 = icmp ne i64 %x, 072 %5 = and i1 %4, %373 %6 = zext i1 %5 to i3274 %7 = zext i1 %3 to i3275 %8 = add i32 %6, %776 ret i32 %877}78 79; Both icmp's have multiple uses, don't optimize80define i32 @icmp_and_xy_multiple_uses(i64 %x, i64 %y) {81; RV32ZICOND-LABEL: icmp_and_xy_multiple_uses:82; RV32ZICOND: # %bb.0:83; RV32ZICOND-NEXT: or a2, a2, a384; RV32ZICOND-NEXT: or a0, a0, a185; RV32ZICOND-NEXT: snez a1, a286; RV32ZICOND-NEXT: snez a0, a087; RV32ZICOND-NEXT: and a2, a0, a188; RV32ZICOND-NEXT: add a0, a1, a089; RV32ZICOND-NEXT: add a0, a2, a090; RV32ZICOND-NEXT: ret91;92; RV64ZICOND-LABEL: icmp_and_xy_multiple_uses:93; RV64ZICOND: # %bb.0:94; RV64ZICOND-NEXT: snez a1, a195; RV64ZICOND-NEXT: snez a0, a096; RV64ZICOND-NEXT: and a2, a0, a197; RV64ZICOND-NEXT: add a0, a1, a098; RV64ZICOND-NEXT: add a0, a2, a099; RV64ZICOND-NEXT: ret100 %3 = icmp ne i64 %y, 0101 %4 = icmp ne i64 %x, 0102 %5 = and i1 %4, %3103 %6 = zext i1 %5 to i32104 %7 = zext i1 %3 to i32105 %8 = zext i1 %4 to i32106 %9 = add i32 %6, %7107 %10 = add i32 %9, %8108 ret i32 %10109}110 111 112; (and (icmp x. 0, ne), (icmp y, 0, ne)) -> (czero.eqz (icmp x, 0, ne), y)113define i32 @icmp_and_select(i64 %x, i64 %y, i32 %z) {114; RV32ZICOND-LABEL: icmp_and_select:115; RV32ZICOND: # %bb.0:116; RV32ZICOND-NEXT: sgtz a5, a3117; RV32ZICOND-NEXT: snez a2, a2118; RV32ZICOND-NEXT: czero.eqz a5, a5, a3119; RV32ZICOND-NEXT: czero.nez a2, a2, a3120; RV32ZICOND-NEXT: or a2, a2, a5121; RV32ZICOND-NEXT: or a0, a0, a1122; RV32ZICOND-NEXT: czero.eqz a0, a2, a0123; RV32ZICOND-NEXT: czero.eqz a0, a4, a0124; RV32ZICOND-NEXT: ret125;126; RV64ZICOND-LABEL: icmp_and_select:127; RV64ZICOND: # %bb.0:128; RV64ZICOND-NEXT: sgtz a1, a1129; RV64ZICOND-NEXT: czero.eqz a0, a1, a0130; RV64ZICOND-NEXT: czero.eqz a0, a2, a0131; RV64ZICOND-NEXT: ret132 %3 = icmp sgt i64 %y, 0133 %4 = icmp ne i64 %x, 0134 %5 = and i1 %4, %3135 %6 = select i1 %5, i32 %z, i32 0136 ret i32 %6137}138 139; (and (and (icmp x, 0, ne), (icmp y, 0, ne)), (icmp z, 0, ne)) -> (czero.eqz (czero.eqz (icmp x, 0, ne), y), z)140define i32 @icmp_and_and(i64 %x, i64 %y, i64 %z) {141; RV32ZICOND-LABEL: icmp_and_and:142; RV32ZICOND: # %bb.0:143; RV32ZICOND-NEXT: or a2, a2, a3144; RV32ZICOND-NEXT: or a0, a0, a1145; RV32ZICOND-NEXT: snez a0, a0146; RV32ZICOND-NEXT: czero.eqz a0, a0, a2147; RV32ZICOND-NEXT: or a4, a4, a5148; RV32ZICOND-NEXT: czero.eqz a0, a0, a4149; RV32ZICOND-NEXT: ret150;151; RV64ZICOND-LABEL: icmp_and_and:152; RV64ZICOND: # %bb.0:153; RV64ZICOND-NEXT: snez a0, a0154; RV64ZICOND-NEXT: czero.eqz a0, a0, a1155; RV64ZICOND-NEXT: czero.eqz a0, a0, a2156; RV64ZICOND-NEXT: ret157 %4 = icmp ne i64 %y, 0158 %5 = icmp ne i64 %x, 0159 %6 = and i1 %4, %5160 %7 = icmp ne i64 %z, 0161 %8 = and i1 %7, %6162 %9 = zext i1 %8 to i32163 ret i32 %9164}165 166; (select cond, x, rotl(x, rot.amt)) -> (rotl x, (czero_nez rot.amt, cond))167define i64 @rotate_l_nez(i64 %x, i64 %rot.amt, i1 %cond) {168; RV32ZICOND-LABEL: rotate_l_nez:169; RV32ZICOND: # %bb.0:170; RV32ZICOND-NEXT: andi a4, a4, 1171; RV32ZICOND-NEXT: czero.nez a2, a2, a4172; RV32ZICOND-NEXT: bexti a3, a2, 5173; RV32ZICOND-NEXT: czero.nez a4, a0, a3174; RV32ZICOND-NEXT: czero.eqz a5, a1, a3175; RV32ZICOND-NEXT: czero.nez a1, a1, a3176; RV32ZICOND-NEXT: czero.eqz a0, a0, a3177; RV32ZICOND-NEXT: not a3, a2178; RV32ZICOND-NEXT: or a4, a5, a4179; RV32ZICOND-NEXT: or a0, a0, a1180; RV32ZICOND-NEXT: sll a1, a4, a2181; RV32ZICOND-NEXT: srli a5, a0, 1182; RV32ZICOND-NEXT: sll a2, a0, a2183; RV32ZICOND-NEXT: srli a4, a4, 1184; RV32ZICOND-NEXT: srl a0, a5, a3185; RV32ZICOND-NEXT: srl a3, a4, a3186; RV32ZICOND-NEXT: or a0, a1, a0187; RV32ZICOND-NEXT: or a1, a2, a3188; RV32ZICOND-NEXT: ret189;190; RV64ZICOND-LABEL: rotate_l_nez:191; RV64ZICOND: # %bb.0:192; RV64ZICOND-NEXT: andi a2, a2, 1193; RV64ZICOND-NEXT: czero.nez a1, a1, a2194; RV64ZICOND-NEXT: rol a0, a0, a1195; RV64ZICOND-NEXT: ret196 %6 = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 %rot.amt)197 %7 = select i1 %cond, i64 %x, i64 %6198 ret i64 %7199}200 201; (select cond, rotl(x, rot.amt), x) -> (rotl x, (czero_eqz rot.amt, cond))202define i64 @rotate_l_eqz(i64 %x, i64 %rot.amt, i1 %cond) {203; RV32ZICOND-LABEL: rotate_l_eqz:204; RV32ZICOND: # %bb.0:205; RV32ZICOND-NEXT: andi a4, a4, 1206; RV32ZICOND-NEXT: czero.eqz a2, a2, a4207; RV32ZICOND-NEXT: bexti a3, a2, 5208; RV32ZICOND-NEXT: czero.nez a4, a0, a3209; RV32ZICOND-NEXT: czero.eqz a5, a1, a3210; RV32ZICOND-NEXT: czero.nez a1, a1, a3211; RV32ZICOND-NEXT: czero.eqz a0, a0, a3212; RV32ZICOND-NEXT: not a3, a2213; RV32ZICOND-NEXT: or a4, a5, a4214; RV32ZICOND-NEXT: or a0, a0, a1215; RV32ZICOND-NEXT: sll a1, a4, a2216; RV32ZICOND-NEXT: srli a5, a0, 1217; RV32ZICOND-NEXT: sll a2, a0, a2218; RV32ZICOND-NEXT: srli a4, a4, 1219; RV32ZICOND-NEXT: srl a0, a5, a3220; RV32ZICOND-NEXT: srl a3, a4, a3221; RV32ZICOND-NEXT: or a0, a1, a0222; RV32ZICOND-NEXT: or a1, a2, a3223; RV32ZICOND-NEXT: ret224;225; RV64ZICOND-LABEL: rotate_l_eqz:226; RV64ZICOND: # %bb.0:227; RV64ZICOND-NEXT: andi a2, a2, 1228; RV64ZICOND-NEXT: czero.eqz a1, a1, a2229; RV64ZICOND-NEXT: rol a0, a0, a1230; RV64ZICOND-NEXT: ret231 %6 = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 %rot.amt)232 %7 = select i1 %cond, i64 %6, i64 %x233 ret i64 %7234}235 236; (select cond, const, t) -> (add (czero_nez t - const, cond), const)237define i64 @select_imm_reg(i64 %t, i1 %cond) {238; RV32ZICOND-LABEL: select_imm_reg:239; RV32ZICOND: # %bb.0:240; RV32ZICOND-NEXT: andi a2, a2, 1241; RV32ZICOND-NEXT: addi a0, a0, -3242; RV32ZICOND-NEXT: czero.nez a1, a1, a2243; RV32ZICOND-NEXT: czero.nez a0, a0, a2244; RV32ZICOND-NEXT: addi a0, a0, 3245; RV32ZICOND-NEXT: ret246;247; RV64ZICOND-LABEL: select_imm_reg:248; RV64ZICOND: # %bb.0:249; RV64ZICOND-NEXT: andi a1, a1, 1250; RV64ZICOND-NEXT: addi a0, a0, -3251; RV64ZICOND-NEXT: czero.nez a0, a0, a1252; RV64ZICOND-NEXT: addi a0, a0, 3253; RV64ZICOND-NEXT: ret254 %4 = select i1 %cond, i64 3, i64 %t255 ret i64 %4256}257 258; (select cond, t, const) -> (add (czero_eqz t - const, cond), const)259define i64 @select_reg_imm(i64 %t, i1 %cond) {260; RV32ZICOND-LABEL: select_reg_imm:261; RV32ZICOND: # %bb.0:262; RV32ZICOND-NEXT: andi a2, a2, 1263; RV32ZICOND-NEXT: addi a0, a0, -3264; RV32ZICOND-NEXT: czero.eqz a1, a1, a2265; RV32ZICOND-NEXT: czero.eqz a0, a0, a2266; RV32ZICOND-NEXT: addi a0, a0, 3267; RV32ZICOND-NEXT: ret268;269; RV64ZICOND-LABEL: select_reg_imm:270; RV64ZICOND: # %bb.0:271; RV64ZICOND-NEXT: andi a1, a1, 1272; RV64ZICOND-NEXT: addi a0, a0, -3273; RV64ZICOND-NEXT: czero.eqz a0, a0, a1274; RV64ZICOND-NEXT: addi a0, a0, 3275; RV64ZICOND-NEXT: ret276 %4 = select i1 %cond, i64 %t, i64 3277 ret i64 %4278}279 280; (select cond, -2048, t) -> (xor (czero_nez (xor t, -2048), cond), -2048)281define i64 @select_imm_reg_neg_2048(i64 %t, i1 %cond) {282; RV32ZICOND-LABEL: select_imm_reg_neg_2048:283; RV32ZICOND: # %bb.0:284; RV32ZICOND-NEXT: andi a2, a2, 1285; RV32ZICOND-NEXT: xori a0, a0, -2048286; RV32ZICOND-NEXT: neg a3, a2287; RV32ZICOND-NEXT: czero.nez a0, a0, a2288; RV32ZICOND-NEXT: or a1, a3, a1289; RV32ZICOND-NEXT: xori a0, a0, -2048290; RV32ZICOND-NEXT: ret291;292; RV64ZICOND-LABEL: select_imm_reg_neg_2048:293; RV64ZICOND: # %bb.0:294; RV64ZICOND-NEXT: andi a1, a1, 1295; RV64ZICOND-NEXT: xori a0, a0, -2048296; RV64ZICOND-NEXT: czero.nez a0, a0, a1297; RV64ZICOND-NEXT: xori a0, a0, -2048298; RV64ZICOND-NEXT: ret299 %4 = select i1 %cond, i64 -2048, i64 %t300 ret i64 %4301}302 303; (select cond, 2048, t) -> no transform304define i64 @select_imm_reg_2048(i64 %t, i1 %cond) {305; RV32ZICOND-LABEL: select_imm_reg_2048:306; RV32ZICOND: # %bb.0:307; RV32ZICOND-NEXT: andi a2, a2, 1308; RV32ZICOND-NEXT: bseti a3, zero, 11309; RV32ZICOND-NEXT: czero.nez a0, a0, a2310; RV32ZICOND-NEXT: czero.eqz a3, a3, a2311; RV32ZICOND-NEXT: or a0, a3, a0312; RV32ZICOND-NEXT: czero.nez a1, a1, a2313; RV32ZICOND-NEXT: ret314;315; RV64ZICOND-LABEL: select_imm_reg_2048:316; RV64ZICOND: # %bb.0:317; RV64ZICOND-NEXT: andi a1, a1, 1318; RV64ZICOND-NEXT: bseti a2, zero, 11319; RV64ZICOND-NEXT: czero.nez a0, a0, a1320; RV64ZICOND-NEXT: czero.eqz a1, a2, a1321; RV64ZICOND-NEXT: or a0, a1, a0322; RV64ZICOND-NEXT: ret323 %4 = select i1 %cond, i64 2048, i64 %t324 ret i64 %4325}326 327; (select cond, (and f, ~x), f) -> (andn f, (czero_eqz x, cond))328define i64 @test_inv_and_nez(i64 %f, i64 %x, i1 %cond) {329; RV32ZICOND-LABEL: test_inv_and_nez:330; RV32ZICOND: # %bb.0:331; RV32ZICOND-NEXT: andi a4, a4, 1332; RV32ZICOND-NEXT: czero.eqz a3, a3, a4333; RV32ZICOND-NEXT: czero.eqz a2, a2, a4334; RV32ZICOND-NEXT: andn a0, a0, a2335; RV32ZICOND-NEXT: andn a1, a1, a3336; RV32ZICOND-NEXT: ret337;338; RV64ZICOND-LABEL: test_inv_and_nez:339; RV64ZICOND: # %bb.0:340; RV64ZICOND-NEXT: andi a2, a2, 1341; RV64ZICOND-NEXT: czero.eqz a1, a1, a2342; RV64ZICOND-NEXT: andn a0, a0, a1343; RV64ZICOND-NEXT: ret344 %5 = xor i64 %x, -1345 %6 = select i1 %cond, i64 %5, i64 -1346 %7 = and i64 %6, %f347 ret i64 %7348}349 350; (select cond, f, (and f, ~x)) -> (andn f, (czero_nez x, cond))351define i64 @test_inv_and_eqz(i64 %f, i64 %x, i1 %cond) {352; RV32ZICOND-LABEL: test_inv_and_eqz:353; RV32ZICOND: # %bb.0:354; RV32ZICOND-NEXT: andi a4, a4, 1355; RV32ZICOND-NEXT: czero.nez a3, a3, a4356; RV32ZICOND-NEXT: czero.nez a2, a2, a4357; RV32ZICOND-NEXT: andn a0, a0, a2358; RV32ZICOND-NEXT: andn a1, a1, a3359; RV32ZICOND-NEXT: ret360;361; RV64ZICOND-LABEL: test_inv_and_eqz:362; RV64ZICOND: # %bb.0:363; RV64ZICOND-NEXT: andi a2, a2, 1364; RV64ZICOND-NEXT: czero.nez a1, a1, a2365; RV64ZICOND-NEXT: andn a0, a0, a1366; RV64ZICOND-NEXT: ret367 %5 = xor i64 %x, -1368 %6 = select i1 %cond, i64 -1, i64 %5369 %7 = and i64 %6, %f370 ret i64 %7371}372 373define i32 @pr166596(i32 %conv.i, i1 %iszero) #0 {374; RV32ZICOND-LABEL: pr166596:375; RV32ZICOND: # %bb.0: # %entry376; RV32ZICOND-NEXT: andi a1, a1, 1377; RV32ZICOND-NEXT: xori a0, a0, 1378; RV32ZICOND-NEXT: zext.h a0, a0379; RV32ZICOND-NEXT: clz a0, a0380; RV32ZICOND-NEXT: addi a0, a0, 41381; RV32ZICOND-NEXT: czero.nez a0, a0, a1382; RV32ZICOND-NEXT: addi a0, a0, -9383; RV32ZICOND-NEXT: ret384;385; RV64ZICOND-LABEL: pr166596:386; RV64ZICOND: # %bb.0: # %entry387; RV64ZICOND-NEXT: andi a1, a1, 1388; RV64ZICOND-NEXT: xori a0, a0, 1389; RV64ZICOND-NEXT: zext.h a0, a0390; RV64ZICOND-NEXT: clz a0, a0391; RV64ZICOND-NEXT: addi a0, a0, 9392; RV64ZICOND-NEXT: czero.nez a0, a0, a1393; RV64ZICOND-NEXT: addi a0, a0, -9394; RV64ZICOND-NEXT: ret395entry:396 %not.i = xor i32 %conv.i, 1397 %conv2.i = trunc i32 %not.i to i16398 %conv22 = zext i16 %conv2.i to i64399 %0 = call i64 @llvm.ctlz.i64(i64 %conv22, i1 false)400 %cast = trunc i64 %0 to i32401 %clzg = select i1 %iszero, i32 -9, i32 %cast402 ret i32 %clzg403}404