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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# NOTE: Test expansion of PseudoLD_RV32_OPT/PseudoSD_RV32_OPT after register allocation3# RUN: llc -mtriple=riscv32 -mattr=+zilsd -run-pass riscv-load-store-opt %s -o - | FileCheck %s4--- |5 define i32 @expand_pseudold_valid(ptr %0) {6 %2 = load i32, ptr %0, align 47 %3 = getelementptr inbounds i32, ptr %0, i32 18 %4 = load i32, ptr %3, align 49 %5 = add i32 %2, %410 ret i32 %511 }12 13 define void @expand_pseudosd_valid(ptr %0, i32 %1, i32 %2) {14 store i32 %1, ptr %0, align 415 %4 = getelementptr inbounds i32, ptr %0, i32 116 store i32 %2, ptr %4, align 417 ret void18 }19 20 define i32 @expand_pseudold_invalid_pair(ptr %0) {21 %2 = load i32, ptr %0, align 422 %3 = getelementptr inbounds i32, ptr %0, i32 123 %4 = load i32, ptr %3, align 424 %5 = add i32 %2, %425 ret i32 %526 }27 28 define void @expand_pseudosd_invalid_pair(ptr %0, i32 %1, i32 %2) {29 store i32 %1, ptr %0, align 430 %4 = getelementptr inbounds i32, ptr %0, i32 131 store i32 %2, ptr %4, align 432 ret void33 }34 35 define void @store_zero_combine_valid(ptr %0) {36 store i32 0, ptr %0, align 837 %2 = getelementptr inbounds i32, ptr %0, i32 138 store i32 0, ptr %2, align 839 ret void40 }41 42 define void @store_zero_combine_invalid(ptr %0, i32 %1) {43 store i32 %1, ptr %0, align 844 %3 = getelementptr inbounds i32, ptr %0, i32 145 store i32 0, ptr %3, align 846 ret void47 }48 49 @global_array = external global [100 x i32]50 51 define i32 @expand_pseudold_invalid_symbolic() {52 ret i32 053 }54 55 define i32 @overlapped_first_reg_base_reg() {56 ret i32 057 }58...59---60# Valid consecutive even/odd register pair - should expand to LD_RV3261name: expand_pseudold_valid62tracksRegLiveness: false63body: |64 bb.0:65 liveins: $x1066 67 ; PseudoLD_RV32_OPT with consecutive even/odd registers (x12, x13)68 ; CHECK-LABEL: name: expand_pseudold_valid69 ; CHECK: liveins: $x1070 ; CHECK-NEXT: {{ $}}71 ; CHECK-NEXT: $x12_x13 = LD_RV32 killed $x10, 072 ; CHECK-NEXT: $x10 = ADD killed $x12, killed $x1373 ; CHECK-NEXT: PseudoRET implicit $x1074 $x12, $x13 = PseudoLD_RV32_OPT killed $x10, 075 $x10 = ADD killed $x12, killed $x1376 PseudoRET implicit $x1077 78...79---80# Valid consecutive even/odd register pair - should expand to SD_RV3281name: expand_pseudosd_valid82tracksRegLiveness: false83body: |84 bb.0:85 liveins: $x10, $x12, $x1386 87 ; PseudoSD_RV32_OPT with consecutive even/odd registers (x12, x13)88 ; CHECK-LABEL: name: expand_pseudosd_valid89 ; CHECK: liveins: $x10, $x12, $x1390 ; CHECK-NEXT: {{ $}}91 ; CHECK-NEXT: SD_RV32 killed $x12_x13, killed $x10, 092 ; CHECK-NEXT: PseudoRET93 PseudoSD_RV32_OPT killed $x12, killed $x13, killed $x10, 094 PseudoRET95 96...97---98# Invalid register pair (not consecutive) - should decompose back to LW99name: expand_pseudold_invalid_pair100tracksRegLiveness: false101body: |102 bb.0:103 liveins: $x10104 105 ; PseudoLD_RV32_OPT with non-consecutive registers (x11, x13)106 ; Should decompose back to two LW instructions107 ; CHECK-LABEL: name: expand_pseudold_invalid_pair108 ; CHECK: liveins: $x10109 ; CHECK-NEXT: {{ $}}110 ; CHECK-NEXT: $x11 = LW $x10, 0111 ; CHECK-NEXT: $x13 = LW killed $x10, 4112 ; CHECK-NEXT: $x10 = ADD killed $x11, killed $x13113 ; CHECK-NEXT: PseudoRET implicit $x10114 $x11, $x13 = PseudoLD_RV32_OPT killed $x10, 0115 $x10 = ADD killed $x11, killed $x13116 PseudoRET implicit $x10117 118...119---120# Invalid register pair (not even/odd) - should decompose back to SW121name: expand_pseudosd_invalid_pair122tracksRegLiveness: false123body: |124 bb.0:125 liveins: $x10, $x11, $x14126 127 ; PseudoSD_RV32_OPT with non-consecutive registers (x11, x14)128 ; Should decompose back to two SW instructions129 ; CHECK-LABEL: name: expand_pseudosd_invalid_pair130 ; CHECK: liveins: $x10, $x11, $x14131 ; CHECK-NEXT: {{ $}}132 ; CHECK-NEXT: SW killed $x11, $x10, 0133 ; CHECK-NEXT: SW killed $x14, killed $x10, 4134 ; CHECK-NEXT: PseudoRET135 PseudoSD_RV32_OPT killed $x11, killed $x14, killed $x10, 0136 PseudoRET137 138...139---140# Test store zero combinations - zeros don't need consecutive pairs141name: store_zero_combine_valid142tracksRegLiveness: false143body: |144 bb.0:145 liveins: $x10146 ; CHECK-LABEL: name: store_zero_combine_valid147 ; CHECK: liveins: $x10148 ; CHECK-NEXT: {{ $}}149 ; CHECK-NEXT: SD_RV32 $x0_pair, killed $x10, 0150 ; CHECK-NEXT: PseudoRET151 PseudoSD_RV32_OPT $x0, $x0, killed $x10, 0152 PseudoRET153 154...155---156# Test store zero base combinations - zero can't be first register unless both157# are zeros158name: store_zero_combine_invalid159tracksRegLiveness: false160body: |161 bb.0:162 liveins: $x10163 ; CHECK-LABEL: name: store_zero_combine_invalid164 ; CHECK: liveins: $x10165 ; CHECK-NEXT: {{ $}}166 ; CHECK-NEXT: SW killed $x0, $x10, 0167 ; CHECK-NEXT: SW killed $x1, killed $x10, 4168 ; CHECK-NEXT: PseudoRET169 PseudoSD_RV32_OPT killed $x0, killed $x1, killed $x10, 0170 PseudoRET171 172...173---174# Test invalid register pair with symbolic operands - should split back to LW175name: expand_pseudold_invalid_symbolic176tracksRegLiveness: false177body: |178 bb.0:179 liveins: $x10180 181 ; PseudoLD_RV32_OPT with symbolic operand and non-consecutive registers (x11, x14)182 ; Should decompose back to two LW instructions preserving symbolic references183 ; CHECK-LABEL: name: expand_pseudold_invalid_symbolic184 ; CHECK: liveins: $x10185 ; CHECK-NEXT: {{ $}}186 ; CHECK-NEXT: $x11 = LW $x10, target-flags(riscv-lo) @global_array187 ; CHECK-NEXT: $x14 = LW killed $x10, target-flags(riscv-lo) @global_array + 4188 ; CHECK-NEXT: $x10 = ADD killed $x11, killed $x14189 ; CHECK-NEXT: PseudoRET implicit $x10190 $x11, $x14 = PseudoLD_RV32_OPT killed $x10, target-flags(riscv-lo) @global_array191 $x10 = ADD killed $x11, killed $x14192 PseudoRET implicit $x10193 194...195---196# Test overlapped first reg and base reg - should split back to LW197name: overlapped_first_reg_base_reg198tracksRegLiveness: false199body: |200 bb.0:201 liveins: $x10202 203 ; PseudoLD_RV32_OPT with first destination register overlapping base register ($x11)204 ; Should decompose back to two LW instructions when first reg overlaps base reg205 ; CHECK-LABEL: name: overlapped_first_reg_base_reg206 ; CHECK: liveins: $x10207 ; CHECK-NEXT: {{ $}}208 ; CHECK-NEXT: $x14 = LW $x11, 4209 ; CHECK-NEXT: $x11 = LW killed $x11, 0210 ; CHECK-NEXT: $x10 = ADD killed $x11, killed $x14211 ; CHECK-NEXT: PseudoRET implicit $x10212 $x11, $x14 = PseudoLD_RV32_OPT killed $x11, 0213 $x10 = ADD killed $x11, killed $x14214 PseudoRET implicit $x10215 216...217