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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple=riscv32 -mattr=+zilsd -run-pass riscv-prera-zilsd-opt %s -o - | FileCheck %s3# RUN: llc -mtriple=riscv32 -mattr=+zilsd,+zilsd-4byte-align -run-pass riscv-prera-zilsd-opt %s -o - | FileCheck %s --check-prefix=CHECK-4BYTE4--- |5 declare void @external_func()6 7 define i32 @basic_load_combine(ptr %0) {8 %2 = load i32, ptr %0, align 49 %3 = getelementptr inbounds i32, ptr %0, i32 110 %4 = load i32, ptr %3, align 411 %5 = add i32 %2, %412 ret i32 %513 }14 15 define void @basic_store_combine(ptr %0, i32 %1, i32 %2) {16 store i32 %1, ptr %0, align 417 %4 = getelementptr inbounds i32, ptr %0, i32 118 store i32 %2, ptr %4, align 419 ret void20 }21 22 define i32 @basic_load_combine_8_byte_aligned(ptr %0) {23 %2 = load i32, ptr %0, align 824 %3 = getelementptr inbounds i32, ptr %0, i32 125 %4 = load i32, ptr %3, align 426 %5 = add i32 %2, %427 ret i32 %528 }29 30 define void @basic_store_combine_8_byte_aligned(ptr %0, i32 %1, i32 %2) {31 store i32 %1, ptr %0, align 832 %4 = getelementptr inbounds i32, ptr %0, i32 133 store i32 %2, ptr %4, align 434 ret void35 }36 37 38 define i32 @non_consecutive_offsets(ptr %0) {39 %2 = load i32, ptr %0, align 440 %3 = getelementptr inbounds i32, ptr %0, i32 241 %4 = load i32, ptr %3, align 442 %5 = add i32 %2, %443 ret i32 %544 }45 46 define i32 @different_base_regs(ptr %0, ptr %1) {47 %3 = load i32, ptr %0, align 448 %4 = getelementptr inbounds i32, ptr %1, i32 149 %5 = load i32, ptr %4, align 450 %6 = add i32 %3, %551 ret i32 %652 }53 54 define i32 @call_blocks_optimization(ptr %0) {55 %2 = load i32, ptr %0, align 456 call void @external_func()57 %3 = getelementptr inbounds i32, ptr %0, i32 158 %4 = load i32, ptr %3, align 459 %5 = add i32 %2, %460 ret i32 %561 }62 63 define i32 @terminator_blocks_optimization(ptr %0, i32 %1) {64 %3 = load i32, ptr %0, align 465 %4 = icmp eq i32 %1, %366 br i1 %4, label %5, label %567 5:68 %6 = getelementptr inbounds i32, ptr %0, i32 169 %7 = load i32, ptr %6, align 470 %8 = add i32 %3, %771 ret i32 %872 }73 74 define i32 @memory_aliasing(ptr %0, i32 %1) {75 %3 = load i32, ptr %0, align 476 %4 = getelementptr inbounds i32, ptr %0, i32 277 store i32 %1, ptr %4, align 478 %5 = getelementptr inbounds i32, ptr %0, i32 179 %6 = load i32, ptr %5, align 480 %7 = add i32 %3, %681 ret i32 %782 }83 84 define i32 @multiple_pairs(ptr %0, ptr %1) {85 %3 = load i32, ptr %0, align 486 %4 = getelementptr inbounds i32, ptr %0, i32 187 %5 = load i32, ptr %4, align 488 %6 = add i32 %3, %589 %7 = getelementptr inbounds i32, ptr %1, i32 290 %8 = load i32, ptr %7, align 491 %9 = getelementptr inbounds i32, ptr %1, i32 392 %10 = load i32, ptr %9, align 493 %11 = add i32 %8, %1094 %12 = add i32 %6, %1195 ret i32 %1296 }97 98 define i32 @many_loads(ptr %0) {99 %2 = getelementptr inbounds i32, ptr %0, i32 4100 %3 = load i32, ptr %2, align 4101 %4 = getelementptr inbounds i32, ptr %0, i32 5102 %5 = load i32, ptr %4, align 4103 %6 = getelementptr inbounds i32, ptr %0, i32 6104 %7 = load i32, ptr %6, align 4105 %8 = getelementptr inbounds i32, ptr %0, i32 7106 %9 = load i32, ptr %8, align 4107 %10 = getelementptr inbounds i32, ptr %0, i32 8108 %11 = load i32, ptr %10, align 4109 %12 = getelementptr inbounds i32, ptr %0, i32 9110 %13 = load i32, ptr %12, align 4111 %14 = getelementptr inbounds i32, ptr %0, i32 10112 %15 = load i32, ptr %14, align 4113 %16 = getelementptr inbounds i32, ptr %0, i32 11114 %17 = load i32, ptr %16, align 4115 %18 = getelementptr inbounds i32, ptr %0, i32 12116 %19 = load i32, ptr %18, align 4117 %20 = getelementptr inbounds i32, ptr %0, i32 13118 %21 = load i32, ptr %20, align 4119 %22 = getelementptr inbounds i32, ptr %0, i32 14120 %23 = load i32, ptr %22, align 4121 %24 = getelementptr inbounds i32, ptr %0, i32 15122 %25 = load i32, ptr %24, align 4123 %26 = load i32, ptr %0, align 4124 %27 = getelementptr inbounds i32, ptr %0, i32 1125 %28 = load i32, ptr %27, align 4126 %29 = add i32 %3, %5127 %30 = add i32 %7, %9128 %31 = add i32 %11, %13129 %32 = add i32 %15, %17130 %33 = add i32 %19, %21131 %34 = add i32 %23, %25132 %35 = add i32 %26, %28133 %36 = add i32 %29, %30134 %37 = add i32 %31, %32135 %38 = add i32 %33, %34136 %39 = add i32 %35, %36137 %40 = add i32 %37, %38138 %41 = add i32 %39, %40139 ret i32 %41140 }141 142 define i32 @reverse_order_loads(ptr %0) {143 %2 = getelementptr inbounds i32, ptr %0, i32 1144 %3 = load i32, ptr %2, align 4145 %4 = load i32, ptr %0, align 4146 %5 = add i32 %3, %4147 ret i32 %5148 }149 150 define i32 @offset_calculation(ptr %0) {151 %2 = getelementptr inbounds i8, ptr %0, i32 100152 %3 = load i32, ptr %2, align 4153 %4 = getelementptr inbounds i8, ptr %0, i32 104154 %5 = load i32, ptr %4, align 4155 %6 = add i32 %3, %5156 ret i32 %6157 }158 159 define i32 @large_offsets(ptr %0) {160 %2 = getelementptr inbounds i8, ptr %0, i32 2040161 %3 = load i32, ptr %2, align 4162 %4 = getelementptr inbounds i8, ptr %0, i32 2044163 %5 = load i32, ptr %4, align 4164 %6 = add i32 %3, %5165 ret i32 %6166 }167 168 define i32 @negative_offsets(ptr %0) {169 %2 = getelementptr inbounds i8, ptr %0, i32 -8170 %3 = load i32, ptr %2, align 4171 %4 = getelementptr inbounds i8, ptr %0, i32 -4172 %5 = load i32, ptr %4, align 4173 %6 = add i32 %3, %5174 ret i32 %6175 }176 177 define i32 @volatile_loads(ptr %0) {178 %2 = load volatile i32, ptr %0, align 4179 %3 = getelementptr inbounds i32, ptr %0, i32 1180 %4 = load volatile i32, ptr %3, align 4181 %5 = add i32 %2, %4182 ret i32 %5183 }184 185 define i32 @store_dependency(ptr %0, i32 %1) {186 %3 = load i32, ptr %0, align 4187 %4 = getelementptr inbounds i32, ptr %0, i32 1188 store i32 %1, ptr %4, align 4189 %5 = load i32, ptr %4, align 4190 %6 = add i32 %3, %5191 ret i32 %6192 }193 194 define i32 @three_loads(ptr %0) {195 %2 = load i32, ptr %0, align 4196 %3 = getelementptr inbounds i32, ptr %0, i32 1197 %4 = load i32, ptr %3, align 4198 %5 = getelementptr inbounds i32, ptr %0, i32 2199 %6 = load i32, ptr %5, align 4200 %7 = add i32 %2, %4201 %8 = add i32 %7, %6202 ret i32 %8203 }204 205 define i32 @distance_exceeds_max(ptr %0, i32 %1) {206 %3 = load i32, ptr %0, align 4207 %4 = add i32 %3, %1208 %5 = add i32 %4, %1209 %6 = add i32 %5, %1210 %7 = add i32 %6, %1211 %8 = add i32 %7, %1212 %9 = add i32 %8, %1213 %10 = add i32 %9, %1214 %11 = add i32 %10, %1215 %12 = add i32 %11, %1216 %13 = add i32 %12, %1217 %14 = add i32 %13, %1218 %15 = getelementptr inbounds i32, ptr %0, i32 1219 %16 = load i32, ptr %15, align 4220 %17 = add i32 %14, %16221 ret i32 %17222 }223 224 @global_var = external global [100 x i32]225 226 define i32 @symbolic_operands_global() {227 ret i32 0228 }229 230 define i32 @symbolic_operands_different_globals() {231 ret i32 0232 }233 234 define i32 @symbolic_operands_constantpool() {235 ret i32 0236 }237 238 define i32 @symbolic_operands_interleave() {239 ret i32 0240 }241---242# Basic case: two consecutive 32-bit loads that can be combined into LD243name: basic_load_combine244alignment: 4245tracksRegLiveness: true246liveins:247 - { reg: '$x10', virtual-reg: '%0' }248body: |249 bb.0:250 liveins: $x10251 252 ; CHECK-LABEL: name: basic_load_combine253 ; CHECK: liveins: $x10254 ; CHECK-NEXT: {{ $}}255 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10256 ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32))257 ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32))258 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]]259 ; CHECK-NEXT: PseudoRET260 ;261 ; CHECK-4BYTE-LABEL: name: basic_load_combine262 ; CHECK-4BYTE: liveins: $x10263 ; CHECK-4BYTE-NEXT: {{ $}}264 ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10265 ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32))266 ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]]267 ; CHECK-4BYTE-NEXT: PseudoRET268 %0:gpr = COPY $x10269 %1:gpr = LW %0, 0 :: (load (s32))270 %2:gpr = LW %0, 4 :: (load (s32))271 %3:gpr = ADD %1, %2272 PseudoRET273 274...275---276# Basic case: two consecutive 32-bit stores that can be combined into SD277name: basic_store_combine278alignment: 4279tracksRegLiveness: true280liveins:281 - { reg: '$x10', virtual-reg: '%0' }282 - { reg: '$x11', virtual-reg: '%1' }283 - { reg: '$x12', virtual-reg: '%2' }284body: |285 bb.0:286 liveins: $x10, $x11, $x12287 288 ; CHECK-LABEL: name: basic_store_combine289 ; CHECK: liveins: $x10, $x11, $x12290 ; CHECK-NEXT: {{ $}}291 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10292 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11293 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12294 ; CHECK-NEXT: SW [[COPY1]], [[COPY]], 0 :: (store (s32))295 ; CHECK-NEXT: SW [[COPY2]], [[COPY]], 4 :: (store (s32))296 ; CHECK-NEXT: PseudoRET297 ;298 ; CHECK-4BYTE-LABEL: name: basic_store_combine299 ; CHECK-4BYTE: liveins: $x10, $x11, $x12300 ; CHECK-4BYTE-NEXT: {{ $}}301 ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10302 ; CHECK-4BYTE-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11303 ; CHECK-4BYTE-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12304 ; CHECK-4BYTE-NEXT: PseudoSD_RV32_OPT [[COPY1]], [[COPY2]], [[COPY]], 0 :: (store (s32))305 ; CHECK-4BYTE-NEXT: PseudoRET306 %0:gpr = COPY $x10307 %1:gpr = COPY $x11308 %2:gpr = COPY $x12309 SW %1, %0, 0 :: (store (s32))310 SW %2, %0, 4 :: (store (s32))311 PseudoRET312 313...314---315name: basic_load_combine_8_byte_aligned316alignment: 8317tracksRegLiveness: true318liveins:319 - { reg: '$x10', virtual-reg: '%0' }320body: |321 bb.0:322 liveins: $x10323 324 ; CHECK-LABEL: name: basic_load_combine_8_byte_aligned325 ; CHECK: liveins: $x10326 ; CHECK-NEXT: {{ $}}327 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10328 ; CHECK-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32), align 8), (load (s32))329 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]]330 ; CHECK-NEXT: PseudoRET331 ;332 ; CHECK-4BYTE-LABEL: name: basic_load_combine_8_byte_aligned333 ; CHECK-4BYTE: liveins: $x10334 ; CHECK-4BYTE-NEXT: {{ $}}335 ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10336 ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32), align 8), (load (s32))337 ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]]338 ; CHECK-4BYTE-NEXT: PseudoRET339 %0:gpr = COPY $x10340 %1:gpr = LW %0, 0 :: (load (s32), align 8)341 %2:gpr = LW %0, 4 :: (load (s32))342 %3:gpr = ADD %1, %2343 PseudoRET344 345...346---347# Basic case: two consecutive 32-bit stores that can be combined into SD348name: basic_store_combine_8_byte_aligned349alignment: 8350tracksRegLiveness: true351liveins:352 - { reg: '$x10', virtual-reg: '%0' }353 - { reg: '$x11', virtual-reg: '%1' }354 - { reg: '$x12', virtual-reg: '%2' }355body: |356 bb.0:357 liveins: $x10, $x11, $x12358 359 ; CHECK-LABEL: name: basic_store_combine_8_byte_aligned360 ; CHECK: liveins: $x10, $x11, $x12361 ; CHECK-NEXT: {{ $}}362 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10363 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11364 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12365 ; CHECK-NEXT: PseudoSD_RV32_OPT [[COPY1]], [[COPY2]], [[COPY]], 0 :: (store (s32), align 8), (store (s32))366 ; CHECK-NEXT: PseudoRET367 ;368 ; CHECK-4BYTE-LABEL: name: basic_store_combine_8_byte_aligned369 ; CHECK-4BYTE: liveins: $x10, $x11, $x12370 ; CHECK-4BYTE-NEXT: {{ $}}371 ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10372 ; CHECK-4BYTE-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11373 ; CHECK-4BYTE-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12374 ; CHECK-4BYTE-NEXT: PseudoSD_RV32_OPT [[COPY1]], [[COPY2]], [[COPY]], 0 :: (store (s32), align 8), (store (s32))375 ; CHECK-4BYTE-NEXT: PseudoRET376 %0:gpr = COPY $x10377 %1:gpr = COPY $x11378 %2:gpr = COPY $x12379 SW %1, %0, 0 :: (store (s32), align 8)380 SW %2, %0, 4 :: (store (s32))381 PseudoRET382 383...384---385# Non-consecutive offsets - should not combine386name: non_consecutive_offsets387alignment: 4388tracksRegLiveness: true389liveins:390 - { reg: '$x10', virtual-reg: '%0' }391body: |392 bb.0:393 liveins: $x10394 395 ; CHECK-LABEL: name: non_consecutive_offsets396 ; CHECK: liveins: $x10397 ; CHECK-NEXT: {{ $}}398 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10399 ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32))400 ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 8 :: (load (s32))401 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]]402 ; CHECK-NEXT: PseudoRET403 ;404 ; CHECK-4BYTE-LABEL: name: non_consecutive_offsets405 ; CHECK-4BYTE: liveins: $x10406 ; CHECK-4BYTE-NEXT: {{ $}}407 ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10408 ; CHECK-4BYTE-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32))409 ; CHECK-4BYTE-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 8 :: (load (s32))410 ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]]411 ; CHECK-4BYTE-NEXT: PseudoRET412 %0:gpr = COPY $x10413 ; Should not combine - offset gap is 8, not 4414 %1:gpr = LW %0, 0 :: (load (s32))415 %2:gpr = LW %0, 8 :: (load (s32))416 %3:gpr = ADD %1, %2417 PseudoRET418 419...420---421# Different base registers - should not combine422name: different_base_regs423alignment: 4424tracksRegLiveness: true425liveins:426 - { reg: '$x10', virtual-reg: '%0' }427 - { reg: '$x11', virtual-reg: '%1' }428body: |429 bb.0:430 liveins: $x10, $x11431 432 ; CHECK-LABEL: name: different_base_regs433 ; CHECK: liveins: $x10, $x11434 ; CHECK-NEXT: {{ $}}435 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10436 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11437 ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32))438 ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY1]], 4 :: (load (s32))439 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]]440 ; CHECK-NEXT: PseudoRET441 ;442 ; CHECK-4BYTE-LABEL: name: different_base_regs443 ; CHECK-4BYTE: liveins: $x10, $x11444 ; CHECK-4BYTE-NEXT: {{ $}}445 ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10446 ; CHECK-4BYTE-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11447 ; CHECK-4BYTE-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32))448 ; CHECK-4BYTE-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY1]], 4 :: (load (s32))449 ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]]450 ; CHECK-4BYTE-NEXT: PseudoRET451 %0:gpr = COPY $x10452 %1:gpr = COPY $x11453 ; Should not combine - different base registers454 %2:gpr = LW %0, 0 :: (load (s32))455 %3:gpr = LW %1, 4 :: (load (s32))456 %4:gpr = ADD %2, %3457 PseudoRET458 459...460---461# Call instruction blocks optimization462name: call_blocks_optimization463alignment: 4464tracksRegLiveness: true465liveins:466 - { reg: '$x10', virtual-reg: '%0' }467body: |468 bb.0:469 liveins: $x10470 471 ; CHECK-LABEL: name: call_blocks_optimization472 ; CHECK: liveins: $x10473 ; CHECK-NEXT: {{ $}}474 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10475 ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32))476 ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) @external_func, csr_ilp32_lp64, implicit-def $x1477 ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32))478 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]]479 ; CHECK-NEXT: PseudoRET480 ;481 ; CHECK-4BYTE-LABEL: name: call_blocks_optimization482 ; CHECK-4BYTE: liveins: $x10483 ; CHECK-4BYTE-NEXT: {{ $}}484 ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10485 ; CHECK-4BYTE-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32))486 ; CHECK-4BYTE-NEXT: PseudoCALL target-flags(riscv-call) @external_func, csr_ilp32_lp64, implicit-def $x1487 ; CHECK-4BYTE-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32))488 ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]]489 ; CHECK-4BYTE-NEXT: PseudoRET490 %0:gpr = COPY $x10491 %1:gpr = LW %0, 0 :: (load (s32))492 ; Call instruction should block combining across it493 PseudoCALL target-flags(riscv-call) @external_func, csr_ilp32_lp64, implicit-def $x1494 %2:gpr = LW %0, 4 :: (load (s32))495 %3:gpr = ADD %1, %2496 PseudoRET497 498...499---500# Terminator instruction blocks optimization501name: terminator_blocks_optimization502alignment: 4503tracksRegLiveness: true504liveins:505 - { reg: '$x10', virtual-reg: '%0' }506 - { reg: '$x11', virtual-reg: '%1' }507body: |508 ; CHECK-LABEL: name: terminator_blocks_optimization509 ; CHECK: bb.0:510 ; CHECK-NEXT: successors: %bb.1(0x80000000)511 ; CHECK-NEXT: liveins: $x10, $x11512 ; CHECK-NEXT: {{ $}}513 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10514 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11515 ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32))516 ; CHECK-NEXT: BEQ [[COPY1]], [[LW]], %bb.1517 ; CHECK-NEXT: {{ $}}518 ; CHECK-NEXT: bb.1:519 ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32))520 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]]521 ; CHECK-NEXT: PseudoRET522 ;523 ; CHECK-4BYTE-LABEL: name: terminator_blocks_optimization524 ; CHECK-4BYTE: bb.0:525 ; CHECK-4BYTE-NEXT: successors: %bb.1(0x80000000)526 ; CHECK-4BYTE-NEXT: liveins: $x10, $x11527 ; CHECK-4BYTE-NEXT: {{ $}}528 ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10529 ; CHECK-4BYTE-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11530 ; CHECK-4BYTE-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32))531 ; CHECK-4BYTE-NEXT: BEQ [[COPY1]], [[LW]], %bb.1532 ; CHECK-4BYTE-NEXT: {{ $}}533 ; CHECK-4BYTE-NEXT: bb.1:534 ; CHECK-4BYTE-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32))535 ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]]536 ; CHECK-4BYTE-NEXT: PseudoRET537 bb.0:538 liveins: $x10, $x11539 540 %0:gpr = COPY $x10541 %1:gpr = COPY $x11542 %2:gpr = LW %0, 0 :: (load (s32))543 BEQ %1, %2, %bb.1544 545 bb.1:546 ; Should not combine across basic block boundary547 %3:gpr = LW %0, 4 :: (load (s32))548 %4:gpr = ADD %2, %3549 PseudoRET550 551...552---553# Memory aliasing - store between loads with unknown base should prevent combining554name: memory_aliasing555alignment: 4556tracksRegLiveness: true557liveins:558 - { reg: '$x10', virtual-reg: '%0' }559 - { reg: '$x11', virtual-reg: '%1' }560 - { reg: '$x12', virtual-reg: '%2' }561body: |562 bb.0:563 liveins: $x10, $x11, $x12564 565 ; CHECK-LABEL: name: memory_aliasing566 ; CHECK: liveins: $x10, $x11, $x12567 ; CHECK-NEXT: {{ $}}568 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10569 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11570 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12571 ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32))572 ; CHECK-NEXT: SW [[COPY1]], [[COPY2]], 8 :: (store (s32))573 ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32))574 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]]575 ; CHECK-NEXT: PseudoRET576 ;577 ; CHECK-4BYTE-LABEL: name: memory_aliasing578 ; CHECK-4BYTE: liveins: $x10, $x11, $x12579 ; CHECK-4BYTE-NEXT: {{ $}}580 ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10581 ; CHECK-4BYTE-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11582 ; CHECK-4BYTE-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12583 ; CHECK-4BYTE-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32))584 ; CHECK-4BYTE-NEXT: SW [[COPY1]], [[COPY2]], 8 :: (store (s32))585 ; CHECK-4BYTE-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32))586 ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]]587 ; CHECK-4BYTE-NEXT: PseudoRET588 %0:gpr = COPY $x10589 %1:gpr = COPY $x11590 %2:gpr = COPY $x12591 %3:gpr = LW %0, 0 :: (load (s32))592 SW %1, %2, 8 :: (store (s32))593 %4:gpr = LW %0, 4 :: (load (s32))594 %5:gpr = ADD %3, %4595 PseudoRET596 597...598---599# Multiple pairs in same function600name: multiple_pairs601alignment: 4602tracksRegLiveness: true603liveins:604 - { reg: '$x10', virtual-reg: '%0' }605 - { reg: '$x11', virtual-reg: '%1' }606body: |607 bb.0:608 liveins: $x10, $x11609 610 ; CHECK-LABEL: name: multiple_pairs611 ; CHECK: liveins: $x10, $x11612 ; CHECK-NEXT: {{ $}}613 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10614 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11615 ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32))616 ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32))617 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]]618 ; CHECK-NEXT: [[LW2:%[0-9]+]]:gpr = LW [[COPY1]], 8 :: (load (s32))619 ; CHECK-NEXT: [[LW3:%[0-9]+]]:gpr = LW [[COPY1]], 12 :: (load (s32))620 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[LW2]], [[LW3]]621 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD [[ADD]], [[ADD1]]622 ; CHECK-NEXT: PseudoRET623 ;624 ; CHECK-4BYTE-LABEL: name: multiple_pairs625 ; CHECK-4BYTE: liveins: $x10, $x11626 ; CHECK-4BYTE-NEXT: {{ $}}627 ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10628 ; CHECK-4BYTE-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11629 ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32))630 ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]]631 ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT2:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT3:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY1]], 8 :: (load (s32))632 ; CHECK-4BYTE-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT2]], [[PseudoLD_RV32_OPT3]]633 ; CHECK-4BYTE-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD [[ADD]], [[ADD1]]634 ; CHECK-4BYTE-NEXT: PseudoRET635 %0:gpr = COPY $x10636 %1:gpr = COPY $x11637 ; First pair should combine638 %2:gpr = LW %0, 0 :: (load (s32))639 %3:gpr = LW %0, 4 :: (load (s32))640 %4:gpr = ADD %2, %3641 642 ; Second pair should also combine643 %5:gpr = LW %1, 8 :: (load (s32))644 %6:gpr = LW %1, 12 :: (load (s32))645 %7:gpr = ADD %5, %6646 %8:gpr = ADD %4, %7647 PseudoRET648 649...650---651# Many loads test652name: many_loads653alignment: 4654tracksRegLiveness: true655liveins:656 - { reg: '$x10', virtual-reg: '%0' }657body: |658 bb.0:659 liveins: $x10660 661 ; CHECK-LABEL: name: many_loads662 ; CHECK: liveins: $x10663 ; CHECK-NEXT: {{ $}}664 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10665 ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 16 :: (load (s32))666 ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 20 :: (load (s32))667 ; CHECK-NEXT: [[LW2:%[0-9]+]]:gpr = LW [[COPY]], 24 :: (load (s32))668 ; CHECK-NEXT: [[LW3:%[0-9]+]]:gpr = LW [[COPY]], 28 :: (load (s32))669 ; CHECK-NEXT: [[LW4:%[0-9]+]]:gpr = LW [[COPY]], 32 :: (load (s32))670 ; CHECK-NEXT: [[LW5:%[0-9]+]]:gpr = LW [[COPY]], 36 :: (load (s32))671 ; CHECK-NEXT: [[LW6:%[0-9]+]]:gpr = LW [[COPY]], 40 :: (load (s32))672 ; CHECK-NEXT: [[LW7:%[0-9]+]]:gpr = LW [[COPY]], 44 :: (load (s32))673 ; CHECK-NEXT: [[LW8:%[0-9]+]]:gpr = LW [[COPY]], 48 :: (load (s32))674 ; CHECK-NEXT: [[LW9:%[0-9]+]]:gpr = LW [[COPY]], 52 :: (load (s32))675 ; CHECK-NEXT: [[LW10:%[0-9]+]]:gpr = LW [[COPY]], 56 :: (load (s32))676 ; CHECK-NEXT: [[LW11:%[0-9]+]]:gpr = LW [[COPY]], 60 :: (load (s32))677 ; CHECK-NEXT: [[LW12:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32))678 ; CHECK-NEXT: [[LW13:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32))679 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]]680 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[LW2]], [[LW3]]681 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD [[LW4]], [[LW5]]682 ; CHECK-NEXT: [[ADD3:%[0-9]+]]:gpr = ADD [[LW6]], [[LW7]]683 ; CHECK-NEXT: [[ADD4:%[0-9]+]]:gpr = ADD [[LW8]], [[LW9]]684 ; CHECK-NEXT: [[ADD5:%[0-9]+]]:gpr = ADD [[LW10]], [[LW11]]685 ; CHECK-NEXT: [[ADD6:%[0-9]+]]:gpr = ADD [[LW12]], [[LW13]]686 ; CHECK-NEXT: [[ADD7:%[0-9]+]]:gpr = ADD [[ADD]], [[ADD1]]687 ; CHECK-NEXT: [[ADD8:%[0-9]+]]:gpr = ADD [[ADD2]], [[ADD3]]688 ; CHECK-NEXT: [[ADD9:%[0-9]+]]:gpr = ADD [[ADD4]], [[ADD5]]689 ; CHECK-NEXT: [[ADD10:%[0-9]+]]:gpr = ADD [[ADD6]], [[ADD7]]690 ; CHECK-NEXT: [[ADD11:%[0-9]+]]:gpr = ADD [[ADD8]], [[ADD9]]691 ; CHECK-NEXT: [[ADD12:%[0-9]+]]:gpr = ADD [[ADD10]], [[ADD11]]692 ; CHECK-NEXT: PseudoRET693 ;694 ; CHECK-4BYTE-LABEL: name: many_loads695 ; CHECK-4BYTE: liveins: $x10696 ; CHECK-4BYTE-NEXT: {{ $}}697 ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10698 ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 16 :: (load (s32))699 ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT2:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT3:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 24 :: (load (s32))700 ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT4:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT5:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 32 :: (load (s32))701 ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT6:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT7:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 40 :: (load (s32))702 ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT8:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT9:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 48 :: (load (s32))703 ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT10:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT11:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 56 :: (load (s32))704 ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT12:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT13:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32))705 ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]]706 ; CHECK-4BYTE-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT2]], [[PseudoLD_RV32_OPT3]]707 ; CHECK-4BYTE-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT4]], [[PseudoLD_RV32_OPT5]]708 ; CHECK-4BYTE-NEXT: [[ADD3:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT6]], [[PseudoLD_RV32_OPT7]]709 ; CHECK-4BYTE-NEXT: [[ADD4:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT8]], [[PseudoLD_RV32_OPT9]]710 ; CHECK-4BYTE-NEXT: [[ADD5:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT10]], [[PseudoLD_RV32_OPT11]]711 ; CHECK-4BYTE-NEXT: [[ADD6:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT12]], [[PseudoLD_RV32_OPT13]]712 ; CHECK-4BYTE-NEXT: [[ADD7:%[0-9]+]]:gpr = ADD [[ADD]], [[ADD1]]713 ; CHECK-4BYTE-NEXT: [[ADD8:%[0-9]+]]:gpr = ADD [[ADD2]], [[ADD3]]714 ; CHECK-4BYTE-NEXT: [[ADD9:%[0-9]+]]:gpr = ADD [[ADD4]], [[ADD5]]715 ; CHECK-4BYTE-NEXT: [[ADD10:%[0-9]+]]:gpr = ADD [[ADD6]], [[ADD7]]716 ; CHECK-4BYTE-NEXT: [[ADD11:%[0-9]+]]:gpr = ADD [[ADD8]], [[ADD9]]717 ; CHECK-4BYTE-NEXT: [[ADD12:%[0-9]+]]:gpr = ADD [[ADD10]], [[ADD11]]718 ; CHECK-4BYTE-NEXT: PseudoRET719 %0:gpr = COPY $x10720 ; Create high register pressure with many live values721 %1:gpr = LW %0, 16 :: (load (s32))722 %2:gpr = LW %0, 20 :: (load (s32))723 %3:gpr = LW %0, 24 :: (load (s32))724 %4:gpr = LW %0, 28 :: (load (s32))725 %5:gpr = LW %0, 32 :: (load (s32))726 %6:gpr = LW %0, 36 :: (load (s32))727 %7:gpr = LW %0, 40 :: (load (s32))728 %8:gpr = LW %0, 44 :: (load (s32))729 %9:gpr = LW %0, 48 :: (load (s32))730 %10:gpr = LW %0, 52 :: (load (s32))731 %11:gpr = LW %0, 56 :: (load (s32))732 %12:gpr = LW %0, 60 :: (load (s32))733 734 ; With high register pressure, these loads might not be combined735 ; depending on the profitability analysis736 %13:gpr = LW %0, 0 :: (load (s32))737 %14:gpr = LW %0, 4 :: (load (s32))738 739 ; Use all the loaded values to keep them live740 %15:gpr = ADD %1, %2741 %16:gpr = ADD %3, %4742 %17:gpr = ADD %5, %6743 %18:gpr = ADD %7, %8744 %19:gpr = ADD %9, %10745 %20:gpr = ADD %11, %12746 %21:gpr = ADD %13, %14747 %22:gpr = ADD %15, %16748 %23:gpr = ADD %17, %18749 %24:gpr = ADD %19, %20750 %25:gpr = ADD %21, %22751 %26:gpr = ADD %23, %24752 %27:gpr = ADD %25, %26753 PseudoRET754 755...756---757# Test reverse order - second load has lower offset than first758name: reverse_order_loads759alignment: 4760tracksRegLiveness: true761liveins:762 - { reg: '$x10', virtual-reg: '%0' }763body: |764 bb.0:765 liveins: $x10766 767 ; CHECK-LABEL: name: reverse_order_loads768 ; CHECK: liveins: $x10769 ; CHECK-NEXT: {{ $}}770 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10771 ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32))772 ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32))773 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]]774 ; CHECK-NEXT: PseudoRET775 ;776 ; CHECK-4BYTE-LABEL: name: reverse_order_loads777 ; CHECK-4BYTE: liveins: $x10778 ; CHECK-4BYTE-NEXT: {{ $}}779 ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10780 ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32))781 ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT1]], [[PseudoLD_RV32_OPT]]782 ; CHECK-4BYTE-NEXT: PseudoRET783 %0:gpr = COPY $x10784 ; Load at higher offset first, then lower offset785 ; Should still be combined as LD with lower offset786 %1:gpr = LW %0, 4 :: (load (s32))787 %2:gpr = LW %0, 0 :: (load (s32))788 %3:gpr = ADD %1, %2789 PseudoRET790 791...792---793# Test with immediate offset calculation794name: offset_calculation795alignment: 4796tracksRegLiveness: true797liveins:798 - { reg: '$x10', virtual-reg: '%0' }799body: |800 bb.0:801 liveins: $x10802 803 ; CHECK-LABEL: name: offset_calculation804 ; CHECK: liveins: $x10805 ; CHECK-NEXT: {{ $}}806 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10807 ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 100 :: (load (s32))808 ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 104 :: (load (s32))809 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]]810 ; CHECK-NEXT: PseudoRET811 ;812 ; CHECK-4BYTE-LABEL: name: offset_calculation813 ; CHECK-4BYTE: liveins: $x10814 ; CHECK-4BYTE-NEXT: {{ $}}815 ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10816 ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 100 :: (load (s32))817 ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]]818 ; CHECK-4BYTE-NEXT: PseudoRET819 %0:gpr = COPY $x10820 ; Test with different immediate values that are consecutive821 %1:gpr = LW %0, 100 :: (load (s32))822 %2:gpr = LW %0, 104 :: (load (s32))823 %3:gpr = ADD %1, %2824 PseudoRET825 826...827---828# Test large offset values829name: large_offsets830alignment: 4831tracksRegLiveness: true832liveins:833 - { reg: '$x10', virtual-reg: '%0' }834body: |835 bb.0:836 liveins: $x10837 838 ; CHECK-LABEL: name: large_offsets839 ; CHECK: liveins: $x10840 ; CHECK-NEXT: {{ $}}841 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10842 ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 2040 :: (load (s32))843 ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 2044 :: (load (s32))844 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]]845 ; CHECK-NEXT: PseudoRET846 ;847 ; CHECK-4BYTE-LABEL: name: large_offsets848 ; CHECK-4BYTE: liveins: $x10849 ; CHECK-4BYTE-NEXT: {{ $}}850 ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10851 ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 2040 :: (load (s32))852 ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]]853 ; CHECK-4BYTE-NEXT: PseudoRET854 %0:gpr = COPY $x10855 ; Test with large offset values856 %1:gpr = LW %0, 2040 :: (load (s32))857 %2:gpr = LW %0, 2044 :: (load (s32))858 %3:gpr = ADD %1, %2859 PseudoRET860 861...862---863# Test with negative offsets864name: negative_offsets865alignment: 4866tracksRegLiveness: true867liveins:868 - { reg: '$x10', virtual-reg: '%0' }869body: |870 bb.0:871 liveins: $x10872 873 ; CHECK-LABEL: name: negative_offsets874 ; CHECK: liveins: $x10875 ; CHECK-NEXT: {{ $}}876 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10877 ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], -8 :: (load (s32))878 ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], -4 :: (load (s32))879 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]]880 ; CHECK-NEXT: PseudoRET881 ;882 ; CHECK-4BYTE-LABEL: name: negative_offsets883 ; CHECK-4BYTE: liveins: $x10884 ; CHECK-4BYTE-NEXT: {{ $}}885 ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10886 ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], -8 :: (load (s32))887 ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]]888 ; CHECK-4BYTE-NEXT: PseudoRET889 %0:gpr = COPY $x10890 ; Test with negative consecutive offsets891 %1:gpr = LW %0, -8 :: (load (s32))892 %2:gpr = LW %0, -4 :: (load (s32))893 %3:gpr = ADD %1, %2894 PseudoRET895 896...897---898# Test with volatile loads - should not combine899name: volatile_loads900alignment: 4901tracksRegLiveness: true902liveins:903 - { reg: '$x10', virtual-reg: '%0' }904body: |905 bb.0:906 liveins: $x10907 908 ; CHECK-LABEL: name: volatile_loads909 ; CHECK: liveins: $x10910 ; CHECK-NEXT: {{ $}}911 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10912 ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (volatile load (s32))913 ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (volatile load (s32))914 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]]915 ; CHECK-NEXT: PseudoRET916 ;917 ; CHECK-4BYTE-LABEL: name: volatile_loads918 ; CHECK-4BYTE: liveins: $x10919 ; CHECK-4BYTE-NEXT: {{ $}}920 ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10921 ; CHECK-4BYTE-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (volatile load (s32))922 ; CHECK-4BYTE-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (volatile load (s32))923 ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]]924 ; CHECK-4BYTE-NEXT: PseudoRET925 %0:gpr = COPY $x10926 ; Volatile loads should not be combined927 %1:gpr = LW %0, 0 :: (volatile load (s32))928 %2:gpr = LW %0, 4 :: (volatile load (s32))929 %3:gpr = ADD %1, %2930 PseudoRET931 932...933---934# Test store dependency - store modifies same location as load935name: store_dependency936alignment: 4937tracksRegLiveness: true938liveins:939 - { reg: '$x10', virtual-reg: '%0' }940 - { reg: '$x11', virtual-reg: '%1' }941body: |942 bb.0:943 liveins: $x10, $x11944 945 ; CHECK-LABEL: name: store_dependency946 ; CHECK: liveins: $x10, $x11947 ; CHECK-NEXT: {{ $}}948 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10949 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11950 ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32))951 ; CHECK-NEXT: SW [[COPY1]], [[COPY]], 4 :: (store (s32))952 ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32))953 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]]954 ; CHECK-NEXT: PseudoRET955 ;956 ; CHECK-4BYTE-LABEL: name: store_dependency957 ; CHECK-4BYTE: liveins: $x10, $x11958 ; CHECK-4BYTE-NEXT: {{ $}}959 ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10960 ; CHECK-4BYTE-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11961 ; CHECK-4BYTE-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32))962 ; CHECK-4BYTE-NEXT: SW [[COPY1]], [[COPY]], 4 :: (store (s32))963 ; CHECK-4BYTE-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32))964 ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]]965 ; CHECK-4BYTE-NEXT: PseudoRET966 %0:gpr = COPY $x10967 %1:gpr = COPY $x11968 %2:gpr = LW %0, 0 :: (load (s32))969 ; Store to same location as second load - should prevent combination970 SW %1, %0, 4 :: (store (s32))971 %3:gpr = LW %0, 4 :: (load (s32))972 %4:gpr = ADD %2, %3973 PseudoRET974 975...976---977# Test three loads:978# align 8: last two should combine979# align 4: first two should combine980name: three_loads981alignment: 4982tracksRegLiveness: true983liveins:984 - { reg: '$x10', virtual-reg: '%0' }985body: |986 bb.0:987 liveins: $x10988 989 ; CHECK-LABEL: name: three_loads990 ; CHECK: liveins: $x10991 ; CHECK-NEXT: {{ $}}992 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10993 ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32))994 ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32))995 ; CHECK-NEXT: [[LW2:%[0-9]+]]:gpr = LW [[COPY]], 8 :: (load (s32))996 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]]997 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[ADD]], [[LW2]]998 ; CHECK-NEXT: PseudoRET999 ;1000 ; CHECK-4BYTE-LABEL: name: three_loads1001 ; CHECK-4BYTE: liveins: $x101002 ; CHECK-4BYTE-NEXT: {{ $}}1003 ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x101004 ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32))1005 ; CHECK-4BYTE-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 8 :: (load (s32))1006 ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]]1007 ; CHECK-4BYTE-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[ADD]], [[LW]]1008 ; CHECK-4BYTE-NEXT: PseudoRET1009 %0:gpr = COPY $x101010 ; First two loads should combine, third should remain separate1011 %1:gpr = LW %0, 0 :: (load (s32))1012 %2:gpr = LW %0, 4 :: (load (s32))1013 %3:gpr = LW %0, 8 :: (load (s32))1014 %4:gpr = ADD %1, %21015 %5:gpr = ADD %4, %31016 PseudoRET1017...1018---1019# Test where distance between loads exceeds MaxRescheduleDistance1020name: distance_exceeds_max1021alignment: 41022tracksRegLiveness: true1023liveins:1024 - { reg: '$x10', virtual-reg: '%0' }1025 - { reg: '$x11', virtual-reg: '%1' }1026body: |1027 bb.0:1028 liveins: $x10, $x111029 1030 ; CHECK-LABEL: name: distance_exceeds_max1031 ; CHECK: liveins: $x10, $x111032 ; CHECK-NEXT: {{ $}}1033 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x101034 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x111035 ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32))1036 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[COPY1]]1037 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[ADD]], [[COPY1]]1038 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD [[ADD1]], [[COPY1]]1039 ; CHECK-NEXT: [[ADD3:%[0-9]+]]:gpr = ADD [[ADD2]], [[COPY1]]1040 ; CHECK-NEXT: [[ADD4:%[0-9]+]]:gpr = ADD [[ADD3]], [[COPY1]]1041 ; CHECK-NEXT: [[ADD5:%[0-9]+]]:gpr = ADD [[ADD4]], [[COPY1]]1042 ; CHECK-NEXT: [[ADD6:%[0-9]+]]:gpr = ADD [[ADD5]], [[COPY1]]1043 ; CHECK-NEXT: [[ADD7:%[0-9]+]]:gpr = ADD [[ADD6]], [[COPY1]]1044 ; CHECK-NEXT: [[ADD8:%[0-9]+]]:gpr = ADD [[ADD7]], [[COPY1]]1045 ; CHECK-NEXT: [[ADD9:%[0-9]+]]:gpr = ADD [[ADD8]], [[COPY1]]1046 ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32))1047 ; CHECK-NEXT: PseudoRET1048 ;1049 ; CHECK-4BYTE-LABEL: name: distance_exceeds_max1050 ; CHECK-4BYTE: liveins: $x10, $x111051 ; CHECK-4BYTE-NEXT: {{ $}}1052 ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x101053 ; CHECK-4BYTE-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x111054 ; CHECK-4BYTE-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32))1055 ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[COPY1]]1056 ; CHECK-4BYTE-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[ADD]], [[COPY1]]1057 ; CHECK-4BYTE-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD [[ADD1]], [[COPY1]]1058 ; CHECK-4BYTE-NEXT: [[ADD3:%[0-9]+]]:gpr = ADD [[ADD2]], [[COPY1]]1059 ; CHECK-4BYTE-NEXT: [[ADD4:%[0-9]+]]:gpr = ADD [[ADD3]], [[COPY1]]1060 ; CHECK-4BYTE-NEXT: [[ADD5:%[0-9]+]]:gpr = ADD [[ADD4]], [[COPY1]]1061 ; CHECK-4BYTE-NEXT: [[ADD6:%[0-9]+]]:gpr = ADD [[ADD5]], [[COPY1]]1062 ; CHECK-4BYTE-NEXT: [[ADD7:%[0-9]+]]:gpr = ADD [[ADD6]], [[COPY1]]1063 ; CHECK-4BYTE-NEXT: [[ADD8:%[0-9]+]]:gpr = ADD [[ADD7]], [[COPY1]]1064 ; CHECK-4BYTE-NEXT: [[ADD9:%[0-9]+]]:gpr = ADD [[ADD8]], [[COPY1]]1065 ; CHECK-4BYTE-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32))1066 ; CHECK-4BYTE-NEXT: PseudoRET1067 %0:gpr = COPY $x101068 %1:gpr = COPY $x111069 %2:gpr = LW %0, 0 :: (load (s32))1070 ; Insert 11 instructions between the two loads1071 ; This makes the distance greater than the configured MaxRescheduleDistance1072 %3:gpr = ADD %2, %11073 %4:gpr = ADD %3, %11074 %5:gpr = ADD %4, %11075 %6:gpr = ADD %5, %11076 %7:gpr = ADD %6, %11077 %8:gpr = ADD %7, %11078 %9:gpr = ADD %8, %11079 %10:gpr = ADD %9, %11080 %11:gpr = ADD %10, %11081 %12:gpr = ADD %11, %11082 ; Second load at offset 4 - too far from first load1083 %14:gpr = LW %0, 4 :: (load (s32))1084 PseudoRET1085...1086---1087# Test combining loads with symbolic operands (global address)1088name: symbolic_operands_global1089alignment: 41090tracksRegLiveness: true1091liveins:1092 - { reg: '$x10', virtual-reg: '%0' }1093body: |1094 bb.0:1095 liveins: $x101096 1097 ; CHECK-LABEL: name: symbolic_operands_global1098 ; CHECK: liveins: $x101099 ; CHECK-NEXT: {{ $}}1100 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x101101 ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], target-flags(riscv-lo) @global_var :: (load (s32))1102 ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], target-flags(riscv-lo) @global_var + 4 :: (load (s32))1103 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]]1104 ; CHECK-NEXT: PseudoRET1105 ;1106 ; CHECK-4BYTE-LABEL: name: symbolic_operands_global1107 ; CHECK-4BYTE: liveins: $x101108 ; CHECK-4BYTE-NEXT: {{ $}}1109 ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x101110 ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], target-flags(riscv-lo) @global_var :: (load (s32))1111 ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]]1112 ; CHECK-4BYTE-NEXT: PseudoRET1113 %0:gpr = COPY $x101114 ; Two consecutive loads with symbolic global address operands1115 %1:gpr = LW %0, target-flags(riscv-lo) @global_var :: (load (s32))1116 %2:gpr = LW %0, target-flags(riscv-lo) @global_var + 4 :: (load (s32))1117 %3:gpr = ADD %1, %21118 PseudoRET1119 1120...1121---1122# Test that loads with different global symbols are not combined1123name: symbolic_operands_different_globals1124alignment: 41125tracksRegLiveness: true1126liveins:1127 - { reg: '$x10', virtual-reg: '%0' }1128stack:1129 - { id: 0, offset: -4, size: 4 }1130body: |1131 bb.0:1132 liveins: $x101133 1134 ; CHECK-LABEL: name: symbolic_operands_different_globals1135 ; CHECK: liveins: $x101136 ; CHECK-NEXT: {{ $}}1137 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x101138 ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], target-flags(riscv-lo) @global_var :: (load (s32))1139 ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], %stack.0 :: (load (s32))1140 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]]1141 ; CHECK-NEXT: PseudoRET1142 ;1143 ; CHECK-4BYTE-LABEL: name: symbolic_operands_different_globals1144 ; CHECK-4BYTE: liveins: $x101145 ; CHECK-4BYTE-NEXT: {{ $}}1146 ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x101147 ; CHECK-4BYTE-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], target-flags(riscv-lo) @global_var :: (load (s32))1148 ; CHECK-4BYTE-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], %stack.0 :: (load (s32))1149 ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]]1150 ; CHECK-4BYTE-NEXT: PseudoRET1151 %0:gpr = COPY $x101152 ; Should not combine - different symbol types1153 %1:gpr = LW %0, target-flags(riscv-lo) @global_var :: (load (s32))1154 %2:gpr = LW %0, %stack.0 :: (load (s32))1155 %3:gpr = ADD %1, %21156 PseudoRET1157 1158...1159---1160# Test combining loads with constant pool operands1161name: symbolic_operands_constantpool1162alignment: 41163tracksRegLiveness: true1164liveins:1165 - { reg: '$x10', virtual-reg: '%0' }1166constants:1167 - id: 01168 value: 'double 3.140000e+00'1169 alignment: 81170body: |1171 bb.0:1172 liveins: $x101173 1174 ; CHECK-LABEL: name: symbolic_operands_constantpool1175 ; CHECK: liveins: $x101176 ; CHECK-NEXT: {{ $}}1177 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x101178 ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], target-flags(riscv-lo) %const.0 :: (load (s32))1179 ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], target-flags(riscv-lo) %const.0 + 4 :: (load (s32))1180 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]]1181 ; CHECK-NEXT: PseudoRET1182 ;1183 ; CHECK-4BYTE-LABEL: name: symbolic_operands_constantpool1184 ; CHECK-4BYTE: liveins: $x101185 ; CHECK-4BYTE-NEXT: {{ $}}1186 ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x101187 ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], target-flags(riscv-lo) %const.0 :: (load (s32))1188 ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]]1189 ; CHECK-4BYTE-NEXT: PseudoRET1190 %0:gpr = COPY $x101191 ; Two consecutive loads with constant pool operands1192 %1:gpr = LW %0, target-flags(riscv-lo) %const.0 :: (load (s32))1193 %2:gpr = LW %0, target-flags(riscv-lo) %const.0 + 4 :: (load (s32))1194 %3:gpr = ADD %1, %21195 PseudoRET1196 1197...1198---1199name: symbolic_operands_interleave1200alignment: 41201tracksRegLiveness: true1202liveins:1203 - { reg: '$x10', virtual-reg: '%0' }1204 - { reg: '$x11', virtual-reg: '%1' }1205body: |1206 bb.0:1207 liveins: $x10, $x111208 1209 ; CHECK-LABEL: name: symbolic_operands_interleave1210 ; CHECK: liveins: $x10, $x111211 ; CHECK-NEXT: {{ $}}1212 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x101213 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x111214 ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], target-flags(riscv-lo) @global_var :: (load (s32))1215 ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32))1216 ; CHECK-NEXT: [[LW2:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32))1217 ; CHECK-NEXT: [[LW3:%[0-9]+]]:gpr = LW [[COPY]], target-flags(riscv-lo) @global_var + 4 :: (load (s32))1218 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW2]]1219 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[LW1]], [[LW3]]1220 ; CHECK-NEXT: PseudoRET1221 ;1222 ; CHECK-4BYTE-LABEL: name: symbolic_operands_interleave1223 ; CHECK-4BYTE: liveins: $x10, $x111224 ; CHECK-4BYTE-NEXT: {{ $}}1225 ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x101226 ; CHECK-4BYTE-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x111227 ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], target-flags(riscv-lo) @global_var :: (load (s32))1228 ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT2:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT3:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32))1229 ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT2]]1230 ; CHECK-4BYTE-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT3]], [[PseudoLD_RV32_OPT1]]1231 ; CHECK-4BYTE-NEXT: PseudoRET1232 %0:gpr = COPY $x101233 %1:gpr = COPY $x111234 %2:gpr = LW %0, target-flags(riscv-lo) @global_var :: (load (s32))1235 %3:gpr = LW %0, 4 :: (load (s32))1236 %4:gpr = LW %0, 0 :: (load (s32))1237 %5:gpr = LW %0, target-flags(riscv-lo) @global_var + 4 :: (load (s32))1238 %6:gpr = ADD %2, %41239 %7:gpr = ADD %3, %51240 PseudoRET1241 1242...1243