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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple=riscv32 -mattr=+zilsd -run-pass=greedy,virtregrewriter %s -o - | FileCheck --check-prefix=WITHOUT-HINT %s3# RUN: llc -mtriple=riscv32 -mattr=+zilsd,+zilsd-4byte-align -run-pass=riscv-prera-zilsd-opt,greedy,virtregrewriter %s -o - | FileCheck --check-prefix=WITH-HINT %s4 5--- |6 define i32 @test_load_pair_hints(ptr %p) {7 %v1 = load i32, ptr %p, align 48 %p2 = getelementptr inbounds i8, ptr %p, i32 49 %v2 = load i32, ptr %p2, align 410 %sum = add i32 %v1, %v211 ret i32 %sum12 }13 14 define void @test_store_pair_hints(ptr %p, i32 %a, i32 %b) {15 store i32 %a, ptr %p, align 416 %p2 = getelementptr inbounds i8, ptr %p, i32 417 store i32 %b, ptr %p2, align 418 ret void19 }20...21---22# Test that load pairs get register hints and allocate consecutive registers23# After register allocation, should either keep LD_RV32 or split back to LW24name: test_load_pair_hints25tracksRegLiveness: true26body: |27 bb.0:28 liveins: $x1029 30 ; WITHOUT-HINT-LABEL: name: test_load_pair_hints31 ; WITHOUT-HINT: liveins: $x1032 ; WITHOUT-HINT-NEXT: {{ $}}33 ; WITHOUT-HINT-NEXT: renamable $x11 = LW renamable $x10, 0 :: (load (s32) from %ir.p)34 ; WITHOUT-HINT-NEXT: renamable $x10 = LW killed renamable $x10, 4 :: (load (s32) from %ir.p2)35 ; WITHOUT-HINT-NEXT: renamable $x10 = ADD killed renamable $x11, killed renamable $x1036 ; WITHOUT-HINT-NEXT: PseudoRET implicit $x1037 ;38 ; WITH-HINT-LABEL: name: test_load_pair_hints39 ; WITH-HINT: liveins: $x1040 ; WITH-HINT-NEXT: {{ $}}41 ; WITH-HINT-NEXT: renamable $x10, renamable $x11 = PseudoLD_RV32_OPT killed renamable $x10, 0 :: (load (s32) from %ir.p), (load (s32) from %ir.p2)42 ; WITH-HINT-NEXT: renamable $x10 = ADD killed renamable $x10, killed renamable $x1143 ; WITH-HINT-NEXT: PseudoRET implicit $x1044 %10:gpr = COPY $x1045 ; These two LW instructions at offset 0 and 4 should be combined46 %0:gpr = LW %10, 0 :: (load (s32) from %ir.p)47 %1:gpr = LW %10, 4 :: (load (s32) from %ir.p2)48 %2:gpr = ADD %0, %149 $x10 = COPY %250 PseudoRET implicit $x1051 52...53---54# Test that store pairs get register hints and allocate consecutive registers55# After register allocation, should either keep SD_RV32 or split back to SW56name: test_store_pair_hints57tracksRegLiveness: true58body: |59 bb.0:60 liveins: $x10, $x11, $x1261 62 ; WITHOUT-HINT-LABEL: name: test_store_pair_hints63 ; WITHOUT-HINT: liveins: $x10, $x11, $x1264 ; WITHOUT-HINT-NEXT: {{ $}}65 ; WITHOUT-HINT-NEXT: SW killed renamable $x11, renamable $x10, 0 :: (store (s32) into %ir.p)66 ; WITHOUT-HINT-NEXT: SW killed renamable $x12, killed renamable $x10, 4 :: (store (s32) into %ir.p2)67 ; WITHOUT-HINT-NEXT: PseudoRET68 ;69 ; WITH-HINT-LABEL: name: test_store_pair_hints70 ; WITH-HINT: liveins: $x10, $x11, $x1271 ; WITH-HINT-NEXT: {{ $}}72 ; WITH-HINT-NEXT: renamable $x14 = COPY $x1173 ; WITH-HINT-NEXT: renamable $x15 = COPY $x1274 ; WITH-HINT-NEXT: PseudoSD_RV32_OPT killed renamable $x14, killed renamable $x15, killed renamable $x10, 0 :: (store (s32) into %ir.p), (store (s32) into %ir.p2)75 ; WITH-HINT-NEXT: PseudoRET76 %10:gpr = COPY $x1077 %11:gpr = COPY $x1178 %12:gpr = COPY $x1279 ; These two SW instructions at offset 0 and 4 should be combined80 SW %11, %10, 0 :: (store (s32) into %ir.p)81 SW %12, %10, 4 :: (store (s32) into %ir.p2)82 PseudoRET83...84