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1; RUN: llc -mtriple=riscv32 -mattr=+zmmul -verify-machineinstrs < %s \2; RUN: | not FileCheck -check-prefix=CHECK-DIV %s3; RUN: llc -mtriple=riscv64 -mattr=+zmmul -verify-machineinstrs < %s \4; RUN: | not FileCheck -check-prefix=CHECK-DIV %s5; RUN: llc -mtriple=riscv32 -mattr=+zmmul -verify-machineinstrs < %s \6; RUN: | not FileCheck -check-prefix=CHECK-REM %s7; RUN: llc -mtriple=riscv64 -mattr=+zmmul -verify-machineinstrs < %s \8; RUN: | not FileCheck -check-prefix=CHECK-REM %s9 10; RUN: llc -mtriple=riscv32 -mattr=+zmmul -verify-machineinstrs < %s \11; RUN: | not FileCheck -check-prefix=CHECK-UDIV %s12; RUN: llc -mtriple=riscv64 -mattr=+zmmul -verify-machineinstrs < %s \13; RUN: | not FileCheck -check-prefix=CHECK-UDIV %s14; RUN: llc -mtriple=riscv32 -mattr=+zmmul -verify-machineinstrs < %s \15; RUN: | not FileCheck -check-prefix=CHECK-UREM %s16; RUN: llc -mtriple=riscv64 -mattr=+zmmul -verify-machineinstrs < %s \17; RUN: | not FileCheck -check-prefix=CHECK-UREM %s18 19; RUN: llc -mtriple=riscv32 -mattr=+zmmul -verify-machineinstrs < %s \20; RUN: | FileCheck -check-prefix=CHECK-MUL %s21; RUN: llc -mtriple=riscv64 -mattr=+zmmul -verify-machineinstrs < %s \22; RUN: | FileCheck -check-prefix=CHECK-MUL %s23 24; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \25; RUN: | FileCheck -check-prefixes=CHECK-MUL,CHECK-UDIV,CHECK-DIV,CHECK-UREM,CHECK-REM %s26; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \27; RUN: | FileCheck -check-prefixes=CHECK-MUL,CHECK-UDIV,CHECK-DIV,CHECK-UREM,CHECK-REM %s28 29define i32 @foo(i32 %a, i32 %b) {30; CHECK-UDIV: divu{{w?}} {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}31 %1 = udiv i32 %a, %b32; CHECK-DIV: div{{w?}} {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}33 %2 = sdiv i32 %a, %134; CHECK-MUL: mul{{w?}} {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}35 %3 = mul i32 %b, %236; CHECK-UREM: remu{{w?}} {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}37 %4 = urem i32 %3, %b38; CHECK-REM: rem{{w?}} {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}39 %5 = srem i32 %4, %a40 ret i32 %541}42