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1; RUN: llc < %s -mtriple=sparcv9 -disable-sparc-delay-filler -disable-sparc-leaf-proc | FileCheck %s --check-prefix=CHECK --check-prefix=HARD2; RUN: llc < %s -mtriple=sparcv9 -disable-sparc-delay-filler -disable-sparc-leaf-proc -mattr=soft-float | FileCheck %s --check-prefix=CHECK --check-prefix=SOFT3 4; CHECK-LABEL: intarg:5; The save/restore frame is not strictly necessary here, but we would need to6; refer to %o registers instead.7; CHECK: save %sp, -128, %sp8; CHECK: ldx [%fp+2231], [[R2:%[gilo][0-7]]]9; CHECK: ld [%fp+2227], [[R1:%[gilo][0-7]]]10; CHECK: stb %i0, [%i4]11; CHECK: stb %i1, [%i4]12; CHECK: sth %i2, [%i4]13; CHECK: st %i3, [%i4]14; CHECK: stx %i4, [%i4]15; CHECK: st %i5, [%i4]16; CHECK: st [[R1]], [%i4]17; CHECK: stx [[R2]], [%i4]18; CHECK: restore19define void @intarg(i8 %a0, ; %i020 i8 %a1, ; %i121 i16 %a2, ; %i222 i32 %a3, ; %i323 ptr %a4, ; %i424 i32 %a5, ; %i525 i32 signext %a6, ; [%fp+BIAS+176]26 ptr %a7) { ; [%fp+BIAS+184]27 store volatile i8 %a0, ptr %a428 store volatile i8 %a1, ptr %a429 %p16 = bitcast ptr %a4 to ptr30 store volatile i16 %a2, ptr %p1631 %p32 = bitcast ptr %a4 to ptr32 store volatile i32 %a3, ptr %p3233 %pp = bitcast ptr %a4 to ptr34 store volatile ptr %a4, ptr %pp35 store volatile i32 %a5, ptr %p3236 store volatile i32 %a6, ptr %p3237 store volatile ptr %a7, ptr %pp38 ret void39}40 41; CHECK-LABEL: call_intarg:42; 16 saved + 8 args.43; CHECK: save %sp, -192, %sp44; Sign-extend and store the full 64 bits.45; CHECK: sra %i0, 0, [[R:%[gilo][0-7]]]46; Use %o0-%o5 for outgoing arguments47; CHECK: mov 5, %o548; CHECK: stx [[R]], [%sp+2223]49; CHECK: call intarg50; CHECK-NOT: add %sp51; CHECK: restore52define void @call_intarg(i32 %i0, ptr %i1) {53 call void @intarg(i8 0, i8 1, i16 2, i32 3, ptr undef, i32 5, i32 signext %i0, ptr %i1)54 ret void55}56 57; CHECK-LABEL: floatarg:58; HARD: save %sp, -128, %sp59; HARD: ld [%fp+2307], [[F:%f[0-9]+]]60; HARD: fstod %f1,61; HARD: faddd %f2,62; HARD: faddd %f4,63; HARD: faddd %f6,64; HARD: fadds %f31, [[F]]65; SOFT: save %sp, -176, %sp66; SOFT: ld [%fp+2299], %i467; SOFT: ld [%fp+2307], %i568; SOFT: srl %i0, 0, %o069; SOFT-NEXT: call __extendsfdf270; SOFT: mov %o0, %o171; SOFT: mov %i1, %o072; SOFT: mov %i2, %o073; SOFT: mov %i3, %o074define double @floatarg(float %a0, ; %f175 double %a1, ; %d276 double %a2, ; %d477 double %a3, ; %d678 float %a4, ; %f979 float %a5, ; %f1180 float %a6, ; %f1381 float %a7, ; %f1582 float %a8, ; %f1783 float %a9, ; %f1984 float %a10, ; %f2185 float %a11, ; %f2386 float %a12, ; %f2587 float %a13, ; %f2788 float %a14, ; %f2989 float %a15, ; %f3190 float %a16, ; [%fp+BIAS+256] (using 8 bytes)91 double %a17) { ; [%fp+BIAS+264] (using 8 bytes)92 %d0 = fpext float %a0 to double93 %s1 = fadd double %a1, %d094 %s2 = fadd double %a2, %s195 %s3 = fadd double %a3, %s296 %s16 = fadd float %a15, %a1697 %d16 = fpext float %s16 to double98 %s17 = fadd double %d16, %s399 ret double %s17100}101 102; CHECK-LABEL: call_floatarg:103; CHECK: save %sp, -272, %sp104; Store 8 bytes in full slot.105; HARD: std %f2, [%sp+2311]106; Store 4 bytes, right-aligned in slot.107; HARD: st %f1, [%sp+2307]108; HARD: fmovd %f2, %f4109; SOFT: stx %i1, [%sp+2311]110; SOFT: stx %i0, [%sp+2303]111; SOFT: stx %i2, [%sp+2295]112; SOFT: stx %i2, [%sp+2287]113; SOFT: stx %i2, [%sp+2279]114; SOFT: stx %i2, [%sp+2271]115; SOFT: stx %i2, [%sp+2263]116; SOFT: stx %i2, [%sp+2255]117; SOFT: stx %i2, [%sp+2247]118; SOFT: stx %i2, [%sp+2239]119; SOFT: stx %i2, [%sp+2231]120; SOFT: stx %i2, [%sp+2223]121; SOFT: mov %i1, %o2122; SOFT: mov %i1, %o3123; SOFT: mov %i2, %o4124; SOFT: mov %i2, %o5125; CHECK: call floatarg126; CHECK-NOT: add %sp127; CHECK: restore128 129define void @call_floatarg(float %f1, double %d2, float %f5, ptr %p) {130 %r = call double @floatarg(float %f5, double %d2, double %d2, double %d2,131 float %f5, float %f5, float %f5, float %f5,132 float %f5, float %f5, float %f5, float %f5,133 float %f5, float %f5, float %f5, float %f5,134 float %f1, double %d2)135 store double %r, ptr %p136 ret void137}138 139; CHECK-LABEL: mixedarg:140; CHECK: ldx [%fp+2247]141; CHECK: ldx [%fp+2231]142; SOFT: ldx [%fp+2239], %i0143; HARD: fstod %f3144; HARD: faddd %f6145; HARD: faddd %f16146; SOFT: mov %o0, %o1147; SOFT-NEXT: mov %i3, %o0148; SOFT-NEXT: call __adddf3149; SOFT: mov %o0, %o1150; SOFT-NEXT: mov %i0, %o0151; SOFT-NEXT: call __adddf3152; HARD: std %f0, [%i1]153; SOFT: stx %o0, [%i5]154 155define void @mixedarg(i8 %a0, ; %i0156 float %a1, ; %f3157 i16 %a2, ; %i2158 double %a3, ; %d6159 i13 %a4, ; %i4160 float %a5, ; %f11161 i64 %a6, ; [%fp+BIAS+176]162 ptr %a7, ; [%fp+BIAS+184]163 double %a8, ; %d16164 ptr %a9) { ; [%fp+BIAS+200]165 %d1 = fpext float %a1 to double166 %s3 = fadd double %a3, %d1167 %s8 = fadd double %a8, %s3168 store double %s8, ptr %a7169 store i16 %a2, ptr %a9170 ret void171}172 173; CHECK-LABEL: call_mixedarg:174; CHECK: stx %i2, [%sp+2247]175; CHECK: stx %i0, [%sp+2223]176; HARD: fmovd %f2, %f6177; HARD: fmovd %f2, %f16178; CHECK: call mixedarg179; CHECK-NOT: add %sp180; CHECK: restore181 182define void @call_mixedarg(i64 %i0, double %f2, ptr %i2) {183 call void @mixedarg(i8 undef,184 float undef,185 i16 undef,186 double %f2,187 i13 undef,188 float undef,189 i64 %i0,190 ptr undef,191 double %f2,192 ptr %i2)193 ret void194}195 196; The inreg attribute is used to indicate 32-bit sized struct elements that197; share an 8-byte slot.198; CHECK-LABEL: inreg_fi:199; SOFT: srlx %i0, 32, [[R:%[gilo][0-7]]]200; HARD: fstoi %f1201; SOFT: call __fixsfsi202; HARD: srlx %i0, 32, [[R:%[gilo][0-7]]]203; CHECK: sub [[R]],204define i32 @inreg_fi(i32 inreg %a0, ; high bits of %i0205 float inreg %a1) { ; %f1206 %b1 = fptosi float %a1 to i32207 %rv = sub i32 %a0, %b1208 ret i32 %rv209}210 211; CHECK-LABEL: call_inreg_fi:212; Allocate space for 6 arguments, even when only 2 are used.213; CHECK: save %sp, -176, %sp214; HARD-DAG: sllx %i1, 32, %o0215; HARD-DAG: fmovs %f5, %f1216; SOFT: srl %i2, 0, %i0217; SOFT: sllx %i1, 32, %i1218; SOFT: or %i1, %i0, %o0219; CHECK: call inreg_fi220define void @call_inreg_fi(ptr %p, i32 %i1, float %f5) {221 %x = call i32 @inreg_fi(i32 inreg %i1, float inreg %f5)222 ret void223}224 225; CHECK-LABEL: inreg_ff:226; HARD: fsubs %f0, %f1, %f0227; SOFT: srlx %i0, 32, %o0228; SOFT: srl %i0, 0, %o1229; SOFT: call __subsf3230define float @inreg_ff(float inreg %a0, ; %f0231 float inreg %a1) { ; %f1232 %rv = fsub float %a0, %a1233 ret float %rv234}235 236; CHECK-LABEL: call_inreg_ff:237; HARD-DAG: fmovs %f3, %f0238; HARD-DAG: fmovs %f5, %f1239; SOFT: srl %i2, 0, %i0240; SOFT: sllx %i1, 32, %i1241; SOFT: or %i1, %i0, %o0242; CHECK: call inreg_ff243define void @call_inreg_ff(ptr %p, float %f3, float %f5) {244 %x = call float @inreg_ff(float inreg %f3, float inreg %f5)245 ret void246}247 248; CHECK-LABEL: inreg_if:249; HARD: fstoi %f0250; SOFT: srlx %i0, 32, %o0251; SOFT: call __fixsfsi252; CHECK: sub %i0253define i32 @inreg_if(float inreg %a0, ; %f0254 i32 inreg %a1) { ; low bits of %i0255 %b0 = fptosi float %a0 to i32256 %rv = sub i32 %a1, %b0257 ret i32 %rv258}259 260; CHECK-LABEL: call_inreg_if:261; HARD: mov %i2, %o0262; HARD: fmovs %f3, %f0263; SOFT: srl %i2, 0, %i0264; SOFT: sllx %i1, 32, %i1265; SOFT: or %i1, %i0, %o0266; CHECK: call inreg_if267define void @call_inreg_if(ptr %p, float %f3, i32 %i2) {268 %x = call i32 @inreg_if(float inreg %f3, i32 inreg %i2)269 ret void270}271 272; The frontend shouldn't do this. Just pass i64 instead.273; CHECK-LABEL: inreg_ii:274; CHECK: srlx %i0, 32, [[R:%[gilo][0-7]]]275; CHECK: sub %i0, [[R]], %i0276define i32 @inreg_ii(i32 inreg %a0, ; high bits of %i0277 i32 inreg %a1) { ; low bits of %i0278 %rv = sub i32 %a1, %a0279 ret i32 %rv280}281 282; CHECK-LABEL: call_inreg_ii:283; CHECK: srl %i2, 0, [[R2:%[gilo][0-7]]]284; CHECK: sllx %i1, 32, [[R1:%[gilo][0-7]]]285; CHECK: or [[R1]], [[R2]], %o0286; CHECK: call inreg_ii287define void @call_inreg_ii(ptr %p, i32 %i1, i32 %i2) {288 %x = call i32 @inreg_ii(i32 inreg %i1, i32 inreg %i2)289 ret void290}291 292; This is not a C struct, the i32 member uses 8 bytes, but the float only 4.293; CHECK-LABEL: ret_i32_float_pair:294; CHECK: ld [%i2], %i0295; HARD: ld [%i3], %f2296; SOFT: ld [%i3], %i1297define { i32, float } @ret_i32_float_pair(i32 %a0, i32 %a1,298 ptr %p, ptr %q) {299 %r1 = load i32, ptr %p300 %rv1 = insertvalue { i32, float } undef, i32 %r1, 0301 store i32 0, ptr %p302 %r2 = load float, ptr %q303 %rv2 = insertvalue { i32, float } %rv1, float %r2, 1304 ret { i32, float } %rv2305}306 307; CHECK-LABEL: call_ret_i32_float_pair:308; CHECK: call ret_i32_float_pair309; CHECK: st %o0, [%i0]310; HARD: st %f2, [%i1]311; SOFT: st %o1, [%i1]312define void @call_ret_i32_float_pair(ptr %i0, ptr %i1) {313 %rv = call { i32, float } @ret_i32_float_pair(i32 undef, i32 undef,314 ptr undef, ptr undef)315 %e0 = extractvalue { i32, float } %rv, 0316 store i32 %e0, ptr %i0317 %e1 = extractvalue { i32, float } %rv, 1318 store float %e1, ptr %i1319 ret void320}321 322; This is a C struct, each member uses 4 bytes.323; CHECK-LABEL: ret_i32_float_packed:324; CHECK: ld [%i2], [[R:%[gilo][0-7]]]325; HARD: ld [%i3], %f1326; SOFT: ld [%i3], %i1327; CHECK: sllx [[R]], 32, %i0328define inreg { i32, float } @ret_i32_float_packed(i32 %a0, i32 %a1,329 ptr %p, ptr %q) {330 %r1 = load i32, ptr %p331 %rv1 = insertvalue { i32, float } undef, i32 %r1, 0332 store i32 0, ptr %p333 %r2 = load float, ptr %q334 %rv2 = insertvalue { i32, float } %rv1, float %r2, 1335 ret { i32, float } %rv2336}337 338; CHECK-LABEL: call_ret_i32_float_packed:339; CHECK: call ret_i32_float_packed340; CHECK: srlx %o0, 32, [[R:%[gilo][0-7]]]341; CHECK: st [[R]], [%i0]342; HARD: st %f1, [%i1]343; SOFT: st %o0, [%i1]344define void @call_ret_i32_float_packed(ptr %i0, ptr %i1) {345 %rv = call { i32, float } @ret_i32_float_packed(i32 undef, i32 undef,346 ptr undef, ptr undef)347 %e0 = extractvalue { i32, float } %rv, 0348 store i32 %e0, ptr %i0349 %e1 = extractvalue { i32, float } %rv, 1350 store float %e1, ptr %i1351 ret void352}353 354; The C frontend should use i64 to return { i32, i32 } structs, but verify that355; we don't miscompile thi case where both struct elements are placed in %i0.356; CHECK-LABEL: ret_i32_packed:357; CHECK: ld [%i2], [[R1:%[gilo][0-7]]]358; CHECK: ld [%i3], [[R2:%[gilo][0-7]]]359; CHECK: sllx [[R2]], 32, [[R3:%[gilo][0-7]]]360; CHECK: or [[R3]], [[R1]], %i0361define inreg { i32, i32 } @ret_i32_packed(i32 %a0, i32 %a1,362 ptr %p, ptr %q) {363 %r1 = load i32, ptr %p364 %rv1 = insertvalue { i32, i32 } undef, i32 %r1, 1365 store i32 0, ptr %p366 %r2 = load i32, ptr %q367 %rv2 = insertvalue { i32, i32 } %rv1, i32 %r2, 0368 ret { i32, i32 } %rv2369}370 371; CHECK-LABEL: call_ret_i32_packed:372; CHECK: call ret_i32_packed373; CHECK: srlx %o0, 32, [[R:%[gilo][0-7]]]374; CHECK: st [[R]], [%i0]375; CHECK: st %o0, [%i1]376define void @call_ret_i32_packed(ptr %i0, ptr %i1) {377 %rv = call { i32, i32 } @ret_i32_packed(i32 undef, i32 undef,378 ptr undef, ptr undef)379 %e0 = extractvalue { i32, i32 } %rv, 0380 store i32 %e0, ptr %i0381 %e1 = extractvalue { i32, i32 } %rv, 1382 store i32 %e1, ptr %i1383 ret void384}385 386; The return value must be sign-extended to 64 bits.387; CHECK-LABEL: ret_sext:388; CHECK: sra %i0, 0, %i0389define signext i32 @ret_sext(i32 %a0) {390 ret i32 %a0391}392 393; CHECK-LABEL: ret_zext:394; CHECK: srl %i0, 0, %i0395define zeroext i32 @ret_zext(i32 %a0) {396 ret i32 %a0397}398 399; CHECK-LABEL: ret_nosext:400; CHECK-NOT: sra401define signext i32 @ret_nosext(i32 signext %a0) {402 ret i32 %a0403}404 405; CHECK-LABEL: ret_nozext:406; CHECK-NOT: srl407define signext i32 @ret_nozext(i32 signext %a0) {408 ret i32 %a0409}410 411; CHECK-LABEL: test_register_directive:412; CHECK: .register %g2, #scratch413; CHECK: .register %g3, #scratch414; CHECK: add %i0, 2, %g2415; CHECK: add %i0, 3, %g3416define i32 @test_register_directive(i32 %i0) {417entry:418 %0 = add nsw i32 %i0, 2419 %1 = add nsw i32 %i0, 3420 tail call void asm sideeffect "", "r,r,~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6},~{o7},~{g1},~{g4},~{g5},~{g6},~{g7}"(i32 %0, i32 %1)421 %2 = add nsw i32 %0, %1422 ret i32 %2423}424 425; CHECK-LABEL: test_large_stack:426 427; CHECK: sethi 16, %g1428; CHECK: xor %g1, -176, %g1429; CHECK: save %sp, %g1, %sp430 431; CHECK: sethi 14, %g1432; CHECK: xor %g1, -1, %g1433; CHECK: add %g1, %fp, %g1434; CHECK: call use_buf435 436define i32 @test_large_stack() {437entry:438 %buffer1 = alloca [16384 x i8], align 8439 %buffer1.sub = getelementptr inbounds [16384 x i8], ptr %buffer1, i32 0, i32 0440 %0 = call i32 @use_buf(i32 16384, ptr %buffer1.sub)441 ret i32 %0442}443 444declare i32 @use_buf(i32, ptr)445 446; CHECK-LABEL: test_fp128_args:447; HARD-DAG: std %f0, [%fp+{{.+}}]448; HARD-DAG: std %f2, [%fp+{{.+}}]449; HARD-DAG: std %f6, [%fp+{{.+}}]450; HARD-DAG: std %f4, [%fp+{{.+}}]451; HARD: add %fp, [[Offset:[0-9]+]], %o0452; HARD: call _Qp_add453; HARD: ldd [%fp+[[Offset]]], %f0454; SOFT-DAG: mov %i0, %o0455; SOFT-DAG: mov %i1, %o1456; SOFT-DAG: mov %i2, %o2457; SOFT-DAG: mov %i3, %o3458; SOFT: call __addtf3459; SOFT: mov %o0, %i0460; SOFT: mov %o1, %i1461 462define fp128 @test_fp128_args(fp128 %a, fp128 %b) {463entry:464 %0 = fadd fp128 %a, %b465 ret fp128 %0466}467 468declare i64 @receive_fp128(i64 %a, ...)469 470; CHECK-LABEL: test_fp128_variable_args:471; HARD-DAG: std %f4, [%sp+[[Offset0:[0-9]+]]]472; HARD-DAG: std %f6, [%sp+[[Offset1:[0-9]+]]]473; HARD-DAG: ldx [%sp+[[Offset0]]], %o2474; HARD-DAG: ldx [%sp+[[Offset1]]], %o3475; SOFT-DAG: mov %i0, %o0476; SOFT-DAG: mov %i2, %o2477; SOFT-DAG: mov %i3, %o3478; CHECK: call receive_fp128479define i64 @test_fp128_variable_args(i64 %a, fp128 %b) {480entry:481 %0 = call i64 (i64, ...) @receive_fp128(i64 %a, fp128 %b)482 ret i64 %0483}484 485declare i64 @receive_i128(i64 %a, i128 %b)486 487; CHECK-LABEL: test_i128_args:488; CHECK: mov %i3, %o3489; CHECK: mov %i2, %o2490; CHECK: mov %i0, %o0491; CHECK: call receive_i128492define i64 @test_i128_args(i64 %a, i128 %b) {493entry:494 %0 = call i64 @receive_i128(i64 %a, i128 %b)495 ret i64 %0496}497 498; CHECK-LABEL: test_call_libfunc:499; HARD: st %f1, [%fp+[[Offset0:[0-9]+]]]500; HARD: fmovs %f3, %f1501; SOFT: srl %i1, 0, %o0502; CHECK: call cosf503; HARD: st %f0, [%fp+[[Offset1:[0-9]+]]]504; HARD: ld [%fp+[[Offset0]]], %f1505; SOFT: mov %o0, %i1506; SOFT: srl %i0, 0, %o0507; CHECK: call sinf508; HARD: ld [%fp+[[Offset1]]], %f1509; HARD: fmuls %f1, %f0, %f0510; SOFT: mov %o0, %o1511; SOFT: mov %i1, %o0512; SOFT: call __mulsf3513; SOFT: sllx %o0, 32, %i0514 515define inreg float @test_call_libfunc(float %arg0, float %arg1) {516entry:517 %0 = tail call inreg float @cosf(float %arg1)518 %1 = tail call inreg float @sinf(float %arg0)519 %2 = fmul float %0, %1520 ret float %2521}522 523declare inreg float @cosf(float %arg) readnone nounwind524declare inreg float @sinf(float %arg) readnone nounwind525