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1; RUN: llc < %s -mtriple=sparcv9 -mattr=+popc -disable-sparc-delay-filler -disable-sparc-leaf-proc | FileCheck %s2; RUN: llc < %s -mtriple=sparcv9 -mattr=+popc | FileCheck %s -check-prefix=OPT3; RUN: llc %s -mtriple=sparcv9 -mattr=+popc -filetype=null4 5; CHECK-LABEL: ret2:6; CHECK: mov %i1, %i07 8; OPT-LABEL: ret2:9; OPT: retl10; OPT: mov %o1, %o011define i64 @ret2(i64 %a, i64 %b) {12 ret i64 %b13}14 15; CHECK: shl_imm16; CHECK: sllx %i0, 7, %i017 18; OPT-LABEL: shl_imm:19; OPT: retl20; OPT: sllx %o0, 7, %o021define i64 @shl_imm(i64 %a) {22 %x = shl i64 %a, 723 ret i64 %x24}25 26; CHECK: sra_reg27; CHECK: srax %i0, %i1, %i028 29; OPT-LABEL: sra_reg:30; OPT: retl31; OPT: srax %o0, %o1, %o032define i64 @sra_reg(i64 %a, i64 %b) {33 %x = ashr i64 %a, %b34 ret i64 %x35}36 37; Immediate materialization. Many of these patterns could actually be merged38; into the restore instruction:39;40; restore %g0, %g0, %o041;42; CHECK: ret_imm043; CHECK: mov %g0, %i044 45; OPT: ret_imm046; OPT: retl47; OPT: mov %g0, %o048define i64 @ret_imm0() {49 ret i64 050}51 52; CHECK: ret_simm1353; CHECK: mov -4096, %i054 55; OPT: ret_simm1356; OPT: retl57; OPT: mov -4096, %o058define i64 @ret_simm13() {59 ret i64 -409660}61 62; CHECK: ret_sethi63; CHECK: sethi 4, %i064; CHECK-NOT: or65; CHECK: restore66 67; OPT: ret_sethi68; OPT: retl69; OPT: sethi 4, %o070define i64 @ret_sethi() {71 ret i64 409672}73 74; CHECK: ret_sethi_or75; CHECK: sethi 4, [[R:%[goli][0-7]]]76; CHECK: or [[R]], 1, %i077 78; OPT: ret_sethi_or79; OPT: sethi 4, [[R:%[go][0-7]]]80; OPT: retl81; OPT: or [[R]], 1, %o082 83define i64 @ret_sethi_or() {84 ret i64 409785}86 87; CHECK: ret_nimm3388; CHECK: sethi 4, [[R:%[goli][0-7]]]89; CHECK: xor [[R]], -4, %i090 91; OPT: ret_nimm3392; OPT: sethi 4, [[R:%[go][0-7]]]93; OPT: retl94; OPT: xor [[R]], -4, %o095 96define i64 @ret_nimm33() {97 ret i64 -410098}99 100; CHECK: ret_bigimm101; CHECK: sethi102; CHECK: sethi103define i64 @ret_bigimm() {104 ret i64 6800754272627607872105}106 107; CHECK: ret_bigimm2108; CHECK: sethi 1048576109define i64 @ret_bigimm2() {110 ret i64 4611686018427387904 ; 0x4000000000000000111}112 113; CHECK: reg_reg_alu114; CHECK: add %i0, %i1, [[R0:%[goli][0-7]]]115; CHECK: sub [[R0]], %i2, [[R1:%[goli][0-7]]]116; CHECK: andn [[R1]], %i0, %i0117define i64 @reg_reg_alu(i64 %x, i64 %y, i64 %z) {118 %a = add i64 %x, %y119 %b = sub i64 %a, %z120 %c = xor i64 %x, -1121 %d = and i64 %b, %c122 ret i64 %d123}124 125; CHECK: reg_imm_alu126; CHECK: add %i0, -5, [[R0:%[goli][0-7]]]127; CHECK: xor [[R0]], 2, %i0128define i64 @reg_imm_alu(i64 %x, i64 %y, i64 %z) {129 %a = add i64 %x, -5130 %b = xor i64 %a, 2131 ret i64 %b132}133 134; CHECK: loads135; CHECK: ldx [%i0]136; CHECK: stx %137; CHECK: ld [%i1]138; CHECK: st %139; CHECK: ldsw [%i2]140; CHECK: stx %141; CHECK: ldsh [%i3]142; CHECK: sth %143define i64 @loads(ptr %p, ptr %q, ptr %r, ptr %s) {144 %a = load i64, ptr %p145 %ai = add i64 1, %a146 store i64 %ai, ptr %p147 %b = load i32, ptr %q148 %b2 = zext i32 %b to i64149 %bi = trunc i64 %ai to i32150 store i32 %bi, ptr %q151 %c = load i32, ptr %r152 %c2 = sext i32 %c to i64153 store i64 %ai, ptr %p154 %d = load i16, ptr %s155 %d2 = sext i16 %d to i64156 %di = trunc i64 %ai to i16157 store i16 %di, ptr %s158 159 %x1 = add i64 %a, %b2160 %x2 = add i64 %c2, %d2161 %x3 = add i64 %x1, %x2162 ret i64 %x3163}164 165; CHECK: load_bool166; CHECK: ldub [%i0], %i0167define i64 @load_bool(ptr %p) {168 %a = load i1, ptr %p169 %b = zext i1 %a to i64170 ret i64 %b171}172 173; CHECK: stores174; CHECK: ldx [%i0+8], [[R:%[goli][0-7]]]175; CHECK: stx [[R]], [%i0+16]176; CHECK: st [[R]], [%i1+-8]177; CHECK: sth [[R]], [%i2+40]178; CHECK: stb [[R]], [%i3+-20]179define void @stores(ptr %p, ptr %q, ptr %r, ptr %s) {180 %p1 = getelementptr i64, ptr %p, i64 1181 %p2 = getelementptr i64, ptr %p, i64 2182 %pv = load i64, ptr %p1183 store i64 %pv, ptr %p2184 185 %q2 = getelementptr i32, ptr %q, i32 -2186 %qv = trunc i64 %pv to i32187 store i32 %qv, ptr %q2188 189 %r2 = getelementptr i16, ptr %r, i16 20190 %rv = trunc i64 %pv to i16191 store i16 %rv, ptr %r2192 193 %s2 = getelementptr i8, ptr %s, i8 -20194 %sv = trunc i64 %pv to i8195 store i8 %sv, ptr %s2196 197 ret void198}199 200; CHECK: promote_shifts201; CHECK: ldub [%i0], [[R:%[goli][0-7]]]202; CHECK: sll [[R]], [[R]], %i0203define i8 @promote_shifts(ptr %p) {204 %L24 = load i8, ptr %p205 %L32 = load i8, ptr %p206 %B36 = shl i8 %L24, %L32207 ret i8 %B36208}209 210; CHECK: multiply211; CHECK: mulx %i0, %i1, %i0212define i64 @multiply(i64 %a, i64 %b) {213 %r = mul i64 %a, %b214 ret i64 %r215}216 217; CHECK: signed_divide218; CHECK: sdivx %i0, %i1, %i0219define i64 @signed_divide(i64 %a, i64 %b) {220 %r = sdiv i64 %a, %b221 ret i64 %r222}223 224; CHECK: unsigned_divide225; CHECK: udivx %i0, %i1, %i0226define i64 @unsigned_divide(i64 %a, i64 %b) {227 %r = udiv i64 %a, %b228 ret i64 %r229}230 231define void @access_fi() {232entry:233 %b = alloca [32 x i8], align 1234 %arraydecay = getelementptr inbounds [32 x i8], ptr %b, i64 0, i64 0235 call void @g(ptr %arraydecay) #2236 ret void237}238 239declare void @g(ptr)240 241; CHECK: expand_setcc242; CHECK: movrgz %i0, 1,243define i32 @expand_setcc(i64 %a) {244 %cond = icmp sle i64 %a, 0245 %cast2 = zext i1 %cond to i32246 %RV = sub i32 1, %cast2247 ret i32 %RV248}249 250; CHECK: spill_i64251; CHECK: stx252; CHECK: ldx253define i64 @spill_i64(i64 %x) {254 call void asm sideeffect "", "~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7}"()255 ret i64 %x256}257 258; CHECK: bitcast_i64_f64259; CHECK: std260; CHECK: ldx261define i64 @bitcast_i64_f64(double %x) {262 %y = bitcast double %x to i64263 ret i64 %y264}265 266; CHECK: bitcast_f64_i64267; CHECK: stx268; CHECK: ldd269define double @bitcast_f64_i64(i64 %x) {270 %y = bitcast i64 %x to double271 ret double %y272}273 274; CHECK-LABEL: store_zero:275; CHECK: stx %g0, [%i0]276; CHECK: stx %g0, [%i1+8]277 278; OPT-LABEL: store_zero:279; OPT: stx %g0, [%o0]280; OPT: stx %g0, [%o1+8]281define i64 @store_zero(ptr nocapture %a, ptr nocapture %b) {282entry:283 store i64 0, ptr %a, align 8284 %0 = getelementptr inbounds i64, ptr %b, i32 1285 store i64 0, ptr %0, align 8286 ret i64 0287}288 289; CHECK-LABEL: bit_ops290; CHECK: popc291 292; OPT-LABEL: bit_ops293; OPT: popc294 295define i64 @bit_ops(i64 %arg) {296entry:297 %0 = tail call i64 @llvm.ctpop.i64(i64 %arg)298 %1 = tail call i64 @llvm.ctlz.i64(i64 %arg, i1 true)299 %2 = tail call i64 @llvm.cttz.i64(i64 %arg, i1 true)300 %3 = tail call i64 @llvm.bswap.i64(i64 %arg)301 %4 = add i64 %0, %1302 %5 = add i64 %2, %3303 %6 = add i64 %4, %5304 ret i64 %6305}306 307declare i64 @llvm.ctpop.i64(i64) nounwind readnone308declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone309declare i64 @llvm.cttz.i64(i64, i1) nounwind readnone310declare i64 @llvm.bswap.i64(i64) nounwind readnone311