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1; RUN: llc -mtriple=sparc <%s | FileCheck %s2 3; CHECK-LABEL: test_constraint_r4; CHECK: add %i1, %i0, %i05define i32 @test_constraint_r(i32 %a, i32 %b) {6entry:7 %0 = tail call i32 asm sideeffect "add $2, $1, $0", "=r,r,r"(i32 %a, i32 %b)8 ret i32 %09}10 11;; Check tests only that the constraints are accepted without a compiler failure.12; CHECK-LABEL: test_constraints_nro:13%struct.anon = type { i32, i32 }14@v = external global %struct.anon, align 415define void @test_constraints_nro() {16entry:17 %0 = load i32, ptr @v;18 %1 = load i32, ptr getelementptr inbounds (%struct.anon, ptr @v, i32 0, i32 1);19 tail call void asm sideeffect "", "nro,nro"(i32 %0, i32 %1)20 ret void21}22 23; CHECK-LABEL: test_constraint_I:24; CHECK: add %i0, 1023, %i025define i32 @test_constraint_I(i32 %a) {26entry:27 %0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 1023)28 ret i32 %029}30 31; CHECK-LABEL: test_constraint_I_neg:32; CHECK: add %i0, -4096, %i033define i32 @test_constraint_I_neg(i32 %a) {34entry:35 %0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 -4096)36 ret i32 %037}38 39; CHECK-LABEL: test_constraint_I_largeimm:40; CHECK: sethi 9, [[R0:%[gilo][0-7]]]41; CHECK: or [[R0]], 784, [[R1:%[gilo][0-7]]]42; CHECK: add %i0, [[R1]], %i043define i32 @test_constraint_I_largeimm(i32 %a) {44entry:45 %0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 10000)46 ret i32 %047}48 49; CHECK-LABEL: test_constraint_reg:50; CHECK: ldda [%i1] 43, %g251; CHECK: ldda [%i1] 43, %g452define void @test_constraint_reg(i32 %s, ptr %ptr) {53entry:54 %0 = tail call i64 asm sideeffect "ldda [$1] $2, $0", "={r2},r,n"(ptr %ptr, i32 43)55 %1 = tail call i64 asm sideeffect "ldda [$1] $2, $0", "={g4},r,n"(ptr %ptr, i32 43)56 ret void57}58 59;; Ensure that i64 args to asm are allocated to the IntPair register class.60;; Also checks that there's no register renaming for leaf proc if it has inline asm.61; CHECK-LABEL: test_constraint_r_i64:62; CHECK: mov %i0, %i563; CHECK: sra %i5, 31, %i464; CHECK: std %i4, [%i1]65define i32 @test_constraint_r_i64(i32 %foo, ptr %out, i32 %o) {66entry:67 %conv = sext i32 %foo to i6468 tail call void asm sideeffect "std $0, [$1]", "r,r,~{memory}"(i64 %conv, ptr %out)69 ret i32 %o70}71 72;; Same test without leaf-proc opt73; CHECK-LABEL: test_constraint_r_i64_noleaf:74; CHECK: mov %i0, %i575; CHECK: sra %i5, 31, %i476; CHECK: std %i4, [%i1]77define i32 @test_constraint_r_i64_noleaf(i32 %foo, ptr %out, i32 %o) #0 {78entry:79 %conv = sext i32 %foo to i6480 tail call void asm sideeffect "std $0, [$1]", "r,r,~{memory}"(i64 %conv, ptr %out)81 ret i32 %o82}83attributes #0 = { "frame-pointer"="all" }84 85;; Ensures that tied in and out gets allocated properly.86; CHECK-LABEL: test_i64_inout:87; CHECK: mov 5, %i388; CHECK: mov %g0, %i289; CHECK: xor %i2, %g0, %i290; CHECK: mov %i2, %i091; CHECK: ret92define i64 @test_i64_inout() {93entry:94 %0 = call i64 asm sideeffect "xor $1, %g0, $0", "=r,0,~{i1}"(i64 5);95 ret i64 %096}97 98 99;; Ensures that inline-asm accepts and uses 'f' and 'e' register constraints.100; CHECK-LABEL: fadds:101; CHECK: fadds %f0, %f1, %f0102define float @fadds(float, float) local_unnamed_addr #2 {103entry:104 %2 = tail call float asm sideeffect "fadds $1, $2, $0;", "=f,f,e"(float %0, float %1) #7105 ret float %2106}107 108; CHECK-LABEL: faddd:109; CHECK: faddd %f0, %f2, %f0110define double @faddd(double, double) local_unnamed_addr #2 {111entry:112 %2 = tail call double asm sideeffect "faddd $1, $2, $0;", "=f,f,e"(double %0, double %1) #7113 ret double %2114}115 116; CHECK-LABEL: test_addressing_mode_i64:117; CHECK: std %l0, [%i0]118define void @test_addressing_mode_i64(ptr %out) {119entry:120 call void asm "std %l0, $0", "=*m,r"(ptr elementtype(i64) nonnull %out, i64 0)121 ret void122}123 124; CHECK-LABEL: test_constraint_float_reg:125; CHECK: fadds %f20, %f20, %f20126; CHECK: faddd %f20, %f20, %f20127define void @test_constraint_float_reg() {128entry:129 tail call void asm sideeffect "fadds $0,$1,$2", "{f20},{f20},{f20}"(float 6.0, float 7.0, float 8.0)130 tail call void asm sideeffect "faddd $0,$1,$2", "{f20},{f20},{f20}"(double 9.0, double 10.0, double 11.0)131 ret void132}133 134; CHECK-LABEL: test_constraint_f_e_i32_i64:135; CHECK: ld [%i0+%lo(.LCPI13_0)], %f0136; CHECK: ldd [%i0+%lo(.LCPI13_1)], %f2137; CHECK: fadds %f0, %f0, %f0138; CHECK: faddd %f2, %f2, %f0139 140define void @test_constraint_f_e_i32_i64() {141entry:142 %0 = call float asm sideeffect "fadds $1, $2, $0", "=f,f,e"(i32 0, i32 0)143 %1 = call double asm sideeffect "faddd $1, $2, $0", "=f,f,e"(i64 0, i64 0)144 ret void145}146 147; CHECK-LABEL: test_symbol:148; CHECK: ba,a brtarget149define void @test_symbol() {150Entry:151 call void asm sideeffect "ba,a ${0}", "X"(ptr @brtarget)152 unreachable153}154 155declare void @brtarget()156