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1; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-vulkan-unknown %s -o - | FileCheck %s2; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o - -filetype=obj | spirv-val %}3 4; Test lowering to spir-v backend for various types and scalar/vector5 6; CHECK: OpCapability GroupNonUniformArithmetic7 8; CHECK-DAG: %[[#f16:]] = OpTypeFloat 169; CHECK-DAG: %[[#f32:]] = OpTypeFloat 3210; CHECK-DAG: %[[#uint:]] = OpTypeInt 32 011; CHECK-DAG: %[[#v4_half:]] = OpTypeVector %[[#f16]] 412; CHECK-DAG: %[[#scope:]] = OpConstant %[[#uint]] 313 14; CHECK-LABEL: Begin function test_float15; CHECK: %[[#fexpr:]] = OpFunctionParameter %[[#f32]]16define float @test_float(float %fexpr) {17entry:18; CHECK: %[[#fret:]] = OpGroupNonUniformFMin %[[#f32]] %[[#scope]] Reduce %[[#fexpr]]19 %0 = call float @llvm.spv.wave.reduce.min.f32(float %fexpr)20 ret float %021}22 23; CHECK-LABEL: Begin function test_int_signed24; CHECK: %[[#iexpr:]] = OpFunctionParameter %[[#uint]]25define i32 @test_int_signed(i32 %iexpr) {26entry:27; CHECK: %[[#iret:]] = OpGroupNonUniformSMin %[[#uint]] %[[#scope]] Reduce %[[#iexpr]]28 %0 = call i32 @llvm.spv.wave.reduce.min.i32(i32 %iexpr)29 ret i32 %030}31 32; CHECK-LABEL: Begin function test_int_unsigned33; CHECK: %[[#iexpr:]] = OpFunctionParameter %[[#uint]]34define i32 @test_int_unsigned(i32 %iexpr) {35entry:36; CHECK: %[[#iret:]] = OpGroupNonUniformUMin %[[#uint]] %[[#scope]] Reduce %[[#iexpr]]37 %0 = call i32 @llvm.spv.wave.reduce.umin.i32(i32 %iexpr)38 ret i32 %039}40 41; CHECK-LABEL: Begin function test_vhalf42; CHECK: %[[#vbexpr:]] = OpFunctionParameter %[[#v4_half]]43define <4 x half> @test_vhalf(<4 x half> %vbexpr) {44entry:45; CHECK: %[[#vhalfret:]] = OpGroupNonUniformFMin %[[#v4_half]] %[[#scope]] Reduce %[[#vbexpr]]46 %0 = call <4 x half> @llvm.spv.wave.reduce.min.v4half(<4 x half> %vbexpr)47 ret <4 x half> %048}49 50declare float @llvm.spv.wave.reduce.min.f32(float)51declare i32 @llvm.spv.wave.reduce.min.i32(i32)52declare <4 x half> @llvm.spv.wave.reduce.min.v4half(<4 x half>)53 54declare float @llvm.spv.wave.reduce.umin.f32(float)55declare i32 @llvm.spv.wave.reduce.umin.i32(i32)56declare <4 x half> @llvm.spv.wave.reduce.umin.v4half(<4 x half>)57 58