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1; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv1.5-vulkan-unknown %s -o - | FileCheck %s2; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv1.5-vulkan-unknown %s -o - -filetype=obj | spirv-val %}3 4; Test lowering to spir-v backend for various types and scalar/vector5 6; CHECK: Capability Shader7; CHECK: Capability GroupNonUniformShuffle8 9; CHECK-DAG: %[[#uint:]] = OpTypeInt 32 010; CHECK-DAG: %[[#f32:]] = OpTypeFloat 3211; CHECK-DAG: %[[#v4_float:]] = OpTypeVector %[[#f32]] 412; CHECK-DAG: %[[#bool:]] = OpTypeBool13; CHECK-DAG: %[[#v4_bool:]] = OpTypeVector %[[#bool]] 414; CHECK-DAG: %[[#scope:]] = OpConstant %[[#uint]] 315 16; CHECK-LABEL: Begin function test_float17; CHECK: %[[#fexpr:]] = OpFunctionParameter %[[#f32]]18; CHECK: %[[#idx1:]] = OpFunctionParameter %[[#uint]]19define float @test_float(float %fexpr, i32 %idx) {20entry:21; CHECK: %[[#fret:]] = OpGroupNonUniformShuffle %[[#f32]] %[[#scope]] %[[#fexpr]] %[[#idx1]]22 %0 = call float @llvm.spv.wave.readlane.f32(float %fexpr, i32 %idx)23 ret float %024}25 26; CHECK-LABEL: Begin function test_int27; CHECK: %[[#iexpr:]] = OpFunctionParameter %[[#uint]]28; CHECK: %[[#idx2:]] = OpFunctionParameter %[[#uint]]29define i32 @test_int(i32 %iexpr, i32 %idx) {30entry:31; CHECK: %[[#iret:]] = OpGroupNonUniformShuffle %[[#uint]] %[[#scope]] %[[#iexpr]] %[[#idx2]]32 %0 = call i32 @llvm.spv.wave.readlane.i32(i32 %iexpr, i32 %idx)33 ret i32 %034}35 36; CHECK-LABEL: Begin function test_vbool37; CHECK: %[[#vbexpr:]] = OpFunctionParameter %[[#v4_bool]]38; CHECK: %[[#idx3:]] = OpFunctionParameter %[[#uint]]39define <4 x i1> @test_vbool(<4 x i1> %vbexpr, i32 %idx) {40entry:41; CHECK: %[[#vbret:]] = OpGroupNonUniformShuffle %[[#v4_bool]] %[[#scope]] %[[#vbexpr]] %[[#idx3]]42 %0 = call <4 x i1> @llvm.spv.wave.readlane.v4i1(<4 x i1> %vbexpr, i32 %idx)43 ret <4 x i1> %044}45 46; CHECK-LABEL: Begin function test_vfloat47; CHECK: %[[#vfexpr:]] = OpFunctionParameter %[[#v4_float]]48; CHECK: %[[#idx4:]] = OpFunctionParameter %[[#uint]]49define <4 x float> @test_vfloat(<4 x float> %vfexpr, i32 %idx) {50entry:51; CHECK: %[[#vbret:]] = OpGroupNonUniformShuffle %[[#v4_float]] %[[#scope]] %[[#vfexpr]] %[[#idx4]]52 %0 = call <4 x float> @llvm.spv.wave.readlane.v4f32(<4 x float> %vfexpr, i32 %idx)53 ret <4 x float> %054}55 56declare float @llvm.spv.wave.readlane.f32(float, i32)57declare i32 @llvm.spv.wave.readlane.i32(i32, i32)58declare <4 x i1> @llvm.spv.wave.readlane.v4i1(<4 x i1>, i32)59declare <4 x float> @llvm.spv.wave.readlane.v4f32(<4 x float>, i32)60