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1; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv-unknown-vulkan %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-HLSL2; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-OCL3; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan %s -o - -filetype=obj | spirv-val %}4; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}5; Make sure spirv operation function calls for any are generated.6 7; CHECK-HLSL-DAG: OpMemoryModel Logical GLSL4508; CHECK-OCL-DAG: OpMemoryModel Physical32 OpenCL9; CHECK-DAG: OpName %[[#any_bool_arg:]] "a"10; CHECK-DAG: %[[#int_64:]] = OpTypeInt 64 011; CHECK-DAG: %[[#bool:]] = OpTypeBool12; CHECK-DAG: %[[#int_32:]] = OpTypeInt 32 013; CHECK-DAG: %[[#int_16:]] = OpTypeInt 16 014; CHECK-DAG: %[[#float_64:]] = OpTypeFloat 6415; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 3216; CHECK-DAG: %[[#float_16:]] = OpTypeFloat 1617; CHECK-DAG: %[[#vec4_bool:]] = OpTypeVector %[[#bool]] 418; CHECK-DAG: %[[#vec4_16:]] = OpTypeVector %[[#int_16]] 419; CHECK-DAG: %[[#vec4_32:]] = OpTypeVector %[[#int_32]] 420; CHECK-DAG: %[[#vec4_64:]] = OpTypeVector %[[#int_64]] 421; CHECK-DAG: %[[#vec4_float_16:]] = OpTypeVector %[[#float_16]] 422; CHECK-DAG: %[[#vec4_float_32:]] = OpTypeVector %[[#float_32]] 423; CHECK-DAG: %[[#vec4_float_64:]] = OpTypeVector %[[#float_64]] 424 25; CHECK-HLSL-DAG: %[[#const_i64_0:]] = OpConstant %[[#int_64]] 026; CHECK-HLSL-DAG: %[[#const_i32_0:]] = OpConstant %[[#int_32]] 027; CHECK-HLSL-DAG: %[[#const_i16_0:]] = OpConstant %[[#int_16]] 028; CHECK-HLSL-DAG: %[[#const_f64_0:]] = OpConstant %[[#float_64]] 029; CHECK-HLSL-DAG: %[[#const_f32_0:]] = OpConstant %[[#float_32]] 030; CHECK-HLSL-DAG: %[[#const_f16_0:]] = OpConstant %[[#float_16]] 031; CHECK-HLSL-DAG: %[[#vec4_const_zeros_i16:]] = OpConstantComposite %[[#vec4_16]] %[[#const_i16_0]] %[[#const_i16_0]] %[[#const_i16_0]] %[[#const_i16_0]]32; CHECK-HLSL-DAG: %[[#vec4_const_zeros_i32:]] = OpConstantComposite %[[#vec4_32]] %[[#const_i32_0]] %[[#const_i32_0]] %[[#const_i32_0]] %[[#const_i32_0]]33; CHECK-HLSL-DAG: %[[#vec4_const_zeros_i64:]] = OpConstantComposite %[[#vec4_64]] %[[#const_i64_0]] %[[#const_i64_0]] %[[#const_i64_0]] %[[#const_i64_0]]34; CHECK-HLSL-DAG: %[[#vec4_const_zeros_f16:]] = OpConstantComposite %[[#vec4_float_16]] %[[#const_f16_0]] %[[#const_f16_0]] %[[#const_f16_0]] %[[#const_f16_0]]35; CHECK-HLSL-DAG: %[[#vec4_const_zeros_f32:]] = OpConstantComposite %[[#vec4_float_32]] %[[#const_f32_0]] %[[#const_f32_0]] %[[#const_f32_0]] %[[#const_f32_0]]36; CHECK-HLSL-DAG: %[[#vec4_const_zeros_f64:]] = OpConstantComposite %[[#vec4_float_64]] %[[#const_f64_0]] %[[#const_f64_0]] %[[#const_f64_0]] %[[#const_f64_0]]37 38; CHECK-OCL-DAG: %[[#const_i64_0:]] = OpConstantNull %[[#int_64]]39; CHECK-OCL-DAG: %[[#const_i32_0:]] = OpConstantNull %[[#int_32]]40; CHECK-OCL-DAG: %[[#const_i16_0:]] = OpConstantNull %[[#int_16]]41; CHECK-OCL-DAG: %[[#const_f64_0:]] = OpConstantNull %[[#float_64]] 42; CHECK-OCL-DAG: %[[#const_f32_0:]] = OpConstantNull %[[#float_32]]43; CHECK-OCL-DAG: %[[#const_f16_0:]] = OpConstantNull %[[#float_16]]44; CHECK-OCL-DAG: %[[#vec4_const_zeros_i16:]] = OpConstantNull %[[#vec4_16]]45; CHECK-OCL-DAG: %[[#vec4_const_zeros_i32:]] = OpConstantNull %[[#vec4_32]]46; CHECK-OCL-DAG: %[[#vec4_const_zeros_i64:]] = OpConstantNull %[[#vec4_64]]47; CHECK-OCL-DAG: %[[#vec4_const_zeros_f16:]] = OpConstantNull %[[#vec4_float_16]]48; CHECK-OCL-DAG: %[[#vec4_const_zeros_f32:]] = OpConstantNull %[[#vec4_float_32]]49; CHECK-OCL-DAG: %[[#vec4_const_zeros_f64:]] = OpConstantNull %[[#vec4_float_64]]50 51define noundef i1 @any_int64_t(i64 noundef %p0) {52entry:53 ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]54 ; CHECK: %[[#]] = OpINotEqual %[[#bool]] %[[#arg0]] %[[#const_i64_0]]55 %hlsl.any = call i1 @llvm.spv.any.i64(i64 %p0)56 ret i1 %hlsl.any57}58 59 60define noundef i1 @any_int(i32 noundef %p0) {61entry:62 ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]63 ; CHECK: %[[#]] = OpINotEqual %[[#bool]] %[[#arg0]] %[[#const_i32_0]]64 %hlsl.any = call i1 @llvm.spv.any.i32(i32 %p0)65 ret i1 %hlsl.any66}67 68 69define noundef i1 @any_int16_t(i16 noundef %p0) {70entry:71 ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]72 ; CHECK: %[[#]] = OpINotEqual %[[#bool]] %[[#arg0]] %[[#const_i16_0]]73 %hlsl.any = call i1 @llvm.spv.any.i16(i16 %p0)74 ret i1 %hlsl.any75}76 77define noundef i1 @any_double(double noundef %p0) {78entry:79 ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]80 ; CHECK: %[[#]] = OpFOrdNotEqual %[[#bool]] %[[#arg0]] %[[#const_f64_0]]81 %hlsl.any = call i1 @llvm.spv.any.f64(double %p0)82 ret i1 %hlsl.any83}84 85 86define noundef i1 @any_float(float noundef %p0) {87entry:88 ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]89 ; CHECK: %[[#]] = OpFOrdNotEqual %[[#bool]] %[[#arg0]] %[[#const_f32_0]]90 %hlsl.any = call i1 @llvm.spv.any.f32(float %p0)91 ret i1 %hlsl.any92}93 94 95define noundef i1 @any_half(half noundef %p0) {96entry:97 ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]98 ; CHECK: %[[#]] = OpFOrdNotEqual %[[#bool]] %[[#arg0]] %[[#const_f16_0]]99 %hlsl.any = call i1 @llvm.spv.any.f16(half %p0)100 ret i1 %hlsl.any101}102 103 104define noundef i1 @any_bool4(<4 x i1> noundef %p0) {105entry:106 ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#vec4_bool]]107 ; CHECK: %[[#]] = OpAny %[[#bool]] %[[#arg0]]108 %hlsl.any = call i1 @llvm.spv.any.v4i1(<4 x i1> %p0)109 ret i1 %hlsl.any110}111 112define noundef i1 @any_short4(<4 x i16> noundef %p0) {113entry:114 ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]115 ; CHECK: %[[#shortVecNotEq:]] = OpINotEqual %[[#vec4_bool]] %[[#arg0]] %[[#vec4_const_zeros_i16]]116 ; CHECK: %[[#]] = OpAny %[[#bool]] %[[#shortVecNotEq]]117 %hlsl.any = call i1 @llvm.spv.any.v4i16(<4 x i16> %p0)118 ret i1 %hlsl.any119}120 121define noundef i1 @any_int4(<4 x i32> noundef %p0) {122entry:123 ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]124 ; CHECK: %[[#i32VecNotEq:]] = OpINotEqual %[[#vec4_bool]] %[[#arg0]] %[[#vec4_const_zeros_i32]]125 ; CHECK: %[[#]] = OpAny %[[#bool]] %[[#i32VecNotEq]]126 %hlsl.any = call i1 @llvm.spv.any.v4i32(<4 x i32> %p0)127 ret i1 %hlsl.any128}129 130define noundef i1 @any_int64_t4(<4 x i64> noundef %p0) {131entry:132 ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]133 ; CHECK: %[[#i64VecNotEq:]] = OpINotEqual %[[#vec4_bool]] %[[#arg0]] %[[#vec4_const_zeros_i64]]134 ; CHECK: %[[#]] = OpAny %[[#bool]] %[[#i64VecNotEq]]135 %hlsl.any = call i1 @llvm.spv.any.v4i64(<4 x i64> %p0)136 ret i1 %hlsl.any137}138 139define noundef i1 @any_half4(<4 x half> noundef %p0) {140entry:141 ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]142 ; CHECK: %[[#f16VecNotEq:]] = OpFOrdNotEqual %[[#vec4_bool]] %[[#arg0]] %[[#vec4_const_zeros_f16]]143 ; CHECK: %[[#]] = OpAny %[[#bool]] %[[#f16VecNotEq]]144 %hlsl.any = call i1 @llvm.spv.any.v4f16(<4 x half> %p0)145 ret i1 %hlsl.any146}147 148define noundef i1 @any_float4(<4 x float> noundef %p0) {149entry:150 ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]151 ; CHECK: %[[#f32VecNotEq:]] = OpFOrdNotEqual %[[#vec4_bool]] %[[#arg0]] %[[#vec4_const_zeros_f32]]152 ; CHECK: %[[#]] = OpAny %[[#bool]] %[[#f32VecNotEq]]153 %hlsl.any = call i1 @llvm.spv.any.v4f32(<4 x float> %p0)154 ret i1 %hlsl.any155}156 157define noundef i1 @any_double4(<4 x double> noundef %p0) {158entry:159 ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]160 ; CHECK: %[[#f64VecNotEq:]] = OpFOrdNotEqual %[[#vec4_bool]] %[[#arg0]] %[[#vec4_const_zeros_f64]]161 ; CHECK: %[[#]] = OpAny %[[#bool]] %[[#f64VecNotEq]]162 %hlsl.any = call i1 @llvm.spv.any.v4f64(<4 x double> %p0)163 ret i1 %hlsl.any164}165 166define noundef i1 @any_bool(i1 noundef %a) {167entry:168 ; CHECK: %[[#any_bool_arg:]] = OpFunctionParameter %[[#bool]]169 ; CHECK: OpReturnValue %[[#any_bool_arg]]170 %hlsl.any = call i1 @llvm.spv.any.i1(i1 %a)171 ret i1 %hlsl.any172}173 174declare i1 @llvm.spv.any.v4f16(<4 x half>)175declare i1 @llvm.spv.any.v4f32(<4 x float>)176declare i1 @llvm.spv.any.v4f64(<4 x double>)177declare i1 @llvm.spv.any.v4i1(<4 x i1>)178declare i1 @llvm.spv.any.v4i16(<4 x i16>)179declare i1 @llvm.spv.any.v4i32(<4 x i32>)180declare i1 @llvm.spv.any.v4i64(<4 x i64>)181declare i1 @llvm.spv.any.i1(i1)182declare i1 @llvm.spv.any.i16(i16)183declare i1 @llvm.spv.any.i32(i32)184declare i1 @llvm.spv.any.i64(i64)185declare i1 @llvm.spv.any.f16(half)186declare i1 @llvm.spv.any.f32(float)187declare i1 @llvm.spv.any.f64(double)188