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1; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s2; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}3 4; CHECK-DAG: OpName %[[#test_int32_double_conversion:]] "test_int32_double_conversion"5; CHECK-DAG: %[[#int:]] = OpTypeInt 32 06; CHECK-DAG: %[[#v8i32:]] = OpTypeVector %[[#int]] 87; CHECK-DAG: %[[#v4i32:]] = OpTypeVector %[[#int]] 48; CHECK-DAG: %[[#ptr_func_v8i32:]] = OpTypePointer Function %[[#v8i32]]9 10; CHECK-DAG: OpName %[[#test_v3f64_conversion:]] "test_v3f64_conversion"11; CHECK-DAG: %[[#double:]] = OpTypeFloat 6412; CHECK-DAG: %[[#v3f64:]] = OpTypeVector %[[#double]] 313; CHECK-DAG: %[[#ptr_func_v3f64:]] = OpTypePointer Function %[[#v3f64]]14; CHECK-DAG: %[[#v4f64:]] = OpTypeVector %[[#double]] 415 16define spir_kernel void @test_int32_double_conversion(ptr %G_vec) {17; CHECK: %[[#test_int32_double_conversion]] = OpFunction18; CHECK: %[[#param:]] = OpFunctionParameter %[[#ptr_func_v8i32]]19entry:20 ; CHECK: %[[#LOAD:]] = OpLoad %[[#v8i32]] %[[#param]]21 ; CHECK: %[[#SHUF1:]] = OpVectorShuffle %[[#v4i32]] %[[#LOAD]] %{{[a-zA-Z0-9_]+}} 0 2 4 622 ; CHECK: %[[#SHUF2:]] = OpVectorShuffle %[[#v4i32]] %[[#LOAD]] %{{[a-zA-Z0-9_]+}} 1 3 5 723 ; CHECK: %[[#SHUF3:]] = OpVectorShuffle %[[#v8i32]] %[[#SHUF1]] %[[#SHUF2]] 0 4 1 5 2 6 3 724 ; CHECK: OpStore %[[#param]] %[[#SHUF3]]25 26 %0 = load <8 x i32>, ptr %G_vec27 %1 = shufflevector <8 x i32> %0, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>28 %2 = shufflevector <8 x i32> %0, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>29 %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>30 store <8 x i32> %3, ptr %G_vec31 ret void32}33 34define spir_kernel void @test_v3f64_conversion(ptr %G_vec) {35; CHECK: %[[#test_v3f64_conversion:]] = OpFunction36; CHECK: %[[#param_v3f64:]] = OpFunctionParameter %[[#ptr_func_v3f64]]37entry:38 ; CHECK: %[[#LOAD:]] = OpLoad %[[#v3f64]] %[[#param_v3f64]]39 %0 = load <3 x double>, ptr %G_vec40 41 ; The 6-element vector is not legal. It get expanded to 8.42 ; CHECK: %[[#EXTRACT1:]] = OpCompositeExtract %[[#double]] %[[#LOAD]] 043 ; CHECK: %[[#EXTRACT2:]] = OpCompositeExtract %[[#double]] %[[#LOAD]] 144 ; CHECK: %[[#EXTRACT3:]] = OpCompositeExtract %[[#double]] %[[#LOAD]] 245 ; CHECK: %[[#CONSTRUCT1:]] = OpCompositeConstruct %[[#v4f64]] %[[#EXTRACT1]] %[[#EXTRACT2]] %[[#EXTRACT3]] %{{[a-zA-Z0-9_]+}}46 ; CHECK: %[[#BITCAST1:]] = OpBitcast %[[#v8i32]] %[[#CONSTRUCT1]]47 %1 = bitcast <3 x double> %0 to <6 x i32>48 49 ; CHECK: %[[#SHUFFLE1:]] = OpVectorShuffle %[[#v8i32]] %[[#BITCAST1]] %{{[a-zA-Z0-9_]+}} 0 2 4 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF50 %2 = shufflevector <6 x i32> %1, <6 x i32> poison, <3 x i32> <i32 0, i32 2, i32 4>51 52 ; CHECK: %[[#SHUFFLE2:]] = OpVectorShuffle %[[#v8i32]] %[[#BITCAST1]] %{{[a-zA-Z0-9_]+}} 1 3 5 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF53 %3 = shufflevector <6 x i32> %1, <6 x i32> poison, <3 x i32> <i32 1, i32 3, i32 5>54 55 ; CHECK: %[[#SHUFFLE3:]] = OpVectorShuffle %[[#v8i32]] %[[#SHUFFLE1]] %[[#SHUFFLE2]] 0 8 1 9 2 10 0xFFFFFFFF 0xFFFFFFFF56 %4 = shufflevector <3 x i32> %2, <3 x i32> %3, <6 x i32> <i32 0, i32 3, i32 1, i32 4, i32 2, i32 5>57 58 ; CHECK: %[[#BITCAST2:]] = OpBitcast %[[#v4f64]] %[[#SHUFFLE3]]59 ; CHECK: %[[#EXTRACT10:]] = OpCompositeExtract %[[#double]] %[[#BITCAST2]] 060 ; CHECK: %[[#EXTRACT11:]] = OpCompositeExtract %[[#double]] %[[#BITCAST2]] 161 ; CHECK: %[[#EXTRACT12:]] = OpCompositeExtract %[[#double]] %[[#BITCAST2]] 262 ; CHECK: %[[#CONSTRUCT3:]] = OpCompositeConstruct %[[#v3f64]] %[[#EXTRACT10]] %[[#EXTRACT11]] %[[#EXTRACT12]]63 %5 = bitcast <6 x i32> %4 to <3 x double>64 65 ; CHECK: OpStore %[[#param_v3f64]] %[[#CONSTRUCT3]]66 store <3 x double> %5, ptr %G_vec67 ret void68}69 70